include/opcode/arm.h

   1 /* ARM assembler/disassembler support.
   2    Copyright (C) 2004-2015 Free Software Foundation, Inc.
   3
   4    This file is part of GDB and GAS.
   5
   6    GDB and GAS are free software; you can redistribute it and/or
   7    modify it under the terms of the GNU General Public License as
   8    published by the Free Software Foundation; either version 3, or (at
   9    your option) any later version.
  10
  11    GDB and GAS are distributed in the hope that it will be useful, but
  12    WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14    General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with GDB or GAS; see the file COPYING3.  If not, write to the
  18    Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21 /* The following bitmasks control CPU extensions:  */
  22 #define ARM_EXT_V1       0x00000001     /* All processors (core set).  */
  23 #define ARM_EXT_V2       0x00000002     /* Multiply instructions.  */
  24 #define ARM_EXT_V2S      0x00000004     /* SWP instructions.       */
  25 #define ARM_EXT_V3       0x00000008     /* MSR MRS.                */
  26 #define ARM_EXT_V3M      0x00000010     /* Allow long multiplies.  */
  27 #define ARM_EXT_V4       0x00000020     /* Allow half word loads.  */
  28 #define ARM_EXT_V4T      0x00000040     /* Thumb.                  */
  29 #define ARM_EXT_V5       0x00000080     /* Allow CLZ, etc.         */
  30 #define ARM_EXT_V5T      0x00000100     /* Improved interworking.  */
  31 #define ARM_EXT_V5ExP    0x00000200     /* DSP core set.           */
  32 #define ARM_EXT_V5E      0x00000400     /* DSP Double transfers.   */
  33 #define ARM_EXT_V5J      0x00000800     /* Jazelle extension.      */
  34 #define ARM_EXT_V6       0x00001000     /* ARM V6.                 */
  35 #define ARM_EXT_V6K      0x00002000     /* ARM V6K.                */
  36 /*                       0x00004000        Was ARM V6Z.            */
  37 #define ARM_EXT_V8       0x00004000     /* is now ARMv8.           */
  38 #define ARM_EXT_V6T2     0x00008000     /* Thumb-2.                */
  39 #define ARM_EXT_DIV      0x00010000     /* Integer division.       */
  40 /* The 'M' in Arm V7M stands for Microcontroller.
  41    On earlier architecture variants it stands for Multiply.  */
  42 #define ARM_EXT_V5E_NOTM 0x00020000     /* Arm V5E but not Arm V7M. */
  43 #define ARM_EXT_V6_NOTM  0x00040000     /* Arm V6 but not Arm V7M. */
  44 #define ARM_EXT_V7       0x00080000     /* Arm V7.                 */
  45 #define ARM_EXT_V7A      0x00100000     /* Arm V7A.                */
  46 #define ARM_EXT_V7R      0x00200000     /* Arm V7R.                */
  47 #define ARM_EXT_V7M      0x00400000     /* Arm V7M.                */
  48 #define ARM_EXT_V6M      0x00800000     /* ARM V6M.                 */
  49 #define ARM_EXT_BARRIER  0x01000000     /* DSB/DMB/ISB.             */
  50 #define ARM_EXT_THUMB_MSR 0x02000000    /* Thumb MSR/MRS.           */
  51 #define ARM_EXT_V6_DSP 0x04000000       /* ARM v6 (DSP-related),
  52                                            not in v7-M.  */
  53 #define ARM_EXT_MP       0x08000000     /* Multiprocessing Extensions.  */
  54 #define ARM_EXT_SEC      0x10000000     /* Security extensions.  */
  55 #define ARM_EXT_OS       0x20000000     /* OS Extensions.  */
  56 #define ARM_EXT_ADIV     0x40000000     /* Integer divide extensions in ARM
  57                                            state.  */
  58 #define ARM_EXT_VIRT     0x80000000     /* Virtualization extensions.  */
  59
  60 #define ARM_EXT2_PAN     0x00000001     /* PAN extension.  */
  61
  62 /* Co-processor space extensions.  */
  63 #define ARM_CEXT_XSCALE   0x00000001    /* Allow MIA etc.          */
  64 #define ARM_CEXT_MAVERICK 0x00000002    /* Use Cirrus/DSP coprocessor.  */
  65 #define ARM_CEXT_IWMMXT   0x00000004    /* Intel Wireless MMX technology coprocessor.   */
  66 #define ARM_CEXT_IWMMXT2  0x00000008    /* Intel Wireless MMX technology coprocessor version 2.   */
  67
  68 #define FPU_ENDIAN_PURE  0x80000000     /* Pure-endian doubles.       */
  69 #define FPU_ENDIAN_BIG   0              /* Double words-big-endian.   */
  70 #define FPU_FPA_EXT_V1   0x40000000     /* Base FPA instruction set.  */
  71 #define FPU_FPA_EXT_V2   0x20000000     /* LFM/SFM.                   */
  72 #define FPU_MAVERICK     0x10000000     /* Cirrus Maverick.           */
  73 #define FPU_VFP_EXT_V1xD 0x08000000     /* Base VFP instruction set.  */
  74 #define FPU_VFP_EXT_V1   0x04000000     /* Double-precision insns.    */
  75 #define FPU_VFP_EXT_V2   0x02000000     /* ARM10E VFPr1.              */
  76 #define FPU_VFP_EXT_V3xD 0x01000000     /* VFPv3 single-precision.    */
  77 #define FPU_VFP_EXT_V3   0x00800000     /* VFPv3 double-precision.    */
  78 #define FPU_NEON_EXT_V1  0x00400000     /* Neon (SIMD) insns.         */
  79 #define FPU_VFP_EXT_D32  0x00200000     /* Registers D16-D31.         */
  80 #define FPU_VFP_EXT_FP16 0x00100000     /* Half-precision extensions. */
  81 #define FPU_NEON_EXT_FMA 0x00080000     /* Neon fused multiply-add    */
  82 #define FPU_VFP_EXT_FMA  0x00040000     /* VFP fused multiply-add     */
  83 #define FPU_VFP_EXT_ARMV8 0x00020000    /* Double-precision FP for ARMv8.  */
  84 #define FPU_NEON_EXT_ARMV8 0x00010000   /* Neon for ARMv8.  */
  85 #define FPU_CRYPTO_EXT_ARMV8 0x00008000 /* Crypto for ARMv8.  */
  86 #define CRC_EXT_ARMV8    0x00004000     /* CRC32 for ARMv8.  */
  87 #define FPU_VFP_EXT_ARMV8xD 0x00002000  /* Single-precision FP for ARMv8.  */
  88
  89 /* Architectures are the sum of the base and extensions.  The ARM ARM (rev E)
  90    defines the following: ARMv3, ARMv3M, ARMv4xM, ARMv4, ARMv4TxM, ARMv4T,
  91    ARMv5xM, ARMv5, ARMv5TxM, ARMv5T, ARMv5TExP, ARMv5TE.  To these we add
  92    three more to cover cores prior to ARM6.  Finally, there are cores which
  93    implement further extensions in the co-processor space.  */
  94 #define ARM_AEXT_V1                       ARM_EXT_V1
  95 #define ARM_AEXT_V2     (ARM_AEXT_V1    | ARM_EXT_V2)
  96 #define ARM_AEXT_V2S    (ARM_AEXT_V2    | ARM_EXT_V2S)
  97 #define ARM_AEXT_V3     (ARM_AEXT_V2S   | ARM_EXT_V3)
  98 #define ARM_AEXT_V3M    (ARM_AEXT_V3    | ARM_EXT_V3M)
  99 #define ARM_AEXT_V4xM   (ARM_AEXT_V3    | ARM_EXT_V4)
 100 #define ARM_AEXT_V4     (ARM_AEXT_V3M   | ARM_EXT_V4)
 101 #define ARM_AEXT_V4TxM  (ARM_AEXT_V4xM  | ARM_EXT_V4T)
 102 #define ARM_AEXT_V4T    (ARM_AEXT_V4    | ARM_EXT_V4T)
 103 #define ARM_AEXT_V5xM   (ARM_AEXT_V4xM  | ARM_EXT_V5)
 104 #define ARM_AEXT_V5     (ARM_AEXT_V4    | ARM_EXT_V5)
 105 #define ARM_AEXT_V5TxM  (ARM_AEXT_V5xM  | ARM_EXT_V4T | ARM_EXT_V5T)
 106 #define ARM_AEXT_V5T    (ARM_AEXT_V5    | ARM_EXT_V4T | ARM_EXT_V5T)
 107 #define ARM_AEXT_V5TExP (ARM_AEXT_V5T   | ARM_EXT_V5ExP)
 108 #define ARM_AEXT_V5TE   (ARM_AEXT_V5TExP | ARM_EXT_V5E)
 109 #define ARM_AEXT_V5TEJ  (ARM_AEXT_V5TE  | ARM_EXT_V5J)
 110 #define ARM_AEXT_V6     (ARM_AEXT_V5TEJ | ARM_EXT_V6)
 111 #define ARM_AEXT_V6K    (ARM_AEXT_V6    | ARM_EXT_V6K)
 112 #define ARM_AEXT_V6Z    (ARM_AEXT_V6K   | ARM_EXT_SEC)
 113 #define ARM_AEXT_V6ZK   (ARM_AEXT_V6K   | ARM_EXT_SEC)
 114 #define ARM_AEXT_V6T2   (ARM_AEXT_V6 \
 115     | ARM_EXT_V6T2 | ARM_EXT_V6_NOTM | ARM_EXT_THUMB_MSR \
 116     | ARM_EXT_V6_DSP )
 117 #define ARM_AEXT_V6KT2  (ARM_AEXT_V6T2 | ARM_EXT_V6K)
 118 #define ARM_AEXT_V6ZT2  (ARM_AEXT_V6T2 | ARM_EXT_SEC)
 119 #define ARM_AEXT_V6ZKT2 (ARM_AEXT_V6T2 | ARM_EXT_V6K | ARM_EXT_SEC)
 120 #define ARM_AEXT_V7_ARM (ARM_AEXT_V6KT2 | ARM_EXT_V7 | ARM_EXT_BARRIER)
 121 #define ARM_AEXT_V7A    (ARM_AEXT_V7_ARM | ARM_EXT_V7A)
 122 #define ARM_AEXT_V7VE   (ARM_AEXT_V7A  | ARM_EXT_DIV | ARM_EXT_ADIV \
 123     | ARM_EXT_VIRT | ARM_EXT_SEC | ARM_EXT_MP)
 124 #define ARM_AEXT_V7R    (ARM_AEXT_V7_ARM | ARM_EXT_V7R | ARM_EXT_DIV)
 125 #define ARM_AEXT_NOTM \
 126   (ARM_AEXT_V4 | ARM_EXT_V5ExP | ARM_EXT_V5J | ARM_EXT_V6_NOTM \
 127    | ARM_EXT_V6_DSP )
 128 #define ARM_AEXT_V6M_ONLY \
 129   ((ARM_EXT_BARRIER | ARM_EXT_V6M | ARM_EXT_THUMB_MSR) & ~(ARM_AEXT_NOTM))
 130 #define ARM_AEXT_V6M \
 131   ((ARM_AEXT_V6K | ARM_AEXT_V6M_ONLY) & ~(ARM_AEXT_NOTM))
 132 #define ARM_AEXT_V6SM (ARM_AEXT_V6M | ARM_EXT_OS)
 133 #define ARM_AEXT_V7M \
 134   ((ARM_AEXT_V7_ARM | ARM_EXT_V6M | ARM_EXT_V7M | ARM_EXT_DIV) \
 135    & ~(ARM_AEXT_NOTM))
 136 #define ARM_AEXT_V7 (ARM_AEXT_V7A & ARM_AEXT_V7R & ARM_AEXT_V7M)
 137 #define ARM_AEXT_V7EM \
 138   (ARM_AEXT_V7M | ARM_EXT_V5ExP | ARM_EXT_V6_DSP)
 139 #define ARM_AEXT_V8A \
 140   (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC | ARM_EXT_DIV | ARM_EXT_ADIV \
 141    | ARM_EXT_VIRT | ARM_EXT_V8)
 142
 143 /* Processors with specific extensions in the co-processor space.  */
 144 #define ARM_ARCH_XSCALE ARM_FEATURE_LOW (ARM_AEXT_V5TE, ARM_CEXT_XSCALE)
 145 #define ARM_ARCH_IWMMXT \
 146  ARM_FEATURE_LOW (ARM_AEXT_V5TE, ARM_CEXT_XSCALE | ARM_CEXT_IWMMXT)
 147 #define ARM_ARCH_IWMMXT2        \
 148  ARM_FEATURE_LOW (ARM_AEXT_V5TE, ARM_CEXT_XSCALE | ARM_CEXT_IWMMXT \
 149                   | ARM_CEXT_IWMMXT2)
 150
 151 #define FPU_VFP_V1xD    (FPU_VFP_EXT_V1xD | FPU_ENDIAN_PURE)
 152 #define FPU_VFP_V1      (FPU_VFP_V1xD | FPU_VFP_EXT_V1)
 153 #define FPU_VFP_V2      (FPU_VFP_V1 | FPU_VFP_EXT_V2)
 154 #define FPU_VFP_V3D16   (FPU_VFP_V2 | FPU_VFP_EXT_V3xD | FPU_VFP_EXT_V3)
 155 #define FPU_VFP_V3      (FPU_VFP_V3D16 | FPU_VFP_EXT_D32)
 156 #define FPU_VFP_V3xD    (FPU_VFP_V1xD | FPU_VFP_EXT_V2 | FPU_VFP_EXT_V3xD)
 157 #define FPU_VFP_V4D16   (FPU_VFP_V3D16 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA)
 158 #define FPU_VFP_V4      (FPU_VFP_V3 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA)
 159 #define FPU_VFP_V4_SP_D16 (FPU_VFP_V3xD | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA)
 160 #define FPU_VFP_V5D16   (FPU_VFP_V4D16 | FPU_VFP_EXT_ARMV8xD | FPU_VFP_EXT_ARMV8)
 161 #define FPU_VFP_V5_SP_D16 (FPU_VFP_V4_SP_D16 | FPU_VFP_EXT_ARMV8xD)
 162 #define FPU_VFP_ARMV8   (FPU_VFP_V4 | FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)
 163 #define FPU_NEON_ARMV8  (FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA | FPU_NEON_EXT_ARMV8)
 164 #define FPU_CRYPTO_ARMV8 (FPU_CRYPTO_EXT_ARMV8)
 165 #define FPU_VFP_HARD    (FPU_VFP_EXT_V1xD | FPU_VFP_EXT_V1 | FPU_VFP_EXT_V2 \
 166                          | FPU_VFP_EXT_V3xD | FPU_VFP_EXT_FMA | FPU_NEON_EXT_FMA \
 167                          | FPU_VFP_EXT_V3 | FPU_NEON_EXT_V1 | FPU_VFP_EXT_D32)
 168 #define FPU_FPA         (FPU_FPA_EXT_V1 | FPU_FPA_EXT_V2)
 169
 170 /* Deprecated.  */
 171 #define FPU_ARCH_VFP    ARM_FEATURE_COPROC (FPU_ENDIAN_PURE)
 172
 173 #define FPU_ARCH_FPE    ARM_FEATURE_COPROC (FPU_FPA_EXT_V1)
 174 #define FPU_ARCH_FPA    ARM_FEATURE_COPROC (FPU_FPA)
 175
 176 #define FPU_ARCH_VFP_V1xD ARM_FEATURE_COPROC (FPU_VFP_V1xD)
 177 #define FPU_ARCH_VFP_V1   ARM_FEATURE_COPROC (FPU_VFP_V1)
 178 #define FPU_ARCH_VFP_V2   ARM_FEATURE_COPROC (FPU_VFP_V2)
 179 #define FPU_ARCH_VFP_V3D16      ARM_FEATURE_COPROC (FPU_VFP_V3D16)
 180 #define FPU_ARCH_VFP_V3D16_FP16 \
 181   ARM_FEATURE_COPROC (FPU_VFP_V3D16 | FPU_VFP_EXT_FP16)
 182 #define FPU_ARCH_VFP_V3   ARM_FEATURE_COPROC (FPU_VFP_V3)
 183 #define FPU_ARCH_VFP_V3_FP16    ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_VFP_EXT_FP16)
 184 #define FPU_ARCH_VFP_V3xD       ARM_FEATURE_COPROC (FPU_VFP_V3xD)
 185 #define FPU_ARCH_VFP_V3xD_FP16  ARM_FEATURE_COPROC (FPU_VFP_V3xD \
 186                                                  | FPU_VFP_EXT_FP16)
 187 #define FPU_ARCH_NEON_V1  ARM_FEATURE_COPROC (FPU_NEON_EXT_V1)
 188 #define FPU_ARCH_VFP_V3_PLUS_NEON_V1 \
 189   ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_NEON_EXT_V1)
 190 #define FPU_ARCH_NEON_FP16 \
 191   ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_NEON_EXT_V1 | FPU_VFP_EXT_FP16)
 192 #define FPU_ARCH_VFP_HARD ARM_FEATURE_COPROC (FPU_VFP_HARD)
 193 #define FPU_ARCH_VFP_V4 ARM_FEATURE_COPROC (FPU_VFP_V4)
 194 #define FPU_ARCH_VFP_V4D16 ARM_FEATURE_COPROC (FPU_VFP_V4D16)
 195 #define FPU_ARCH_VFP_V4_SP_D16 ARM_FEATURE_COPROC (FPU_VFP_V4_SP_D16)
 196 #define FPU_ARCH_VFP_V5D16 ARM_FEATURE_COPROC (FPU_VFP_V5D16)
 197 #define FPU_ARCH_VFP_V5_SP_D16 ARM_FEATURE_COPROC (FPU_VFP_V5_SP_D16)
 198 #define FPU_ARCH_NEON_VFP_V4 \
 199   ARM_FEATURE_COPROC (FPU_VFP_V4 | FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA)
 200 #define FPU_ARCH_VFP_ARMV8 ARM_FEATURE_COPROC (FPU_VFP_ARMV8)
 201 #define FPU_ARCH_NEON_VFP_ARMV8 ARM_FEATURE_COPROC (FPU_NEON_ARMV8 \
 202                                                  | FPU_VFP_ARMV8)
 203 #define FPU_ARCH_CRYPTO_NEON_VFP_ARMV8 \
 204   ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8 | FPU_NEON_ARMV8 | FPU_VFP_ARMV8)
 205 #define ARCH_CRC_ARMV8 ARM_FEATURE_COPROC (CRC_EXT_ARMV8)
 206
 207 #define FPU_ARCH_ENDIAN_PURE ARM_FEATURE_COPROC (FPU_ENDIAN_PURE)
 208
 209 #define FPU_ARCH_MAVERICK ARM_FEATURE_COPROC (FPU_MAVERICK)
 210
 211 #define ARM_ARCH_V1     ARM_FEATURE_CORE_LOW (ARM_AEXT_V1)
 212 #define ARM_ARCH_V2     ARM_FEATURE_CORE_LOW (ARM_AEXT_V2)
 213 #define ARM_ARCH_V2S    ARM_FEATURE_CORE_LOW (ARM_AEXT_V2S)
 214 #define ARM_ARCH_V3     ARM_FEATURE_CORE_LOW (ARM_AEXT_V3)
 215 #define ARM_ARCH_V3M    ARM_FEATURE_CORE_LOW (ARM_AEXT_V3M)
 216 #define ARM_ARCH_V4xM   ARM_FEATURE_CORE_LOW (ARM_AEXT_V4xM)
 217 #define ARM_ARCH_V4     ARM_FEATURE_CORE_LOW (ARM_AEXT_V4)
 218 #define ARM_ARCH_V4TxM  ARM_FEATURE_CORE_LOW (ARM_AEXT_V4TxM)
 219 #define ARM_ARCH_V4T    ARM_FEATURE_CORE_LOW (ARM_AEXT_V4T)
 220 #define ARM_ARCH_V5xM   ARM_FEATURE_CORE_LOW (ARM_AEXT_V5xM)
 221 #define ARM_ARCH_V5     ARM_FEATURE_CORE_LOW (ARM_AEXT_V5)
 222 #define ARM_ARCH_V5TxM  ARM_FEATURE_CORE_LOW (ARM_AEXT_V5TxM)
 223 #define ARM_ARCH_V5T    ARM_FEATURE_CORE_LOW (ARM_AEXT_V5T)
 224 #define ARM_ARCH_V5TExP ARM_FEATURE_CORE_LOW (ARM_AEXT_V5TExP)
 225 #define ARM_ARCH_V5TE   ARM_FEATURE_CORE_LOW (ARM_AEXT_V5TE)
 226 #define ARM_ARCH_V5TEJ  ARM_FEATURE_CORE_LOW (ARM_AEXT_V5TEJ)
 227 #define ARM_ARCH_V6     ARM_FEATURE_CORE_LOW (ARM_AEXT_V6)
 228 #define ARM_ARCH_V6K    ARM_FEATURE_CORE_LOW (ARM_AEXT_V6K)
 229 #define ARM_ARCH_V6Z    ARM_FEATURE_CORE_LOW (ARM_AEXT_V6Z)
 230 #define ARM_ARCH_V6ZK   ARM_FEATURE_CORE_LOW (ARM_AEXT_V6ZK)
 231 #define ARM_ARCH_V6T2   ARM_FEATURE_CORE_LOW (ARM_AEXT_V6T2)
 232 #define ARM_ARCH_V6KT2  ARM_FEATURE_CORE_LOW (ARM_AEXT_V6KT2)
 233 #define ARM_ARCH_V6ZT2  ARM_FEATURE_CORE_LOW (ARM_AEXT_V6ZT2)
 234 #define ARM_ARCH_V6ZKT2 ARM_FEATURE_CORE_LOW (ARM_AEXT_V6ZKT2)
 235 #define ARM_ARCH_V6M    ARM_FEATURE_CORE_LOW (ARM_AEXT_V6M)
 236 #define ARM_ARCH_V6SM   ARM_FEATURE_CORE_LOW (ARM_AEXT_V6SM)
 237 #define ARM_ARCH_V7     ARM_FEATURE_CORE_LOW (ARM_AEXT_V7)
 238 #define ARM_ARCH_V7A    ARM_FEATURE_CORE_LOW (ARM_AEXT_V7A)
 239 #define ARM_ARCH_V7VE   ARM_FEATURE_CORE_LOW (ARM_AEXT_V7VE)
 240 #define ARM_ARCH_V7R    ARM_FEATURE_CORE_LOW (ARM_AEXT_V7R)
 241 #define ARM_ARCH_V7M    ARM_FEATURE_CORE_LOW (ARM_AEXT_V7M)
 242 #define ARM_ARCH_V7EM   ARM_FEATURE_CORE_LOW (ARM_AEXT_V7EM)
 243 #define ARM_ARCH_V8A    ARM_FEATURE_CORE_LOW (ARM_AEXT_V8A)
 244
 245 /* Some useful combinations:  */
 246 #define ARM_ARCH_NONE   ARM_FEATURE_LOW (0, 0)
 247 #define FPU_NONE        ARM_FEATURE_LOW (0, 0)
 248 #define ARM_ANY         ARM_FEATURE (-1, -1, 0) /* Any basic core.  */
 249 #define ARM_FEATURE_ALL ARM_FEATURE (-1, -1, -1)/* All CPU and FPU features.  */
 250 #define FPU_ANY_HARD    ARM_FEATURE_COPROC (FPU_FPA | FPU_VFP_HARD | FPU_MAVERICK)
 251 #define ARM_ARCH_THUMB2 ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2 | ARM_EXT_V7 \
 252                                               | ARM_EXT_V7A | ARM_EXT_V7R \
 253                                               | ARM_EXT_V7M | ARM_EXT_DIV)
 254 /* v7-a+sec.  */
 255 #define ARM_ARCH_V7A_SEC ARM_FEATURE_CORE_LOW (ARM_AEXT_V7A | ARM_EXT_SEC)
 256 /* v7-a+mp+sec.  */
 257 #define ARM_ARCH_V7A_MP_SEC \
 258                         ARM_FEATURE_CORE_LOW (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC)
 259 /* v7-r+idiv.  */
 260 #define ARM_ARCH_V7R_IDIV       ARM_FEATURE_CORE_LOW (ARM_AEXT_V7R | ARM_EXT_ADIV)
 261 /* Features that are present in v6M and v6S-M but not other v6 cores.  */
 262 #define ARM_ARCH_V6M_ONLY ARM_FEATURE_CORE_LOW (ARM_AEXT_V6M_ONLY)
 263 /* v8-a+fp.  */
 264 #define ARM_ARCH_V8A_FP ARM_FEATURE_LOW (ARM_AEXT_V8A, FPU_ARCH_VFP_ARMV8)
 265 /* v8-a+simd (implies fp).  */
 266 #define ARM_ARCH_V8A_SIMD       ARM_FEATURE_LOW (ARM_AEXT_V8A, \
 267                                              FPU_ARCH_NEON_VFP_ARMV8)
 268 /* v8-a+crypto (implies simd+fp).  */
 269 #define ARM_ARCH_V8A_CRYPTOV1   ARM_FEATURE_LOW (ARM_AEXT_V8A, \
 270                                              FPU_ARCH_CRYPTO_NEON_VFP_ARMV8)
 271
 272 /* There are too many feature bits to fit in a single word, so use a
 273    structure.  For simplicity we put all core features in array CORE
 274    and everything else in the other.  All the bits in element core[0]
 275    have been occupied, so new feature should use bit in element core[1]
 276    and use macro ARM_FEATURE to initialize the feature set variable.  */
 277 typedef struct
 278 {
 279   unsigned long core[2];
 280   unsigned long coproc;
 281 } arm_feature_set;
 282
 283 #define ARM_CPU_HAS_FEATURE(CPU,FEAT) \
 284   (((CPU).core[0] & (FEAT).core[0]) != 0 \
 285    || ((CPU).core[1] & (FEAT).core[1]) != 0 \
 286    || ((CPU).coproc & (FEAT).coproc) != 0)
 287
 288 #define ARM_CPU_IS_ANY(CPU) \
 289   ((CPU).core[0] == ((arm_feature_set)ARM_ANY).core[0] \
 290    && (CPU).core[1] == ((arm_feature_set)ARM_ANY).core[1])
 291
 292 #define ARM_MERGE_FEATURE_SETS(TARG,F1,F2)      \
 293   do {                                          \
 294     (TARG).core[0] = (F1).core[0] | (F2).core[0];\
 295     (TARG).core[1] = (F1).core[1] | (F2).core[1];\
 296     (TARG).coproc = (F1).coproc | (F2).coproc;  \
 297   } while (0)
 298
 299 #define ARM_CLEAR_FEATURE(TARG,F1,F2)           \
 300   do {                                          \
 301     (TARG).core[0] = (F1).core[0] &~ (F2).core[0];\
 302     (TARG).core[1] = (F1).core[1] &~ (F2).core[1];\
 303     (TARG).coproc = (F1).coproc &~ (F2).coproc; \
 304   } while (0)
 305
 306 #define ARM_FEATURE_COPY(F1, F2)                \
 307   do {                                          \
 308       (F1).core[0] = (F2).core[0];              \
 309       (F1).core[1] = (F2).core[1];              \
 310       (F1).coproc = (F2).coproc;                \
 311   } while (0)
 312
 313 #define ARM_FEATURE_EQUAL(T1,T2)                \
 314   ((T1).core[0] == (T2).core[0]                 \
 315    && (T1).core[1] == (T2).core[1]              \
 316    && (T1).coproc == (T2).coproc)
 317
 318 #define ARM_FEATURE_ZERO(T)                     \
 319   ((T).core[0] == 0 && (T).core[1] == 0 && (T).coproc == 0)
 320
 321 #define ARM_FEATURE_CORE_EQUAL(T1, T2)          \
 322   ((T1).core[0] == (T2).core[0] && (T1).core[1] == (T2).core[1])
 323
 324 #define ARM_FEATURE_LOW(core, coproc) {{(core), 0}, (coproc)}
 325 #define ARM_FEATURE_CORE_LOW(core) {{(core), 0}, 0}
 326 #define ARM_FEATURE_CORE_HIGH(core) {{0, (core)}, 0}
 327 #define ARM_FEATURE_COPROC(coproc) {{0, 0}, (coproc)}
 328 #define ARM_FEATURE(core1, core2, coproc) {{(core1), (core2)}, (coproc)}