Consolidate Thumb-1/Thumb-2 ISA detection
[external/binutils.git] / include / opcode / arm.h
1 /* ARM assembler/disassembler support.
2    Copyright (C) 2004-2015 Free Software Foundation, Inc.
3
4    This file is part of GDB and GAS.
5
6    GDB and GAS are free software; you can redistribute it and/or
7    modify it under the terms of the GNU General Public License as
8    published by the Free Software Foundation; either version 3, or (at
9    your option) any later version.
10
11    GDB and GAS are distributed in the hope that it will be useful, but
12    WITHOUT ANY WARRANTY; without even the implied warranty of
13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14    General Public License for more details.
15
16    You should have received a copy of the GNU General Public License
17    along with GDB or GAS; see the file COPYING3.  If not, write to the
18    Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
19    MA 02110-1301, USA.  */
20
21 /* The following bitmasks control CPU extensions:  */
22 #define ARM_EXT_V1       0x00000001     /* All processors (core set).  */
23 #define ARM_EXT_V2       0x00000002     /* Multiply instructions.  */
24 #define ARM_EXT_V2S      0x00000004     /* SWP instructions.       */
25 #define ARM_EXT_V3       0x00000008     /* MSR MRS.                */
26 #define ARM_EXT_V3M      0x00000010     /* Allow long multiplies.  */
27 #define ARM_EXT_V4       0x00000020     /* Allow half word loads.  */
28 #define ARM_EXT_V4T      0x00000040     /* Thumb.                  */
29 #define ARM_EXT_V5       0x00000080     /* Allow CLZ, etc.         */
30 #define ARM_EXT_V5T      0x00000100     /* Improved interworking.  */
31 #define ARM_EXT_V5ExP    0x00000200     /* DSP core set.           */
32 #define ARM_EXT_V5E      0x00000400     /* DSP Double transfers.   */
33 #define ARM_EXT_V5J      0x00000800     /* Jazelle extension.      */
34 #define ARM_EXT_V6       0x00001000     /* ARM V6.                 */
35 #define ARM_EXT_V6K      0x00002000     /* ARM V6K.                */
36 /*                       0x00004000        Was ARM V6Z.            */
37 #define ARM_EXT_V8       0x00004000     /* is now ARMv8.           */
38 #define ARM_EXT_V6T2     0x00008000     /* Thumb-2.                */
39 #define ARM_EXT_DIV      0x00010000     /* Integer division.       */
40 /* The 'M' in Arm V7M stands for Microcontroller.
41    On earlier architecture variants it stands for Multiply.  */
42 #define ARM_EXT_V5E_NOTM 0x00020000     /* Arm V5E but not Arm V7M. */
43 #define ARM_EXT_V6_NOTM  0x00040000     /* Arm V6 but not Arm V7M. */
44 #define ARM_EXT_V7       0x00080000     /* Arm V7.                 */
45 #define ARM_EXT_V7A      0x00100000     /* Arm V7A.                */
46 #define ARM_EXT_V7R      0x00200000     /* Arm V7R.                */
47 #define ARM_EXT_V7M      0x00400000     /* Arm V7M.                */
48 #define ARM_EXT_V6M      0x00800000     /* ARM V6M.                 */
49 #define ARM_EXT_BARRIER  0x01000000     /* DSB/DMB/ISB.             */
50 #define ARM_EXT_THUMB_MSR 0x02000000    /* Thumb MSR/MRS.           */
51 #define ARM_EXT_V6_DSP 0x04000000       /* ARM v6 (DSP-related),
52                                            not in v7-M.  */
53 #define ARM_EXT_MP       0x08000000     /* Multiprocessing Extensions.  */
54 #define ARM_EXT_SEC      0x10000000     /* Security extensions.  */
55 #define ARM_EXT_OS       0x20000000     /* OS Extensions.  */
56 #define ARM_EXT_ADIV     0x40000000     /* Integer divide extensions in ARM 
57                                            state.  */
58 #define ARM_EXT_VIRT     0x80000000     /* Virtualization extensions.  */
59
60 #define ARM_EXT2_PAN     0x00000001     /* PAN extension.  */
61 #define ARM_EXT2_V8_2A   0x00000002     /* ARM V8.2A.  */
62
63 /* Co-processor space extensions.  */
64 #define ARM_CEXT_XSCALE   0x00000001    /* Allow MIA etc.          */
65 #define ARM_CEXT_MAVERICK 0x00000002    /* Use Cirrus/DSP coprocessor.  */
66 #define ARM_CEXT_IWMMXT   0x00000004    /* Intel Wireless MMX technology coprocessor.   */
67 #define ARM_CEXT_IWMMXT2  0x00000008    /* Intel Wireless MMX technology coprocessor version 2.   */
68
69 #define FPU_ENDIAN_PURE  0x80000000     /* Pure-endian doubles.       */
70 #define FPU_ENDIAN_BIG   0              /* Double words-big-endian.   */
71 #define FPU_FPA_EXT_V1   0x40000000     /* Base FPA instruction set.  */
72 #define FPU_FPA_EXT_V2   0x20000000     /* LFM/SFM.                   */
73 #define FPU_MAVERICK     0x10000000     /* Cirrus Maverick.           */
74 #define FPU_VFP_EXT_V1xD 0x08000000     /* Base VFP instruction set.  */
75 #define FPU_VFP_EXT_V1   0x04000000     /* Double-precision insns.    */
76 #define FPU_VFP_EXT_V2   0x02000000     /* ARM10E VFPr1.              */
77 #define FPU_VFP_EXT_V3xD 0x01000000     /* VFPv3 single-precision.    */
78 #define FPU_VFP_EXT_V3   0x00800000     /* VFPv3 double-precision.    */
79 #define FPU_NEON_EXT_V1  0x00400000     /* Neon (SIMD) insns.         */
80 #define FPU_VFP_EXT_D32  0x00200000     /* Registers D16-D31.         */
81 #define FPU_VFP_EXT_FP16 0x00100000     /* Half-precision extensions. */
82 #define FPU_NEON_EXT_FMA 0x00080000     /* Neon fused multiply-add    */
83 #define FPU_VFP_EXT_FMA  0x00040000     /* VFP fused multiply-add     */
84 #define FPU_VFP_EXT_ARMV8 0x00020000    /* Double-precision FP for ARMv8.  */
85 #define FPU_NEON_EXT_ARMV8 0x00010000   /* Neon for ARMv8.  */
86 #define FPU_CRYPTO_EXT_ARMV8 0x00008000 /* Crypto for ARMv8.  */
87 #define CRC_EXT_ARMV8    0x00004000     /* CRC32 for ARMv8.  */
88 #define FPU_VFP_EXT_ARMV8xD 0x00002000  /* Single-precision FP for ARMv8.  */
89 #define FPU_NEON_EXT_RDMA 0x00001000     /* v8.1 Adv.SIMD extensions.  */
90
91 /* Architectures are the sum of the base and extensions.  The ARM ARM (rev E)
92    defines the following: ARMv3, ARMv3M, ARMv4xM, ARMv4, ARMv4TxM, ARMv4T,
93    ARMv5xM, ARMv5, ARMv5TxM, ARMv5T, ARMv5TExP, ARMv5TE.  To these we add
94    three more to cover cores prior to ARM6.  Finally, there are cores which
95    implement further extensions in the co-processor space.  */
96 #define ARM_AEXT_V1                       ARM_EXT_V1
97 #define ARM_AEXT_V2     (ARM_AEXT_V1    | ARM_EXT_V2)
98 #define ARM_AEXT_V2S    (ARM_AEXT_V2    | ARM_EXT_V2S)
99 #define ARM_AEXT_V3     (ARM_AEXT_V2S   | ARM_EXT_V3)
100 #define ARM_AEXT_V3M    (ARM_AEXT_V3    | ARM_EXT_V3M)
101 #define ARM_AEXT_V4xM   (ARM_AEXT_V3    | ARM_EXT_V4)
102 #define ARM_AEXT_V4     (ARM_AEXT_V3M   | ARM_EXT_V4)
103 #define ARM_AEXT_V4TxM  (ARM_AEXT_V4xM  | ARM_EXT_V4T)
104 #define ARM_AEXT_V4T    (ARM_AEXT_V4    | ARM_EXT_V4T)
105 #define ARM_AEXT_V5xM   (ARM_AEXT_V4xM  | ARM_EXT_V5)
106 #define ARM_AEXT_V5     (ARM_AEXT_V4    | ARM_EXT_V5)
107 #define ARM_AEXT_V5TxM  (ARM_AEXT_V5xM  | ARM_EXT_V4T | ARM_EXT_V5T)
108 #define ARM_AEXT_V5T    (ARM_AEXT_V5    | ARM_EXT_V4T | ARM_EXT_V5T)
109 #define ARM_AEXT_V5TExP (ARM_AEXT_V5T   | ARM_EXT_V5ExP)
110 #define ARM_AEXT_V5TE   (ARM_AEXT_V5TExP | ARM_EXT_V5E)
111 #define ARM_AEXT_V5TEJ  (ARM_AEXT_V5TE  | ARM_EXT_V5J)
112 #define ARM_AEXT_V6     (ARM_AEXT_V5TEJ | ARM_EXT_V6)
113 #define ARM_AEXT_V6K    (ARM_AEXT_V6    | ARM_EXT_V6K)
114 #define ARM_AEXT_V6Z    (ARM_AEXT_V6K   | ARM_EXT_SEC)
115 #define ARM_AEXT_V6KZ   (ARM_AEXT_V6K   | ARM_EXT_SEC)
116 #define ARM_AEXT_V6T2   (ARM_AEXT_V6 \
117     | ARM_EXT_V6T2 | ARM_EXT_V6_NOTM | ARM_EXT_THUMB_MSR \
118     | ARM_EXT_V6_DSP )
119 #define ARM_AEXT_V6KT2  (ARM_AEXT_V6T2 | ARM_EXT_V6K)
120 #define ARM_AEXT_V6ZT2  (ARM_AEXT_V6T2 | ARM_EXT_SEC)
121 #define ARM_AEXT_V6KZT2 (ARM_AEXT_V6T2 | ARM_EXT_V6K | ARM_EXT_SEC)
122 #define ARM_AEXT_V7_ARM (ARM_AEXT_V6KT2 | ARM_EXT_V7 | ARM_EXT_BARRIER)
123 #define ARM_AEXT_V7A    (ARM_AEXT_V7_ARM | ARM_EXT_V7A)
124 #define ARM_AEXT_V7VE   (ARM_AEXT_V7A  | ARM_EXT_DIV | ARM_EXT_ADIV \
125     | ARM_EXT_VIRT | ARM_EXT_SEC | ARM_EXT_MP)
126 #define ARM_AEXT_V7R    (ARM_AEXT_V7_ARM | ARM_EXT_V7R | ARM_EXT_DIV)
127 #define ARM_AEXT_NOTM \
128   (ARM_AEXT_V4 | ARM_EXT_V5ExP | ARM_EXT_V5J | ARM_EXT_V6_NOTM \
129    | ARM_EXT_V6_DSP )
130 #define ARM_AEXT_V6M_ONLY \
131   ((ARM_EXT_BARRIER | ARM_EXT_V6M | ARM_EXT_THUMB_MSR) & ~(ARM_AEXT_NOTM))
132 #define ARM_AEXT_V6M \
133   ((ARM_AEXT_V6K | ARM_AEXT_V6M_ONLY) & ~(ARM_AEXT_NOTM))
134 #define ARM_AEXT_V6SM (ARM_AEXT_V6M | ARM_EXT_OS)
135 #define ARM_AEXT_V7M \
136   ((ARM_AEXT_V7_ARM | ARM_EXT_V6M | ARM_EXT_V7M | ARM_EXT_DIV) \
137    & ~(ARM_AEXT_NOTM))
138 #define ARM_AEXT_V7 (ARM_AEXT_V7A & ARM_AEXT_V7R & ARM_AEXT_V7M)
139 #define ARM_AEXT_V7EM \
140   (ARM_AEXT_V7M | ARM_EXT_V5ExP | ARM_EXT_V6_DSP)
141 #define ARM_AEXT_V8A \
142   (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC | ARM_EXT_DIV | ARM_EXT_ADIV \
143    | ARM_EXT_VIRT | ARM_EXT_V8)
144
145 /* Processors with specific extensions in the co-processor space.  */
146 #define ARM_ARCH_XSCALE ARM_FEATURE_LOW (ARM_AEXT_V5TE, ARM_CEXT_XSCALE)
147 #define ARM_ARCH_IWMMXT \
148  ARM_FEATURE_LOW (ARM_AEXT_V5TE, ARM_CEXT_XSCALE | ARM_CEXT_IWMMXT)
149 #define ARM_ARCH_IWMMXT2        \
150  ARM_FEATURE_LOW (ARM_AEXT_V5TE, ARM_CEXT_XSCALE | ARM_CEXT_IWMMXT \
151                   | ARM_CEXT_IWMMXT2)
152
153 #define FPU_VFP_V1xD    (FPU_VFP_EXT_V1xD | FPU_ENDIAN_PURE)
154 #define FPU_VFP_V1      (FPU_VFP_V1xD | FPU_VFP_EXT_V1)
155 #define FPU_VFP_V2      (FPU_VFP_V1 | FPU_VFP_EXT_V2)
156 #define FPU_VFP_V3D16   (FPU_VFP_V2 | FPU_VFP_EXT_V3xD | FPU_VFP_EXT_V3)
157 #define FPU_VFP_V3      (FPU_VFP_V3D16 | FPU_VFP_EXT_D32)
158 #define FPU_VFP_V3xD    (FPU_VFP_V1xD | FPU_VFP_EXT_V2 | FPU_VFP_EXT_V3xD)
159 #define FPU_VFP_V4D16   (FPU_VFP_V3D16 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA)
160 #define FPU_VFP_V4      (FPU_VFP_V3 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA)
161 #define FPU_VFP_V4_SP_D16 (FPU_VFP_V3xD | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA)
162 #define FPU_VFP_V5D16   (FPU_VFP_V4D16 | FPU_VFP_EXT_ARMV8xD | FPU_VFP_EXT_ARMV8)
163 #define FPU_VFP_V5_SP_D16 (FPU_VFP_V4_SP_D16 | FPU_VFP_EXT_ARMV8xD)
164 #define FPU_VFP_ARMV8   (FPU_VFP_V4 | FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)
165 #define FPU_NEON_ARMV8  (FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA | FPU_NEON_EXT_ARMV8)
166 #define FPU_CRYPTO_ARMV8 (FPU_CRYPTO_EXT_ARMV8)
167 #define FPU_VFP_HARD    (FPU_VFP_EXT_V1xD | FPU_VFP_EXT_V1 | FPU_VFP_EXT_V2 \
168                          | FPU_VFP_EXT_V3xD | FPU_VFP_EXT_FMA | FPU_NEON_EXT_FMA \
169                          | FPU_VFP_EXT_V3 | FPU_NEON_EXT_V1 | FPU_VFP_EXT_D32)
170 #define FPU_FPA         (FPU_FPA_EXT_V1 | FPU_FPA_EXT_V2)
171
172 /* Deprecated.  */
173 #define FPU_ARCH_VFP    ARM_FEATURE_COPROC (FPU_ENDIAN_PURE)
174
175 #define FPU_ARCH_FPE    ARM_FEATURE_COPROC (FPU_FPA_EXT_V1)
176 #define FPU_ARCH_FPA    ARM_FEATURE_COPROC (FPU_FPA)
177
178 #define FPU_ARCH_VFP_V1xD ARM_FEATURE_COPROC (FPU_VFP_V1xD)
179 #define FPU_ARCH_VFP_V1   ARM_FEATURE_COPROC (FPU_VFP_V1)
180 #define FPU_ARCH_VFP_V2   ARM_FEATURE_COPROC (FPU_VFP_V2)
181 #define FPU_ARCH_VFP_V3D16      ARM_FEATURE_COPROC (FPU_VFP_V3D16)
182 #define FPU_ARCH_VFP_V3D16_FP16 \
183   ARM_FEATURE_COPROC (FPU_VFP_V3D16 | FPU_VFP_EXT_FP16)
184 #define FPU_ARCH_VFP_V3   ARM_FEATURE_COPROC (FPU_VFP_V3)
185 #define FPU_ARCH_VFP_V3_FP16    ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_VFP_EXT_FP16)
186 #define FPU_ARCH_VFP_V3xD       ARM_FEATURE_COPROC (FPU_VFP_V3xD)
187 #define FPU_ARCH_VFP_V3xD_FP16  ARM_FEATURE_COPROC (FPU_VFP_V3xD \
188                                                  | FPU_VFP_EXT_FP16)
189 #define FPU_ARCH_NEON_V1  ARM_FEATURE_COPROC (FPU_NEON_EXT_V1)
190 #define FPU_ARCH_VFP_V3_PLUS_NEON_V1 \
191   ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_NEON_EXT_V1)
192 #define FPU_ARCH_NEON_FP16 \
193   ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_NEON_EXT_V1 | FPU_VFP_EXT_FP16)
194 #define FPU_ARCH_VFP_HARD ARM_FEATURE_COPROC (FPU_VFP_HARD)
195 #define FPU_ARCH_VFP_V4 ARM_FEATURE_COPROC (FPU_VFP_V4)
196 #define FPU_ARCH_VFP_V4D16 ARM_FEATURE_COPROC (FPU_VFP_V4D16)
197 #define FPU_ARCH_VFP_V4_SP_D16 ARM_FEATURE_COPROC (FPU_VFP_V4_SP_D16)
198 #define FPU_ARCH_VFP_V5D16 ARM_FEATURE_COPROC (FPU_VFP_V5D16)
199 #define FPU_ARCH_VFP_V5_SP_D16 ARM_FEATURE_COPROC (FPU_VFP_V5_SP_D16)
200 #define FPU_ARCH_NEON_VFP_V4 \
201   ARM_FEATURE_COPROC (FPU_VFP_V4 | FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA)
202 #define FPU_ARCH_VFP_ARMV8 ARM_FEATURE_COPROC (FPU_VFP_ARMV8)
203 #define FPU_ARCH_NEON_VFP_ARMV8 ARM_FEATURE_COPROC (FPU_NEON_ARMV8 \
204                                                  | FPU_VFP_ARMV8)
205 #define FPU_ARCH_CRYPTO_NEON_VFP_ARMV8 \
206   ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8 | FPU_NEON_ARMV8 | FPU_VFP_ARMV8)
207 #define ARCH_CRC_ARMV8 ARM_FEATURE_COPROC (CRC_EXT_ARMV8)
208 #define FPU_ARCH_NEON_VFP_ARMV8_1 \
209   ARM_FEATURE_COPROC (FPU_NEON_ARMV8                             \
210                       | FPU_VFP_ARMV8                            \
211                       | FPU_NEON_EXT_RDMA)
212 #define FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1 \
213   ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8 | FPU_NEON_ARMV8 | FPU_VFP_ARMV8 \
214                       | FPU_NEON_EXT_RDMA)
215
216
217 #define FPU_ARCH_ENDIAN_PURE ARM_FEATURE_COPROC (FPU_ENDIAN_PURE)
218
219 #define FPU_ARCH_MAVERICK ARM_FEATURE_COPROC (FPU_MAVERICK)
220
221 #define ARM_ARCH_V1     ARM_FEATURE_CORE_LOW (ARM_AEXT_V1)
222 #define ARM_ARCH_V2     ARM_FEATURE_CORE_LOW (ARM_AEXT_V2)
223 #define ARM_ARCH_V2S    ARM_FEATURE_CORE_LOW (ARM_AEXT_V2S)
224 #define ARM_ARCH_V3     ARM_FEATURE_CORE_LOW (ARM_AEXT_V3)
225 #define ARM_ARCH_V3M    ARM_FEATURE_CORE_LOW (ARM_AEXT_V3M)
226 #define ARM_ARCH_V4xM   ARM_FEATURE_CORE_LOW (ARM_AEXT_V4xM)
227 #define ARM_ARCH_V4     ARM_FEATURE_CORE_LOW (ARM_AEXT_V4)
228 #define ARM_ARCH_V4TxM  ARM_FEATURE_CORE_LOW (ARM_AEXT_V4TxM)
229 #define ARM_ARCH_V4T    ARM_FEATURE_CORE_LOW (ARM_AEXT_V4T)
230 #define ARM_ARCH_V5xM   ARM_FEATURE_CORE_LOW (ARM_AEXT_V5xM)
231 #define ARM_ARCH_V5     ARM_FEATURE_CORE_LOW (ARM_AEXT_V5)
232 #define ARM_ARCH_V5TxM  ARM_FEATURE_CORE_LOW (ARM_AEXT_V5TxM)
233 #define ARM_ARCH_V5T    ARM_FEATURE_CORE_LOW (ARM_AEXT_V5T)
234 #define ARM_ARCH_V5TExP ARM_FEATURE_CORE_LOW (ARM_AEXT_V5TExP)
235 #define ARM_ARCH_V5TE   ARM_FEATURE_CORE_LOW (ARM_AEXT_V5TE)
236 #define ARM_ARCH_V5TEJ  ARM_FEATURE_CORE_LOW (ARM_AEXT_V5TEJ)
237 #define ARM_ARCH_V6     ARM_FEATURE_CORE_LOW (ARM_AEXT_V6)
238 #define ARM_ARCH_V6K    ARM_FEATURE_CORE_LOW (ARM_AEXT_V6K)
239 #define ARM_ARCH_V6Z    ARM_FEATURE_CORE_LOW (ARM_AEXT_V6Z)
240 #define ARM_ARCH_V6KZ   ARM_FEATURE_CORE_LOW (ARM_AEXT_V6KZ)
241 #define ARM_ARCH_V6T2   ARM_FEATURE_CORE_LOW (ARM_AEXT_V6T2)
242 #define ARM_ARCH_V6KT2  ARM_FEATURE_CORE_LOW (ARM_AEXT_V6KT2)
243 #define ARM_ARCH_V6ZT2  ARM_FEATURE_CORE_LOW (ARM_AEXT_V6ZT2)
244 #define ARM_ARCH_V6KZT2 ARM_FEATURE_CORE_LOW (ARM_AEXT_V6KZT2)
245 #define ARM_ARCH_V6M    ARM_FEATURE_CORE_LOW (ARM_AEXT_V6M)
246 #define ARM_ARCH_V6SM   ARM_FEATURE_CORE_LOW (ARM_AEXT_V6SM)
247 #define ARM_ARCH_V7     ARM_FEATURE_CORE_LOW (ARM_AEXT_V7)
248 #define ARM_ARCH_V7A    ARM_FEATURE_CORE_LOW (ARM_AEXT_V7A)
249 #define ARM_ARCH_V7VE   ARM_FEATURE_CORE_LOW (ARM_AEXT_V7VE)
250 #define ARM_ARCH_V7R    ARM_FEATURE_CORE_LOW (ARM_AEXT_V7R)
251 #define ARM_ARCH_V7M    ARM_FEATURE_CORE_LOW (ARM_AEXT_V7M)
252 #define ARM_ARCH_V7EM   ARM_FEATURE_CORE_LOW (ARM_AEXT_V7EM)
253 #define ARM_ARCH_V8A    ARM_FEATURE_CORE_LOW (ARM_AEXT_V8A)
254 #define ARM_ARCH_V8_1A  ARM_FEATURE (ARM_AEXT_V8A, ARM_EXT2_PAN, \
255                                      CRC_EXT_ARMV8)
256 #define ARM_ARCH_V8_2A  ARM_FEATURE (ARM_AEXT_V8A, \
257                                      ARM_EXT2_PAN | ARM_EXT2_V8_2A,     \
258                                      CRC_EXT_ARMV8)
259
260 /* Some useful combinations:  */
261 #define ARM_ARCH_NONE   ARM_FEATURE_LOW (0, 0)
262 #define FPU_NONE        ARM_FEATURE_LOW (0, 0)
263 #define ARM_ANY         ARM_FEATURE (-1, -1, 0) /* Any basic core.  */
264 #define ARM_FEATURE_ALL ARM_FEATURE (-1, -1, -1)/* All CPU and FPU features.  */
265 #define FPU_ANY_HARD    ARM_FEATURE_COPROC (FPU_FPA | FPU_VFP_HARD | FPU_MAVERICK)
266 /* Extensions containing some Thumb-2 instructions.  If any is present, Thumb
267    ISA is Thumb-2.  */
268 #define ARM_ARCH_THUMB2 ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2 | ARM_EXT_V7 \
269                                               | ARM_EXT_DIV | ARM_EXT_V8)
270 /* v7-a+sec.  */
271 #define ARM_ARCH_V7A_SEC ARM_FEATURE_CORE_LOW (ARM_AEXT_V7A | ARM_EXT_SEC)
272 /* v7-a+mp+sec.  */
273 #define ARM_ARCH_V7A_MP_SEC \
274                         ARM_FEATURE_CORE_LOW (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC)
275 /* v7-r+idiv.  */
276 #define ARM_ARCH_V7R_IDIV       ARM_FEATURE_CORE_LOW (ARM_AEXT_V7R | ARM_EXT_ADIV)
277 /* Features that are present in v6M and v6S-M but not other v6 cores.  */
278 #define ARM_ARCH_V6M_ONLY ARM_FEATURE_CORE_LOW (ARM_AEXT_V6M_ONLY)
279 /* v8-a+fp.  */
280 #define ARM_ARCH_V8A_FP ARM_FEATURE_LOW (ARM_AEXT_V8A, FPU_ARCH_VFP_ARMV8)
281 /* v8-a+simd (implies fp).  */
282 #define ARM_ARCH_V8A_SIMD       ARM_FEATURE_LOW (ARM_AEXT_V8A, \
283                                              FPU_ARCH_NEON_VFP_ARMV8)
284 /* v8-a+crypto (implies simd+fp).  */
285 #define ARM_ARCH_V8A_CRYPTOV1   ARM_FEATURE_LOW (ARM_AEXT_V8A, \
286                                              FPU_ARCH_CRYPTO_NEON_VFP_ARMV8)
287
288 /* v8.1-a+fp.  */
289 #define ARM_ARCH_V8_1A_FP       ARM_FEATURE (ARM_AEXT_V8A, ARM_EXT2_PAN, \
290                                      FPU_ARCH_VFP_ARMV8)
291 /* v8.1-a+simd (implies fp).  */
292 #define ARM_ARCH_V8_1A_SIMD     ARM_FEATURE (ARM_AEXT_V8A, ARM_EXT2_PAN, \
293                                      FPU_ARCH_NEON_VFP_ARMV8_1)
294 /* v8.1-a+crypto (implies simd+fp).  */
295 #define ARM_ARCH_V8_1A_CRYPTOV1   ARM_FEATURE (ARM_AEXT_V8A, ARM_EXT2_PAN, \
296                                                FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1)
297
298
299 /* There are too many feature bits to fit in a single word, so use a
300    structure.  For simplicity we put all core features in array CORE
301    and everything else in the other.  All the bits in element core[0]
302    have been occupied, so new feature should use bit in element core[1]
303    and use macro ARM_FEATURE to initialize the feature set variable.  */
304 typedef struct
305 {
306   unsigned long core[2];
307   unsigned long coproc;
308 } arm_feature_set;
309
310 #define ARM_CPU_HAS_FEATURE(CPU,FEAT) \
311   (((CPU).core[0] & (FEAT).core[0]) != 0 \
312    || ((CPU).core[1] & (FEAT).core[1]) != 0 \
313    || ((CPU).coproc & (FEAT).coproc) != 0)
314
315 #define ARM_CPU_IS_ANY(CPU) \
316   ((CPU).core[0] == ((arm_feature_set)ARM_ANY).core[0] \
317    && (CPU).core[1] == ((arm_feature_set)ARM_ANY).core[1])
318
319 #define ARM_MERGE_FEATURE_SETS(TARG,F1,F2)      \
320   do {                                          \
321     (TARG).core[0] = (F1).core[0] | (F2).core[0];\
322     (TARG).core[1] = (F1).core[1] | (F2).core[1];\
323     (TARG).coproc = (F1).coproc | (F2).coproc;  \
324   } while (0)
325
326 #define ARM_CLEAR_FEATURE(TARG,F1,F2)           \
327   do {                                          \
328     (TARG).core[0] = (F1).core[0] &~ (F2).core[0];\
329     (TARG).core[1] = (F1).core[1] &~ (F2).core[1];\
330     (TARG).coproc = (F1).coproc &~ (F2).coproc; \
331   } while (0)
332
333 #define ARM_FEATURE_COPY(F1, F2)                \
334   do {                                          \
335       (F1).core[0] = (F2).core[0];              \
336       (F1).core[1] = (F2).core[1];              \
337       (F1).coproc = (F2).coproc;                \
338   } while (0)
339
340 #define ARM_FEATURE_EQUAL(T1,T2)                \
341   ((T1).core[0] == (T2).core[0]                 \
342    && (T1).core[1] == (T2).core[1]              \
343    && (T1).coproc == (T2).coproc)
344
345 #define ARM_FEATURE_ZERO(T)                     \
346   ((T).core[0] == 0 && (T).core[1] == 0 && (T).coproc == 0)
347
348 #define ARM_FEATURE_CORE_EQUAL(T1, T2)          \
349   ((T1).core[0] == (T2).core[0] && (T1).core[1] == (T2).core[1])
350
351 #define ARM_FEATURE_LOW(core, coproc) {{(core), 0}, (coproc)}
352 #define ARM_FEATURE_CORE(core1, core2) {{(core1), (core2)}, 0}
353 #define ARM_FEATURE_CORE_LOW(core) {{(core), 0}, 0}
354 #define ARM_FEATURE_CORE_HIGH(core) {{0, (core)}, 0}
355 #define ARM_FEATURE_COPROC(coproc) {{0, 0}, (coproc)}
356 #define ARM_FEATURE(core1, core2, coproc) {{(core1), (core2)}, (coproc)}