1 /* Opcode table for the ARC.
2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
4 Contributed by Claudiu Zissulescu (claziss@synopsys.com)
6 This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
9 GAS/GDB is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GAS/GDB is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GAS or GDB; see the file COPYING3. If not, write to
21 the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
22 MA 02110-1301, USA. */
32 #define MAX_INSN_ARGS 16
36 #define MAX_INSN_FLGS 4
39 /* Instruction Class. */
88 /* Instruction Subclass. */
109 QUARKSE1 = (1U << 16),
110 QUARKSE2 = (1U << 17),
123 /* At most one flag from the set of flags can appear in the
125 F_CLASS_OPTIONAL = (1 << 0),
127 /* Exactly one from from the set of flags must appear in the
129 F_CLASS_REQUIRED = (1 << 1),
131 /* The conditional code can be extended over the standard variants
132 via .extCondCode pseudo-op. */
133 F_CLASS_EXTEND = (1 << 2),
135 /* Condition code flag. */
136 F_CLASS_COND = (1 << 3),
138 /* Write back mode. */
139 F_CLASS_WB = (1 << 4),
142 F_CLASS_ZZ = (1 << 5),
145 F_CLASS_IMPLICIT = (1 << 6)
148 /* The opcode table is an array of struct arc_opcode. */
151 /* The opcode name. */
154 /* The opcode itself. Those bits which will be filled in with
155 operands are zeroes. */
156 unsigned long long opcode;
158 /* The opcode mask. This is used by the disassembler. This is a
159 mask containing ones indicating those bits which must match the
160 opcode field, and zeroes indicating those bits which need not
161 match (and are presumably filled in by operands). */
162 unsigned long long mask;
164 /* One bit flags for the opcode. These are primarily used to
165 indicate specific processors and environments support the
166 instructions. The defined values are listed below. */
169 /* The instruction class. This is used by gdb. */
170 insn_class_t insn_class;
172 /* The instruction subclass. */
173 insn_subclass_t subclass;
175 /* An array of operand codes. Each code is an index into the
176 operand table. They appear in the order which the operands must
177 appear in assembly code, and are terminated by a zero. */
178 unsigned char operands[MAX_INSN_ARGS + 1];
180 /* An array of flag codes. Each code is an index into the flag
181 table. They appear in the order which the flags must appear in
182 assembly code, and are terminated by a zero. */
183 unsigned char flags[MAX_INSN_FLGS + 1];
186 /* The table itself is sorted by major opcode number, and is otherwise
187 in the order in which the disassembler should consider
189 extern const struct arc_opcode arc_opcodes[];
191 /* Return length of an instruction represented by OPCODE, in bytes. */
192 extern int arc_opcode_len (const struct arc_opcode *opcode);
194 /* CPU Availability. */
195 #define ARC_OPCODE_NONE 0x0000
196 #define ARC_OPCODE_ARC600 0x0001 /* ARC 600 specific insns. */
197 #define ARC_OPCODE_ARC700 0x0002 /* ARC 700 specific insns. */
198 #define ARC_OPCODE_ARCv2EM 0x0004 /* ARCv2 EM specific insns. */
199 #define ARC_OPCODE_ARCv2HS 0x0008 /* ARCv2 HS specific insns. */
202 #define ARC_OPCODE_ARCALL (ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 \
203 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS)
204 #define ARC_OPCODE_ARCFPX (ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM)
205 #define ARC_OPCODE_ARCV1 (ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700)
206 #define ARC_OPCODE_ARCV2 (ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS)
207 #define ARC_OPCODE_ARCMPY6E (ARC_OPCODE_ARC700 | ARC_OPCODE_ARCV2)
209 /* The operands table is an array of struct arc_operand. */
212 /* The number of bits in the operand. */
215 /* How far the operand is left shifted in the instruction. */
218 /* The default relocation type for this operand. */
219 signed int default_reloc;
221 /* One bit syntax flags. */
224 /* Insertion function. This is used by the assembler. To insert an
225 operand value into an instruction, check this field.
227 If it is NULL, execute
228 i |= (op & ((1 << o->bits) - 1)) << o->shift;
229 (i is the instruction which we are filling in, o is a pointer to
230 this structure, and op is the opcode value; this assumes twos
231 complement arithmetic).
233 If this field is not NULL, then simply call it with the
234 instruction and the operand value. It will return the new value
235 of the instruction. If the ERRMSG argument is not NULL, then if
236 the operand value is illegal, *ERRMSG will be set to a warning
237 string (the operand will be inserted in any case). If the
238 operand value is legal, *ERRMSG will be unchanged (most operands
239 can accept any value). */
240 unsigned long long (*insert) (unsigned long long instruction,
242 const char **errmsg);
244 /* Extraction function. This is used by the disassembler. To
245 extract this operand type from an instruction, check this field.
247 If it is NULL, compute
248 op = ((i) >> o->shift) & ((1 << o->bits) - 1);
249 if ((o->flags & ARC_OPERAND_SIGNED) != 0
250 && (op & (1 << (o->bits - 1))) != 0)
252 (i is the instruction, o is a pointer to this structure, and op
253 is the result; this assumes twos complement arithmetic).
255 If this field is not NULL, then simply call it with the
256 instruction value. It will return the value of the operand. If
257 the INVALID argument is not NULL, *INVALID will be set to
258 TRUE if this operand type can not actually be extracted from
259 this operand (i.e., the instruction does not match). If the
260 operand is valid, *INVALID will not be changed. */
261 long long int (*extract) (unsigned long long instruction,
262 bfd_boolean *invalid);
265 /* Elements in the table are retrieved by indexing with values from
266 the operands field of the arc_opcodes table. */
267 extern const struct arc_operand arc_operands[];
268 extern const unsigned arc_num_operands;
269 extern const unsigned arc_Toperand;
270 extern const unsigned arc_NToperand;
272 /* Values defined for the flags field of a struct arc_operand. */
274 /* This operand does not actually exist in the assembler input. This
275 is used to support extended mnemonics, for which two operands fields
276 are identical. The assembler should call the insert function with
277 any op value. The disassembler should call the extract function,
278 ignore the return value, and check the value placed in the invalid
280 #define ARC_OPERAND_FAKE 0x0001
282 /* This operand names an integer register. */
283 #define ARC_OPERAND_IR 0x0002
285 /* This operand takes signed values. */
286 #define ARC_OPERAND_SIGNED 0x0004
288 /* This operand takes unsigned values. This exists primarily so that
289 a flags value of 0 can be treated as end-of-arguments. */
290 #define ARC_OPERAND_UNSIGNED 0x0008
292 /* This operand takes long immediate values. */
293 #define ARC_OPERAND_LIMM 0x0010
295 /* This operand is identical like the previous one. */
296 #define ARC_OPERAND_DUPLICATE 0x0020
298 /* This operand is PC relative. Used for internal relocs. */
299 #define ARC_OPERAND_PCREL 0x0040
301 /* This operand is truncated. The truncation is done accordingly to
302 operand alignment attribute. */
303 #define ARC_OPERAND_TRUNCATE 0x0080
305 /* This operand is 16bit aligned. */
306 #define ARC_OPERAND_ALIGNED16 0x0100
308 /* This operand is 32bit aligned. */
309 #define ARC_OPERAND_ALIGNED32 0x0200
311 /* This operand can be ignored by matching process if it is not
313 #define ARC_OPERAND_IGNORE 0x0400
315 /* Don't check the range when matching. */
316 #define ARC_OPERAND_NCHK 0x0800
318 /* Mark the braket possition. */
319 #define ARC_OPERAND_BRAKET 0x1000
321 /* Address type operand for NPS400. */
322 #define ARC_OPERAND_ADDRTYPE 0x2000
324 /* Mark the colon position. */
325 #define ARC_OPERAND_COLON 0x4000
327 /* Mask for selecting the type for typecheck purposes. */
328 #define ARC_OPERAND_TYPECHECK_MASK \
330 | ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED \
331 | ARC_OPERAND_UNSIGNED | ARC_OPERAND_BRAKET \
332 | ARC_OPERAND_ADDRTYPE | ARC_OPERAND_COLON)
334 /* Macro to determine if an operand is a fake operand. */
335 #define ARC_OPERAND_IS_FAKE(op) \
336 ((operand->flags & ARC_OPERAND_FAKE) \
337 && !((operand->flags & ARC_OPERAND_BRAKET) \
338 || (operand->flags & ARC_OPERAND_COLON)))
340 /* The flags structure. */
341 struct arc_flag_operand
349 /* The number of bits in the operand. */
352 /* How far the operand is left shifted in the instruction. */
355 /* Available for disassembler. */
356 unsigned char favail;
359 /* The flag operands table. */
360 extern const struct arc_flag_operand arc_flag_operands[];
361 extern const unsigned arc_num_flag_operands;
363 /* The flag's class structure. */
364 struct arc_flag_class
367 flag_class_t flag_class;
369 /* List of valid flags (codes). */
373 extern const struct arc_flag_class arc_flag_classes[];
375 /* Structure for special cases. */
376 struct arc_flag_special
378 /* Name of special case instruction. */
381 /* List of flags applicable for special case instruction. */
385 extern const struct arc_flag_special arc_flag_special_cases[];
386 extern const unsigned arc_num_flag_special;
388 /* Relocation equivalence structure. */
389 struct arc_reloc_equiv_tab
391 const char * name; /* String to lookup. */
392 const char * mnemonic; /* Extra matching condition. */
393 unsigned flags[32]; /* Extra matching condition. */
394 signed int oldreloc; /* Old relocation. */
395 signed int newreloc; /* New relocation. */
398 extern const struct arc_reloc_equiv_tab arc_reloc_equiv[];
399 extern const unsigned arc_num_equiv_tab;
401 /* Structure for operand operations for pseudo/alias instructions. */
402 struct arc_operand_operation
404 /* The index for operand from operand array. */
405 unsigned operand_idx;
407 /* Defines if it needs the operand inserted by the assembler or
408 whether this operand comes from the pseudo instruction's
410 unsigned char needs_insert;
412 /* Count we have to add to the operand. Use negative number to
413 subtract from the operand. Also use this number to add to 0 if
414 the operand needs to be inserted (i.e. needs_insert == 1). */
417 /* Index of the operand to swap with. To be done AFTER applying
419 unsigned swap_operand_idx;
422 /* Structure for pseudo/alias instructions. */
423 struct arc_pseudo_insn
425 /* Mnemonic for pseudo/alias insn. */
426 const char * mnemonic_p;
428 /* Mnemonic for real instruction. */
429 const char * mnemonic_r;
431 /* Flag that will have to be added (if any). */
434 /* Amount of operands. */
435 unsigned operand_cnt;
437 /* Array of operand operations. */
438 struct arc_operand_operation operand[6];
441 extern const struct arc_pseudo_insn arc_pseudo_insns[];
442 extern const unsigned arc_num_pseudo_insn;
444 /* Structure for AUXILIARY registers. */
447 /* Register address. */
450 /* One bit flags for the opcode. These are primarily used to
451 indicate specific processors and environments support the
455 /* AUX register subclass. */
456 insn_subclass_t subclass;
461 /* Size of the string. */
465 extern const struct arc_aux_reg arc_aux_regs[];
466 extern const unsigned arc_num_aux_regs;
468 extern const struct arc_opcode arc_relax_opcodes[];
469 extern const unsigned arc_num_relax_opcodes;
471 /* Macro used for generating one class of NPS instructions. */
472 #define NPS_CMEM_HIGH_VALUE 0x57f0
474 /* Macros to help generating regular pattern instructions. */
475 #define FIELDA(word) (word & 0x3F)
476 #define FIELDB(word) (((word & 0x07) << 24) | (((word >> 3) & 0x07) << 12))
477 #define FIELDC(word) ((word & 0x3F) << 6)
478 #define FIELDF (0x01 << 15)
479 #define FIELDQ (0x1F)
481 #define INSN3OP(MOP,SOP) (((MOP & 0x1F) << 27) | ((SOP & 0x3F) << 16))
482 #define INSN2OPX(MOP,SOP1,SOP2) (INSN3OP (MOP,SOP1) | (SOP2 & 0x3F))
483 #define INSN2OP(MOP,SOP) (INSN2OPX (MOP,0x2F,SOP))
485 #define INSN3OP_ABC(MOP,SOP) (INSN3OP (MOP,SOP))
486 #define INSN3OP_ALC(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDB (62))
487 #define INSN3OP_ABL(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDC (62))
488 #define INSN3OP_ALL(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDB (62) | FIELDC (62))
489 #define INSN3OP_0BC(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62))
490 #define INSN3OP_0LC(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDB (62))
491 #define INSN3OP_0BL(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDC (62))
492 #define INSN3OP_0LL(MOP,SOP) \
493 (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDB (62) | FIELDC (62))
494 #define INSN3OP_ABU(MOP,SOP) (INSN3OP (MOP,SOP) | (0x01 << 22))
495 #define INSN3OP_ALU(MOP,SOP) (INSN3OP (MOP,SOP) | (0x01 << 22) | FIELDB (62))
496 #define INSN3OP_0BU(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62) | (0x01 << 22))
497 #define INSN3OP_0LU(MOP,SOP) \
498 (INSN3OP (MOP,SOP) | FIELDA (62) | (0x01 << 22) | FIELDB (62))
499 #define INSN3OP_BBS(MOP,SOP) (INSN3OP (MOP,SOP) | (0x02 << 22))
500 #define INSN3OP_0LS(MOP,SOP) (INSN3OP (MOP,SOP) | (0x02 << 22) | FIELDB (62))
501 #define INSN3OP_CBBC(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22))
502 #define INSN3OP_CBBL(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDC (62))
503 #define INSN3OP_C0LC(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDB (62))
504 #define INSN3OP_C0LL(MOP,SOP) \
505 (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDC (62) | FIELDB (62))
506 #define INSN3OP_CBBU(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | (0x01 << 5))
507 #define INSN3OP_C0LU(MOP,SOP) \
508 (INSN3OP (MOP,SOP) | (0x03 << 22) | (0x01 << 5) | FIELDB (62))
510 #define MASK_32BIT(VAL) (0xffffffff & (VAL))
512 #define MINSN3OP_ABC (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63))))
513 #define MINSN3OP_ALC (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDC (63))))
514 #define MINSN3OP_ABL (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDB (63))))
515 #define MINSN3OP_ALL (MASK_32BIT (~(FIELDF | FIELDA (63))))
516 #define MINSN3OP_0BC (MASK_32BIT (~(FIELDF | FIELDB (63) | FIELDC (63))))
517 #define MINSN3OP_0LC (MASK_32BIT (~(FIELDF | FIELDC (63))))
518 #define MINSN3OP_0BL (MASK_32BIT (~(FIELDF | FIELDB (63))))
519 #define MINSN3OP_0LL (MASK_32BIT (~(FIELDF)))
520 #define MINSN3OP_ABU (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63))))
521 #define MINSN3OP_ALU (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDC (63))))
522 #define MINSN3OP_0BU (MASK_32BIT (~(FIELDF | FIELDB (63) | FIELDC (63))))
523 #define MINSN3OP_0LU (MASK_32BIT (~(FIELDF | FIELDC (63))))
524 #define MINSN3OP_BBS (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63))))
525 #define MINSN3OP_0LS (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDC (63))))
526 #define MINSN3OP_CBBC (MASK_32BIT (~(FIELDF | FIELDQ | FIELDB (63) | FIELDC (63))))
527 #define MINSN3OP_CBBL (MASK_32BIT (~(FIELDF | FIELDQ | FIELDB (63))))
528 #define MINSN3OP_C0LC (MASK_32BIT (~(FIELDF | FIELDQ | FIELDC (63))))
529 #define MINSN3OP_C0LL (MASK_32BIT (~(FIELDF | FIELDQ)))
530 #define MINSN3OP_CBBU (MASK_32BIT (~(FIELDF | FIELDQ | FIELDB (63) | FIELDC (63))))
531 #define MINSN3OP_C0LU (MASK_32BIT (~(FIELDF | FIELDQ | FIELDC (63))))
533 #define INSN2OP_BC(MOP,SOP) (INSN2OP (MOP,SOP))
534 #define INSN2OP_BL(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDC (62))
535 #define INSN2OP_0C(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDB (62))
536 #define INSN2OP_0L(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDB (62) | FIELDC (62))
537 #define INSN2OP_BU(MOP,SOP) (INSN2OP (MOP,SOP) | (0x01 << 22))
538 #define INSN2OP_0U(MOP,SOP) (INSN2OP (MOP,SOP) | (0x01 << 22) | FIELDB (62))
540 #define MINSN2OP_BC (MASK_32BIT ((~(FIELDF | FIELDB (63) | FIELDC (63)))))
541 #define MINSN2OP_BL (MASK_32BIT ((~(FIELDF | FIELDB (63)))))
542 #define MINSN2OP_0C (MASK_32BIT ((~(FIELDF | FIELDC (63)))))
543 #define MINSN2OP_0L (MASK_32BIT ((~(FIELDF))))
544 #define MINSN2OP_BU (MASK_32BIT ((~(FIELDF | FIELDB (63) | FIELDC (63)))))
545 #define MINSN2OP_0U (MASK_32BIT ((~(FIELDF | FIELDC (63)))))
547 /* Various constants used when defining an extension instruction. */
548 #define ARC_SYNTAX_3OP (1 << 0)
549 #define ARC_SYNTAX_2OP (1 << 1)
550 #define ARC_SYNTAX_1OP (1 << 2)
551 #define ARC_SYNTAX_NOP (1 << 3)
552 #define ARC_SYNTAX_MASK (0x0F)
554 #define ARC_OP1_MUST_BE_IMM (1 << 0)
555 #define ARC_OP1_IMM_IMPLIED (1 << 1)
557 #define ARC_SUFFIX_NONE (1 << 0)
558 #define ARC_SUFFIX_COND (1 << 1)
559 #define ARC_SUFFIX_FLAG (1 << 2)
561 #define ARC_REGISTER_READONLY (1 << 0)
562 #define ARC_REGISTER_WRITEONLY (1 << 1)
563 #define ARC_REGISTER_NOSHORT_CUT (1 << 2)
565 /* Constants needed to initialize extension instructions. */
566 extern const unsigned char flags_none[MAX_INSN_FLGS + 1];
567 extern const unsigned char flags_f[MAX_INSN_FLGS + 1];
568 extern const unsigned char flags_cc[MAX_INSN_FLGS + 1];
569 extern const unsigned char flags_ccf[MAX_INSN_FLGS + 1];
571 extern const unsigned char arg_none[MAX_INSN_ARGS + 1];
572 extern const unsigned char arg_32bit_rarbrc[MAX_INSN_ARGS + 1];
573 extern const unsigned char arg_32bit_zarbrc[MAX_INSN_ARGS + 1];
574 extern const unsigned char arg_32bit_rbrbrc[MAX_INSN_ARGS + 1];
575 extern const unsigned char arg_32bit_rarbu6[MAX_INSN_ARGS + 1];
576 extern const unsigned char arg_32bit_zarbu6[MAX_INSN_ARGS + 1];
577 extern const unsigned char arg_32bit_rbrbu6[MAX_INSN_ARGS + 1];
578 extern const unsigned char arg_32bit_rbrbs12[MAX_INSN_ARGS + 1];
579 extern const unsigned char arg_32bit_ralimmrc[MAX_INSN_ARGS + 1];
580 extern const unsigned char arg_32bit_rarblimm[MAX_INSN_ARGS + 1];
581 extern const unsigned char arg_32bit_zalimmrc[MAX_INSN_ARGS + 1];
582 extern const unsigned char arg_32bit_zarblimm[MAX_INSN_ARGS + 1];
584 extern const unsigned char arg_32bit_rbrblimm[MAX_INSN_ARGS + 1];
585 extern const unsigned char arg_32bit_ralimmu6[MAX_INSN_ARGS + 1];
586 extern const unsigned char arg_32bit_zalimmu6[MAX_INSN_ARGS + 1];
588 extern const unsigned char arg_32bit_zalimms12[MAX_INSN_ARGS + 1];
589 extern const unsigned char arg_32bit_ralimmlimm[MAX_INSN_ARGS + 1];
590 extern const unsigned char arg_32bit_zalimmlimm[MAX_INSN_ARGS + 1];
592 extern const unsigned char arg_32bit_rbrc[MAX_INSN_ARGS + 1];
593 extern const unsigned char arg_32bit_zarc[MAX_INSN_ARGS + 1];
594 extern const unsigned char arg_32bit_rbu6[MAX_INSN_ARGS + 1];
595 extern const unsigned char arg_32bit_zau6[MAX_INSN_ARGS + 1];
596 extern const unsigned char arg_32bit_rblimm[MAX_INSN_ARGS + 1];
597 extern const unsigned char arg_32bit_zalimm[MAX_INSN_ARGS + 1];
599 extern const unsigned char arg_32bit_limmrc[MAX_INSN_ARGS + 1];
600 extern const unsigned char arg_32bit_limmu6[MAX_INSN_ARGS + 1];
601 extern const unsigned char arg_32bit_limms12[MAX_INSN_ARGS + 1];
602 extern const unsigned char arg_32bit_limmlimm[MAX_INSN_ARGS + 1];
604 extern const unsigned char arg_32bit_rc[MAX_INSN_ARGS + 1];
605 extern const unsigned char arg_32bit_u6[MAX_INSN_ARGS + 1];
606 extern const unsigned char arg_32bit_limm[MAX_INSN_ARGS + 1];
608 /* Address types used in the NPS-400. See page 367 of the NPS-400 CTOP
609 Instruction Set Reference Manual v2.4 for a description of address types. */
613 /* Addresses in memory. */
615 /* Buffer descriptor. */
616 ARC_NPS400_ADDRTYPE_BD,
618 /* Job identifier. */
619 ARC_NPS400_ADDRTYPE_JID,
621 /* Linked Buffer Descriptor. */
622 ARC_NPS400_ADDRTYPE_LBD,
624 /* Multicast Buffer Descriptor. */
625 ARC_NPS400_ADDRTYPE_MBD,
627 /* Summarized Address. */
628 ARC_NPS400_ADDRTYPE_SD,
630 /* SMEM Security Context Local Memory. */
631 ARC_NPS400_ADDRTYPE_SM,
633 /* Extended Address. */
634 ARC_NPS400_ADDRTYPE_XA,
636 /* Extended Summarized Address. */
637 ARC_NPS400_ADDRTYPE_XD,
639 /* CMEM offset addresses. */
641 /* On-demand Counter Descriptor. */
642 ARC_NPS400_ADDRTYPE_CD,
644 /* CMEM Buffer Descriptor. */
645 ARC_NPS400_ADDRTYPE_CBD,
647 /* CMEM Job Identifier. */
648 ARC_NPS400_ADDRTYPE_CJID,
650 /* CMEM Linked Buffer Descriptor. */
651 ARC_NPS400_ADDRTYPE_CLBD,
654 ARC_NPS400_ADDRTYPE_CM,
656 /* CMEM Summarized Address. */
657 ARC_NPS400_ADDRTYPE_CSD,
659 /* CMEM Extended Address. */
660 ARC_NPS400_ADDRTYPE_CXA,
662 /* CMEM Extended Summarized Address. */
663 ARC_NPS400_ADDRTYPE_CXD
665 } arc_nps_address_type;
667 #define ARC_NUM_ADDRTYPES 16
673 #endif /* OPCODE_ARC_H */