1 /* AArch64 assembler/disassembler support.
3 Copyright 2009, 2010, 2011, 2012 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GNU Binutils.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
22 #ifndef OPCODE_AARCH64_H
23 #define OPCODE_AARCH64_H
26 #include "bfd_stdint.h"
30 /* The offset for pc-relative addressing is currently defined to be 0. */
31 #define AARCH64_PCREL_OFFSET 0
33 typedef uint32_t aarch64_insn;
35 /* The following bitmasks control CPU features. */
36 #define AARCH64_FEATURE_V8 0x00000001 /* All processors. */
37 #define AARCH64_FEATURE_CRYPTO 0x00010000 /* Crypto instructions. */
38 #define AARCH64_FEATURE_FP 0x00020000 /* FP instructions. */
39 #define AARCH64_FEATURE_SIMD 0x00040000 /* SIMD instructions. */
41 /* Architectures are the sum of the base and extensions. */
42 #define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
44 | AARCH64_FEATURE_SIMD)
45 #define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0)
46 #define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */
48 /* CPU-specific features. */
49 typedef unsigned long aarch64_feature_set;
51 #define AARCH64_CPU_HAS_FEATURE(CPU,FEAT) \
52 (((CPU) & (FEAT)) != 0)
54 #define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2) \
57 (TARG) = (F1) | (F2); \
61 #define AARCH64_CLEAR_FEATURE(TARG,F1,F2) \
64 (TARG) = (F1) &~ (F2); \
68 #define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
70 #define AARCH64_OPCODE_HAS_FEATURE(OPC,FEAT) \
71 (((OPC) & (FEAT)) != 0)
73 enum aarch64_operand_class
75 AARCH64_OPND_CLASS_NIL,
76 AARCH64_OPND_CLASS_INT_REG,
77 AARCH64_OPND_CLASS_MODIFIED_REG,
78 AARCH64_OPND_CLASS_FP_REG,
79 AARCH64_OPND_CLASS_SIMD_REG,
80 AARCH64_OPND_CLASS_SIMD_ELEMENT,
81 AARCH64_OPND_CLASS_SISD_REG,
82 AARCH64_OPND_CLASS_SIMD_REGLIST,
83 AARCH64_OPND_CLASS_CP_REG,
84 AARCH64_OPND_CLASS_ADDRESS,
85 AARCH64_OPND_CLASS_IMMEDIATE,
86 AARCH64_OPND_CLASS_SYSTEM,
89 /* Operand code that helps both parsing and coding.
90 Keep AARCH64_OPERANDS synced. */
94 AARCH64_OPND_NIL, /* no operand---MUST BE FIRST!*/
96 AARCH64_OPND_Rd, /* Integer register as destination. */
97 AARCH64_OPND_Rn, /* Integer register as source. */
98 AARCH64_OPND_Rm, /* Integer register as source. */
99 AARCH64_OPND_Rt, /* Integer register used in ld/st instructions. */
100 AARCH64_OPND_Rt2, /* Integer register used in ld/st pair instructions. */
101 AARCH64_OPND_Rs, /* Integer register used in ld/st exclusive. */
102 AARCH64_OPND_Ra, /* Integer register used in ddp_3src instructions. */
103 AARCH64_OPND_Rt_SYS, /* Integer register used in system instructions. */
105 AARCH64_OPND_Rd_SP, /* Integer Rd or SP. */
106 AARCH64_OPND_Rn_SP, /* Integer Rn or SP. */
107 AARCH64_OPND_Rm_EXT, /* Integer Rm extended. */
108 AARCH64_OPND_Rm_SFT, /* Integer Rm shifted. */
110 AARCH64_OPND_Fd, /* Floating-point Fd. */
111 AARCH64_OPND_Fn, /* Floating-point Fn. */
112 AARCH64_OPND_Fm, /* Floating-point Fm. */
113 AARCH64_OPND_Fa, /* Floating-point Fa. */
114 AARCH64_OPND_Ft, /* Floating-point Ft. */
115 AARCH64_OPND_Ft2, /* Floating-point Ft2. */
117 AARCH64_OPND_Sd, /* AdvSIMD Scalar Sd. */
118 AARCH64_OPND_Sn, /* AdvSIMD Scalar Sn. */
119 AARCH64_OPND_Sm, /* AdvSIMD Scalar Sm. */
121 AARCH64_OPND_Vd, /* AdvSIMD Vector Vd. */
122 AARCH64_OPND_Vn, /* AdvSIMD Vector Vn. */
123 AARCH64_OPND_Vm, /* AdvSIMD Vector Vm. */
124 AARCH64_OPND_VdD1, /* AdvSIMD <Vd>.D[1]; for FMOV only. */
125 AARCH64_OPND_VnD1, /* AdvSIMD <Vn>.D[1]; for FMOV only. */
126 AARCH64_OPND_Ed, /* AdvSIMD Vector Element Vd. */
127 AARCH64_OPND_En, /* AdvSIMD Vector Element Vn. */
128 AARCH64_OPND_Em, /* AdvSIMD Vector Element Vm. */
129 AARCH64_OPND_LVn, /* AdvSIMD Vector register list used in e.g. TBL. */
130 AARCH64_OPND_LVt, /* AdvSIMD Vector register list used in ld/st. */
131 AARCH64_OPND_LVt_AL, /* AdvSIMD Vector register list for loading single
132 structure to all lanes. */
133 AARCH64_OPND_LEt, /* AdvSIMD Vector Element list. */
135 AARCH64_OPND_Cn, /* Co-processor register in CRn field. */
136 AARCH64_OPND_Cm, /* Co-processor register in CRm field. */
138 AARCH64_OPND_IDX, /* AdvSIMD EXT index operand. */
139 AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left. */
140 AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right. */
141 AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift. */
142 AARCH64_OPND_SIMD_IMM_SFT, /* AdvSIMD modified immediate with shift. */
143 AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate. */
144 AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction
146 AARCH64_OPND_IMM0, /* Immediate for #0. */
147 AARCH64_OPND_FPIMM0, /* Immediate for #0.0. */
148 AARCH64_OPND_FPIMM, /* Floating-point Immediate. */
149 AARCH64_OPND_IMMR, /* Immediate #<immr> in e.g. BFM. */
150 AARCH64_OPND_IMMS, /* Immediate #<imms> in e.g. BFM. */
151 AARCH64_OPND_WIDTH, /* Immediate #<width> in e.g. BFI. */
152 AARCH64_OPND_IMM, /* Immediate. */
153 AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field. */
154 AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field. */
155 AARCH64_OPND_UIMM4, /* Unsigned 4-bit immediate in the CRm field. */
156 AARCH64_OPND_UIMM7, /* Unsigned 7-bit immediate in the CRm:op2 fields. */
157 AARCH64_OPND_BIT_NUM, /* Immediate. */
158 AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions. */
159 AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions. */
160 AARCH64_OPND_NZCV, /* Flag bit specifier giving an alternative value for
161 each condition flag. */
163 AARCH64_OPND_LIMM, /* Logical Immediate. */
164 AARCH64_OPND_AIMM, /* Arithmetic immediate. */
165 AARCH64_OPND_HALF, /* #<imm16>{, LSL #<shift>} operand in move wide. */
166 AARCH64_OPND_FBITS, /* FP #<fbits> operand in e.g. SCVTF */
167 AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias. */
169 AARCH64_OPND_COND, /* Standard condition as the last operand. */
171 AARCH64_OPND_ADDR_ADRP, /* Memory address for ADRP */
172 AARCH64_OPND_ADDR_PCREL14, /* 14-bit PC-relative address for e.g. TBZ. */
173 AARCH64_OPND_ADDR_PCREL19, /* 19-bit PC-relative address for e.g. LDR. */
174 AARCH64_OPND_ADDR_PCREL21, /* 21-bit PC-relative address for e.g. ADR. */
175 AARCH64_OPND_ADDR_PCREL26, /* 26-bit PC-relative address for e.g. BL. */
177 AARCH64_OPND_ADDR_SIMPLE, /* Address of ld/st exclusive. */
178 AARCH64_OPND_ADDR_REGOFF, /* Address of register offset. */
179 AARCH64_OPND_ADDR_SIMM7, /* Address of signed 7-bit immediate. */
180 AARCH64_OPND_ADDR_SIMM9, /* Address of signed 9-bit immediate. */
181 AARCH64_OPND_ADDR_SIMM9_2, /* Same as the above, but the immediate is
182 negative or unaligned and there is
183 no writeback allowed. This operand code
184 is only used to support the programmer-
185 friendly feature of using LDR/STR as the
186 the mnemonic name for LDUR/STUR instructions
187 wherever there is no ambiguity. */
188 AARCH64_OPND_ADDR_UIMM12, /* Address of unsigned 12-bit immediate. */
189 AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures. */
190 AARCH64_OPND_SIMD_ADDR_POST, /* Address of ld/st multiple post-indexed. */
192 AARCH64_OPND_SYSREG, /* System register operand. */
193 AARCH64_OPND_PSTATEFIELD, /* PSTATE field name operand. */
194 AARCH64_OPND_SYSREG_AT, /* System register <at_op> operand. */
195 AARCH64_OPND_SYSREG_DC, /* System register <dc_op> operand. */
196 AARCH64_OPND_SYSREG_IC, /* System register <ic_op> operand. */
197 AARCH64_OPND_SYSREG_TLBI, /* System register <tlbi_op> operand. */
198 AARCH64_OPND_BARRIER, /* Barrier operand. */
199 AARCH64_OPND_BARRIER_ISB, /* Barrier operand for ISB. */
200 AARCH64_OPND_PRFOP, /* Prefetch operation. */
203 /* Qualifier constrains an operand. It either specifies a variant of an
204 operand type or limits values available to an operand type.
206 N.B. Order is important; keep aarch64_opnd_qualifiers synced. */
208 enum aarch64_opnd_qualifier
210 /* Indicating no further qualification on an operand. */
211 AARCH64_OPND_QLF_NIL,
213 /* Qualifying an operand which is a general purpose (integer) register;
214 indicating the operand data size or a specific register. */
215 AARCH64_OPND_QLF_W, /* Wn, WZR or WSP. */
216 AARCH64_OPND_QLF_X, /* Xn, XZR or XSP. */
217 AARCH64_OPND_QLF_WSP, /* WSP. */
218 AARCH64_OPND_QLF_SP, /* SP. */
220 /* Qualifying an operand which is a floating-point register, a SIMD
221 vector element or a SIMD vector element list; indicating operand data
222 size or the size of each SIMD vector element in the case of a SIMD
224 These qualifiers are also used to qualify an address operand to
225 indicate the size of data element a load/store instruction is
227 They are also used for the immediate shift operand in e.g. SSHR. Such
228 a use is only for the ease of operand encoding/decoding and qualifier
229 sequence matching; such a use should not be applied widely; use the value
230 constraint qualifiers for immediate operands wherever possible. */
231 AARCH64_OPND_QLF_S_B,
232 AARCH64_OPND_QLF_S_H,
233 AARCH64_OPND_QLF_S_S,
234 AARCH64_OPND_QLF_S_D,
235 AARCH64_OPND_QLF_S_Q,
237 /* Qualifying an operand which is a SIMD vector register or a SIMD vector
238 register list; indicating register shape.
239 They are also used for the immediate shift operand in e.g. SSHR. Such
240 a use is only for the ease of operand encoding/decoding and qualifier
241 sequence matching; such a use should not be applied widely; use the value
242 constraint qualifiers for immediate operands wherever possible. */
243 AARCH64_OPND_QLF_V_8B,
244 AARCH64_OPND_QLF_V_16B,
245 AARCH64_OPND_QLF_V_4H,
246 AARCH64_OPND_QLF_V_8H,
247 AARCH64_OPND_QLF_V_2S,
248 AARCH64_OPND_QLF_V_4S,
249 AARCH64_OPND_QLF_V_1D,
250 AARCH64_OPND_QLF_V_2D,
251 AARCH64_OPND_QLF_V_1Q,
253 /* Constraint on value. */
254 AARCH64_OPND_QLF_imm_0_7,
255 AARCH64_OPND_QLF_imm_0_15,
256 AARCH64_OPND_QLF_imm_0_31,
257 AARCH64_OPND_QLF_imm_0_63,
258 AARCH64_OPND_QLF_imm_1_32,
259 AARCH64_OPND_QLF_imm_1_64,
261 /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
263 AARCH64_OPND_QLF_LSL,
264 AARCH64_OPND_QLF_MSL,
266 /* Special qualifier helping retrieve qualifier information during the
267 decoding time (currently not in use). */
268 AARCH64_OPND_QLF_RETRIEVE,
271 /* Instruction class. */
273 enum aarch64_insn_class
328 ldst_imm9, /* immpost or immpre */
346 /* Opcode enumerators. */
390 OP_MOV_IMM_LOG, /* MOV alias for moving bitmask immediate. */
391 OP_MOV_IMM_WIDE, /* MOV alias for moving wide immediate. */
392 OP_MOV_IMM_WIDEN, /* MOV alias for moving wide immediate (negated). */
394 OP_MOV_V, /* MOV alias for moving vector register. */
423 OP_FCVTXN_S, /* Scalar version. */
427 OP_TOTAL_NUM, /* Pseudo. */
430 /* Maximum number of operands an instruction can have. */
431 #define AARCH64_MAX_OPND_NUM 6
432 /* Maximum number of qualifier sequences an instruction can have. */
433 #define AARCH64_MAX_QLF_SEQ_NUM 10
434 /* Operand qualifier typedef; optimized for the size. */
435 typedef unsigned char aarch64_opnd_qualifier_t;
436 /* Operand qualifier sequence typedef. */
437 typedef aarch64_opnd_qualifier_t \
438 aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];
440 /* FIXME: improve the efficiency. */
441 static inline bfd_boolean
442 empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
445 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
446 if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
451 /* This structure holds information for a particular opcode. */
453 struct aarch64_opcode
455 /* The name of the mnemonic. */
458 /* The opcode itself. Those bits which will be filled in with
459 operands are zeroes. */
462 /* The opcode mask. This is used by the disassembler. This is a
463 mask containing ones indicating those bits which must match the
464 opcode field, and zeroes indicating those bits which need not
465 match (and are presumably filled in by operands). */
468 /* Instruction class. */
469 enum aarch64_insn_class iclass;
471 /* Enumerator identifier. */
474 /* Which architecture variant provides this instruction. */
475 const aarch64_feature_set *avariant;
477 /* An array of operand codes. Each code is an index into the
478 operand table. They appear in the order which the operands must
479 appear in assembly code, and are terminated by a zero. */
480 enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM];
482 /* A list of operand qualifier code sequence. Each operand qualifier
483 code qualifies the corresponding operand code. Each operand
484 qualifier sequence specifies a valid opcode variant and related
485 constraint on operands. */
486 aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
488 /* Flags providing information about this instruction */
492 typedef struct aarch64_opcode aarch64_opcode;
494 /* Table describing all the AArch64 opcodes. */
495 extern aarch64_opcode aarch64_opcode_table[];
498 #define F_ALIAS (1 << 0)
499 #define F_HAS_ALIAS (1 << 1)
500 /* Disassembly preference priority 1-3 (the larger the higher). If nothing
501 is specified, it is the priority 0 by default, i.e. the lowest priority. */
502 #define F_P1 (1 << 2)
503 #define F_P2 (2 << 2)
504 #define F_P3 (3 << 2)
505 /* Flag an instruction that is truly conditional executed, e.g. b.cond. */
506 #define F_COND (1 << 4)
507 /* Instruction has the field of 'sf'. */
508 #define F_SF (1 << 5)
509 /* Instruction has the field of 'size:Q'. */
510 #define F_SIZEQ (1 << 6)
511 /* Floating-point instruction has the field of 'type'. */
512 #define F_FPTYPE (1 << 7)
513 /* AdvSIMD scalar instruction has the field of 'size'. */
514 #define F_SSIZE (1 << 8)
515 /* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q". */
517 /* Size of GPR operand in AdvSIMD instructions encoded in Q. */
518 #define F_GPRSIZE_IN_Q (1 << 10)
519 /* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22. */
520 #define F_LDS_SIZE (1 << 11)
521 /* Optional operand; assume maximum of 1 operand can be optional. */
522 #define F_OPD0_OPT (1 << 12)
523 #define F_OPD1_OPT (2 << 12)
524 #define F_OPD2_OPT (3 << 12)
525 #define F_OPD3_OPT (4 << 12)
526 #define F_OPD4_OPT (5 << 12)
527 /* Default value for the optional operand when omitted from the assembly. */
528 #define F_DEFAULT(X) (((X) & 0x1f) << 15)
529 /* Instruction that is an alias of another instruction needs to be
530 encoded/decoded by converting it to/from the real form, followed by
531 the encoding/decoding according to the rules of the real opcode.
532 This compares to the direct coding using the alias's information.
533 N.B. this flag requires F_ALIAS to be used together. */
534 #define F_CONV (1 << 20)
535 /* Use together with F_ALIAS to indicate an alias opcode is a programmer
536 friendly pseudo instruction available only in the assembly code (thus will
537 not show up in the disassembly). */
538 #define F_PSEUDO (1 << 21)
539 /* Instruction has miscellaneous encoding/decoding rules. */
540 #define F_MISC (1 << 22)
541 /* Instruction has the field of 'N'; used in conjunction with F_SF. */
542 #define F_N (1 << 23)
543 /* Opcode dependent field. */
544 #define F_OD(X) (((X) & 0x7) << 24)
545 /* Next bit is 27. */
547 static inline bfd_boolean
548 alias_opcode_p (const aarch64_opcode *opcode)
550 return (opcode->flags & F_ALIAS) ? TRUE : FALSE;
553 static inline bfd_boolean
554 opcode_has_alias (const aarch64_opcode *opcode)
556 return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE;
559 /* Priority for disassembling preference. */
561 opcode_priority (const aarch64_opcode *opcode)
563 return (opcode->flags >> 2) & 0x3;
566 static inline bfd_boolean
567 pseudo_opcode_p (const aarch64_opcode *opcode)
569 return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE;
572 static inline bfd_boolean
573 optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
575 return (((opcode->flags >> 12) & 0x7) == idx + 1)
579 static inline aarch64_insn
580 get_optional_operand_default_value (const aarch64_opcode *opcode)
582 return (opcode->flags >> 15) & 0x1f;
585 static inline unsigned int
586 get_opcode_dependent_value (const aarch64_opcode *opcode)
588 return (opcode->flags >> 24) & 0x7;
591 static inline bfd_boolean
592 opcode_has_special_coder (const aarch64_opcode *opcode)
594 return (opcode->flags & (F_SF | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
595 | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
599 struct aarch64_name_value_pair
605 extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
606 extern const struct aarch64_name_value_pair aarch64_sys_regs [];
607 extern const struct aarch64_name_value_pair aarch64_pstatefields [];
608 extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
609 extern const struct aarch64_name_value_pair aarch64_prfops [32];
613 const char *template;
616 } aarch64_sys_ins_reg;
618 extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
619 extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
620 extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
621 extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
623 /* Shift/extending operator kinds.
624 N.B. order is important; keep aarch64_operand_modifiers synced. */
625 enum aarch64_modifier_kind
644 aarch64_extend_operator_p (enum aarch64_modifier_kind);
646 enum aarch64_modifier_kind
647 aarch64_get_operand_modifier (const struct aarch64_name_value_pair *);
652 /* A list of names with the first one as the disassembly preference;
653 terminated by NULL if fewer than 3. */
654 const char *names[3];
658 extern const aarch64_cond aarch64_conds[16];
660 const aarch64_cond* get_cond_from_value (aarch64_insn value);
661 const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);
663 /* Structure representing an operand. */
665 struct aarch64_opnd_info
667 enum aarch64_opnd type;
668 aarch64_opnd_qualifier_t qualifier;
685 unsigned first_regno : 5;
686 unsigned num_regs : 3;
687 /* 1 if it is a list of reg element. */
688 unsigned has_index : 1;
689 /* Lane index; valid only when has_index is 1. */
692 /* e.g. immediate or pc relative address offset. */
698 /* e.g. address in STR (register offset). */
711 unsigned pcrel : 1; /* PC-relative. */
712 unsigned writeback : 1;
713 unsigned preind : 1; /* Pre-indexed. */
714 unsigned postind : 1; /* Post-indexed. */
716 const aarch64_cond *cond;
717 /* The encoding of the system register. */
719 /* The encoding of the PSTATE field. */
720 aarch64_insn pstatefield;
721 const aarch64_sys_ins_reg *sysins_op;
722 const struct aarch64_name_value_pair *barrier;
723 const struct aarch64_name_value_pair *prfop;
726 /* Operand shifter; in use when the operand is a register offset address,
727 add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}. */
730 enum aarch64_modifier_kind kind;
732 unsigned operator_present: 1; /* Only valid during encoding. */
733 /* Value of the 'S' field in ld/st reg offset; used only in decoding. */
734 unsigned amount_present: 1;
737 unsigned skip:1; /* Operand is not completed if there is a fixup needed
738 to be done on it. In some (but not all) of these
739 cases, we need to tell libopcodes to skip the
740 constraint checking and the encoding for this
741 operand, so that the libopcodes can pick up the
742 right opcode before the operand is fixed-up. This
743 flag should only be used during the
744 assembling/encoding. */
745 unsigned present:1; /* Whether this operand is present in the assembly
746 line; not used during the disassembly. */
749 typedef struct aarch64_opnd_info aarch64_opnd_info;
751 /* Structure representing an instruction.
753 It is used during both the assembling and disassembling. The assembler
754 fills an aarch64_inst after a successful parsing and then passes it to the
755 encoding routine to do the encoding. During the disassembling, the
756 disassembler calls the decoding routine to decode a binary instruction; on a
757 successful return, such a structure will be filled with information of the
758 instruction; then the disassembler uses the information to print out the
763 /* The value of the binary instruction. */
766 /* Corresponding opcode entry. */
767 const aarch64_opcode *opcode;
769 /* Condition for a truly conditional-executed instrutions, e.g. b.cond. */
770 const aarch64_cond *cond;
772 /* Operands information. */
773 aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
776 typedef struct aarch64_inst aarch64_inst;
778 /* Diagnosis related declaration and interface. */
780 /* Operand error kind enumerators.
782 AARCH64_OPDE_RECOVERABLE
783 Less severe error found during the parsing, very possibly because that
784 GAS has picked up a wrong instruction template for the parsing.
786 AARCH64_OPDE_SYNTAX_ERROR
787 General syntax error; it can be either a user error, or simply because
788 that GAS is trying a wrong instruction template.
790 AARCH64_OPDE_FATAL_SYNTAX_ERROR
791 Definitely a user syntax error.
793 AARCH64_OPDE_INVALID_VARIANT
794 No syntax error, but the operands are not a valid combination, e.g.
797 AARCH64_OPDE_OUT_OF_RANGE
798 Error about some immediate value out of a valid range.
800 AARCH64_OPDE_UNALIGNED
801 Error about some immediate value not properly aligned (i.e. not being a
802 multiple times of a certain value).
804 AARCH64_OPDE_REG_LIST
805 Error about the register list operand having unexpected number of
808 AARCH64_OPDE_OTHER_ERROR
809 Error of the highest severity and used for any severe issue that does not
810 fall into any of the above categories.
812 The enumerators are only interesting to GAS. They are declared here (in
813 libopcodes) because that some errors are detected (and then notified to GAS)
814 by libopcodes (rather than by GAS solely).
816 The first three errors are only deteced by GAS while the
817 AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
818 only libopcodes has the information about the valid variants of each
821 The enumerators have an increasing severity. This is helpful when there are
822 multiple instruction templates available for a given mnemonic name (e.g.
823 FMOV); this mechanism will help choose the most suitable template from which
824 the generated diagnostics can most closely describe the issues, if any. */
826 enum aarch64_operand_error_kind
829 AARCH64_OPDE_RECOVERABLE,
830 AARCH64_OPDE_SYNTAX_ERROR,
831 AARCH64_OPDE_FATAL_SYNTAX_ERROR,
832 AARCH64_OPDE_INVALID_VARIANT,
833 AARCH64_OPDE_OUT_OF_RANGE,
834 AARCH64_OPDE_UNALIGNED,
835 AARCH64_OPDE_REG_LIST,
836 AARCH64_OPDE_OTHER_ERROR
839 /* N.B. GAS assumes that this structure work well with shallow copy. */
840 struct aarch64_operand_error
842 enum aarch64_operand_error_kind kind;
845 int data[3]; /* Some data for extra information. */
848 typedef struct aarch64_operand_error aarch64_operand_error;
850 /* Encoding entrypoint. */
853 aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
854 aarch64_insn *, aarch64_opnd_qualifier_t *,
855 aarch64_operand_error *);
857 extern const aarch64_opcode *
858 aarch64_replace_opcode (struct aarch64_inst *,
859 const aarch64_opcode *);
861 /* Given the opcode enumerator OP, return the pointer to the corresponding
864 extern const aarch64_opcode *
865 aarch64_get_opcode (enum aarch64_op);
867 /* Generate the string representation of an operand. */
869 aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
870 const aarch64_opnd_info *, int, int *, bfd_vma *);
872 /* Miscellaneous interface. */
875 aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
877 extern aarch64_opnd_qualifier_t
878 aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
879 const aarch64_opnd_qualifier_t, int);
882 aarch64_num_of_operands (const aarch64_opcode *);
885 aarch64_stack_pointer_p (const aarch64_opnd_info *);
888 int aarch64_zero_register_p (const aarch64_opnd_info *);
890 /* Given an operand qualifier, return the expected data element size
891 of a qualified operand. */
893 aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
895 extern enum aarch64_operand_class
896 aarch64_get_operand_class (enum aarch64_opnd);
899 aarch64_get_operand_name (enum aarch64_opnd);
902 aarch64_get_operand_desc (enum aarch64_opnd);
905 extern int debug_dump;
908 aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
910 #define DEBUG_TRACE(M, ...) \
913 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
916 #define DEBUG_TRACE_IF(C, M, ...) \
918 if (debug_dump && (C)) \
919 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
921 #else /* !DEBUG_AARCH64 */
922 #define DEBUG_TRACE(M, ...) ;
923 #define DEBUG_TRACE_IF(C, M, ...) ;
924 #endif /* DEBUG_AARCH64 */
926 #endif /* OPCODE_AARCH64_H */