1 /* AArch64 assembler/disassembler support.
3 Copyright (C) 2009-2015 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GNU Binutils.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
22 #ifndef OPCODE_AARCH64_H
23 #define OPCODE_AARCH64_H
26 #include "bfd_stdint.h"
34 /* The offset for pc-relative addressing is currently defined to be 0. */
35 #define AARCH64_PCREL_OFFSET 0
37 typedef uint32_t aarch64_insn;
39 /* The following bitmasks control CPU features. */
40 #define AARCH64_FEATURE_V8 0x00000001 /* All processors. */
41 #define AARCH64_FEATURE_V8_2 0x00000020 /* ARMv8.2 processors. */
42 #define AARCH64_FEATURE_CRYPTO 0x00010000 /* Crypto instructions. */
43 #define AARCH64_FEATURE_FP 0x00020000 /* FP instructions. */
44 #define AARCH64_FEATURE_SIMD 0x00040000 /* SIMD instructions. */
45 #define AARCH64_FEATURE_CRC 0x00080000 /* CRC instructions. */
46 #define AARCH64_FEATURE_LSE 0x00100000 /* LSE instructions. */
47 #define AARCH64_FEATURE_PAN 0x00200000 /* PAN instructions. */
48 #define AARCH64_FEATURE_LOR 0x00400000 /* LOR instructions. */
49 #define AARCH64_FEATURE_RDMA 0x00800000 /* v8.1 SIMD instructions. */
50 #define AARCH64_FEATURE_V8_1 0x01000000 /* v8.1 features. */
51 #define AARCH64_FEATURE_F16 0x01000000 /* v8.2 FP16 instructions. */
53 /* Architectures are the sum of the base and extensions. */
54 #define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
56 | AARCH64_FEATURE_SIMD)
57 #define AARCH64_ARCH_V8_1 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
59 | AARCH64_FEATURE_SIMD \
60 | AARCH64_FEATURE_V8_1 \
61 | AARCH64_FEATURE_LSE \
62 | AARCH64_FEATURE_PAN \
63 | AARCH64_FEATURE_LOR \
64 | AARCH64_FEATURE_RDMA)
65 #define AARCH64_ARCH_V8_2 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
66 AARCH64_FEATURE_V8_2 \
67 | AARCH64_FEATURE_F16 \
68 | AARCH64_FEATURE_FP \
69 | AARCH64_FEATURE_SIMD \
70 | AARCH64_FEATURE_LSE \
71 | AARCH64_FEATURE_PAN \
72 | AARCH64_FEATURE_LOR \
73 | AARCH64_FEATURE_RDMA)
75 #define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0)
76 #define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */
78 /* CPU-specific features. */
79 typedef unsigned long aarch64_feature_set;
81 #define AARCH64_CPU_HAS_FEATURE(CPU,FEAT) \
82 (((CPU) & (FEAT)) != 0)
84 #define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2) \
87 (TARG) = (F1) | (F2); \
91 #define AARCH64_CLEAR_FEATURE(TARG,F1,F2) \
94 (TARG) = (F1) &~ (F2); \
98 #define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
100 #define AARCH64_OPCODE_HAS_FEATURE(OPC,FEAT) \
101 (((OPC) & (FEAT)) != 0)
103 enum aarch64_operand_class
105 AARCH64_OPND_CLASS_NIL,
106 AARCH64_OPND_CLASS_INT_REG,
107 AARCH64_OPND_CLASS_MODIFIED_REG,
108 AARCH64_OPND_CLASS_FP_REG,
109 AARCH64_OPND_CLASS_SIMD_REG,
110 AARCH64_OPND_CLASS_SIMD_ELEMENT,
111 AARCH64_OPND_CLASS_SISD_REG,
112 AARCH64_OPND_CLASS_SIMD_REGLIST,
113 AARCH64_OPND_CLASS_CP_REG,
114 AARCH64_OPND_CLASS_ADDRESS,
115 AARCH64_OPND_CLASS_IMMEDIATE,
116 AARCH64_OPND_CLASS_SYSTEM,
117 AARCH64_OPND_CLASS_COND,
120 /* Operand code that helps both parsing and coding.
121 Keep AARCH64_OPERANDS synced. */
125 AARCH64_OPND_NIL, /* no operand---MUST BE FIRST!*/
127 AARCH64_OPND_Rd, /* Integer register as destination. */
128 AARCH64_OPND_Rn, /* Integer register as source. */
129 AARCH64_OPND_Rm, /* Integer register as source. */
130 AARCH64_OPND_Rt, /* Integer register used in ld/st instructions. */
131 AARCH64_OPND_Rt2, /* Integer register used in ld/st pair instructions. */
132 AARCH64_OPND_Rs, /* Integer register used in ld/st exclusive. */
133 AARCH64_OPND_Ra, /* Integer register used in ddp_3src instructions. */
134 AARCH64_OPND_Rt_SYS, /* Integer register used in system instructions. */
136 AARCH64_OPND_Rd_SP, /* Integer Rd or SP. */
137 AARCH64_OPND_Rn_SP, /* Integer Rn or SP. */
138 AARCH64_OPND_PAIRREG, /* Paired register operand. */
139 AARCH64_OPND_Rm_EXT, /* Integer Rm extended. */
140 AARCH64_OPND_Rm_SFT, /* Integer Rm shifted. */
142 AARCH64_OPND_Fd, /* Floating-point Fd. */
143 AARCH64_OPND_Fn, /* Floating-point Fn. */
144 AARCH64_OPND_Fm, /* Floating-point Fm. */
145 AARCH64_OPND_Fa, /* Floating-point Fa. */
146 AARCH64_OPND_Ft, /* Floating-point Ft. */
147 AARCH64_OPND_Ft2, /* Floating-point Ft2. */
149 AARCH64_OPND_Sd, /* AdvSIMD Scalar Sd. */
150 AARCH64_OPND_Sn, /* AdvSIMD Scalar Sn. */
151 AARCH64_OPND_Sm, /* AdvSIMD Scalar Sm. */
153 AARCH64_OPND_Vd, /* AdvSIMD Vector Vd. */
154 AARCH64_OPND_Vn, /* AdvSIMD Vector Vn. */
155 AARCH64_OPND_Vm, /* AdvSIMD Vector Vm. */
156 AARCH64_OPND_VdD1, /* AdvSIMD <Vd>.D[1]; for FMOV only. */
157 AARCH64_OPND_VnD1, /* AdvSIMD <Vn>.D[1]; for FMOV only. */
158 AARCH64_OPND_Ed, /* AdvSIMD Vector Element Vd. */
159 AARCH64_OPND_En, /* AdvSIMD Vector Element Vn. */
160 AARCH64_OPND_Em, /* AdvSIMD Vector Element Vm. */
161 AARCH64_OPND_LVn, /* AdvSIMD Vector register list used in e.g. TBL. */
162 AARCH64_OPND_LVt, /* AdvSIMD Vector register list used in ld/st. */
163 AARCH64_OPND_LVt_AL, /* AdvSIMD Vector register list for loading single
164 structure to all lanes. */
165 AARCH64_OPND_LEt, /* AdvSIMD Vector Element list. */
167 AARCH64_OPND_Cn, /* Co-processor register in CRn field. */
168 AARCH64_OPND_Cm, /* Co-processor register in CRm field. */
170 AARCH64_OPND_IDX, /* AdvSIMD EXT index operand. */
171 AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left. */
172 AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right. */
173 AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift. */
174 AARCH64_OPND_SIMD_IMM_SFT, /* AdvSIMD modified immediate with shift. */
175 AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate. */
176 AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction
178 AARCH64_OPND_IMM0, /* Immediate for #0. */
179 AARCH64_OPND_FPIMM0, /* Immediate for #0.0. */
180 AARCH64_OPND_FPIMM, /* Floating-point Immediate. */
181 AARCH64_OPND_IMMR, /* Immediate #<immr> in e.g. BFM. */
182 AARCH64_OPND_IMMS, /* Immediate #<imms> in e.g. BFM. */
183 AARCH64_OPND_WIDTH, /* Immediate #<width> in e.g. BFI. */
184 AARCH64_OPND_IMM, /* Immediate. */
185 AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field. */
186 AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field. */
187 AARCH64_OPND_UIMM4, /* Unsigned 4-bit immediate in the CRm field. */
188 AARCH64_OPND_UIMM7, /* Unsigned 7-bit immediate in the CRm:op2 fields. */
189 AARCH64_OPND_BIT_NUM, /* Immediate. */
190 AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions. */
191 AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions. */
192 AARCH64_OPND_NZCV, /* Flag bit specifier giving an alternative value for
193 each condition flag. */
195 AARCH64_OPND_LIMM, /* Logical Immediate. */
196 AARCH64_OPND_AIMM, /* Arithmetic immediate. */
197 AARCH64_OPND_HALF, /* #<imm16>{, LSL #<shift>} operand in move wide. */
198 AARCH64_OPND_FBITS, /* FP #<fbits> operand in e.g. SCVTF */
199 AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias. */
201 AARCH64_OPND_COND, /* Standard condition as the last operand. */
202 AARCH64_OPND_COND1, /* Same as the above, but excluding AL and NV. */
204 AARCH64_OPND_ADDR_ADRP, /* Memory address for ADRP */
205 AARCH64_OPND_ADDR_PCREL14, /* 14-bit PC-relative address for e.g. TBZ. */
206 AARCH64_OPND_ADDR_PCREL19, /* 19-bit PC-relative address for e.g. LDR. */
207 AARCH64_OPND_ADDR_PCREL21, /* 21-bit PC-relative address for e.g. ADR. */
208 AARCH64_OPND_ADDR_PCREL26, /* 26-bit PC-relative address for e.g. BL. */
210 AARCH64_OPND_ADDR_SIMPLE, /* Address of ld/st exclusive. */
211 AARCH64_OPND_ADDR_REGOFF, /* Address of register offset. */
212 AARCH64_OPND_ADDR_SIMM7, /* Address of signed 7-bit immediate. */
213 AARCH64_OPND_ADDR_SIMM9, /* Address of signed 9-bit immediate. */
214 AARCH64_OPND_ADDR_SIMM9_2, /* Same as the above, but the immediate is
215 negative or unaligned and there is
216 no writeback allowed. This operand code
217 is only used to support the programmer-
218 friendly feature of using LDR/STR as the
219 the mnemonic name for LDUR/STUR instructions
220 wherever there is no ambiguity. */
221 AARCH64_OPND_ADDR_UIMM12, /* Address of unsigned 12-bit immediate. */
222 AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures. */
223 AARCH64_OPND_SIMD_ADDR_POST, /* Address of ld/st multiple post-indexed. */
225 AARCH64_OPND_SYSREG, /* System register operand. */
226 AARCH64_OPND_PSTATEFIELD, /* PSTATE field name operand. */
227 AARCH64_OPND_SYSREG_AT, /* System register <at_op> operand. */
228 AARCH64_OPND_SYSREG_DC, /* System register <dc_op> operand. */
229 AARCH64_OPND_SYSREG_IC, /* System register <ic_op> operand. */
230 AARCH64_OPND_SYSREG_TLBI, /* System register <tlbi_op> operand. */
231 AARCH64_OPND_BARRIER, /* Barrier operand. */
232 AARCH64_OPND_BARRIER_ISB, /* Barrier operand for ISB. */
233 AARCH64_OPND_PRFOP, /* Prefetch operation. */
236 /* Qualifier constrains an operand. It either specifies a variant of an
237 operand type or limits values available to an operand type.
239 N.B. Order is important; keep aarch64_opnd_qualifiers synced. */
241 enum aarch64_opnd_qualifier
243 /* Indicating no further qualification on an operand. */
244 AARCH64_OPND_QLF_NIL,
246 /* Qualifying an operand which is a general purpose (integer) register;
247 indicating the operand data size or a specific register. */
248 AARCH64_OPND_QLF_W, /* Wn, WZR or WSP. */
249 AARCH64_OPND_QLF_X, /* Xn, XZR or XSP. */
250 AARCH64_OPND_QLF_WSP, /* WSP. */
251 AARCH64_OPND_QLF_SP, /* SP. */
253 /* Qualifying an operand which is a floating-point register, a SIMD
254 vector element or a SIMD vector element list; indicating operand data
255 size or the size of each SIMD vector element in the case of a SIMD
257 These qualifiers are also used to qualify an address operand to
258 indicate the size of data element a load/store instruction is
260 They are also used for the immediate shift operand in e.g. SSHR. Such
261 a use is only for the ease of operand encoding/decoding and qualifier
262 sequence matching; such a use should not be applied widely; use the value
263 constraint qualifiers for immediate operands wherever possible. */
264 AARCH64_OPND_QLF_S_B,
265 AARCH64_OPND_QLF_S_H,
266 AARCH64_OPND_QLF_S_S,
267 AARCH64_OPND_QLF_S_D,
268 AARCH64_OPND_QLF_S_Q,
270 /* Qualifying an operand which is a SIMD vector register or a SIMD vector
271 register list; indicating register shape.
272 They are also used for the immediate shift operand in e.g. SSHR. Such
273 a use is only for the ease of operand encoding/decoding and qualifier
274 sequence matching; such a use should not be applied widely; use the value
275 constraint qualifiers for immediate operands wherever possible. */
276 AARCH64_OPND_QLF_V_8B,
277 AARCH64_OPND_QLF_V_16B,
278 AARCH64_OPND_QLF_V_4H,
279 AARCH64_OPND_QLF_V_8H,
280 AARCH64_OPND_QLF_V_2S,
281 AARCH64_OPND_QLF_V_4S,
282 AARCH64_OPND_QLF_V_1D,
283 AARCH64_OPND_QLF_V_2D,
284 AARCH64_OPND_QLF_V_1Q,
286 /* Constraint on value. */
287 AARCH64_OPND_QLF_imm_0_7,
288 AARCH64_OPND_QLF_imm_0_15,
289 AARCH64_OPND_QLF_imm_0_31,
290 AARCH64_OPND_QLF_imm_0_63,
291 AARCH64_OPND_QLF_imm_1_32,
292 AARCH64_OPND_QLF_imm_1_64,
294 /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
296 AARCH64_OPND_QLF_LSL,
297 AARCH64_OPND_QLF_MSL,
299 /* Special qualifier helping retrieve qualifier information during the
300 decoding time (currently not in use). */
301 AARCH64_OPND_QLF_RETRIEVE,
304 /* Instruction class. */
306 enum aarch64_insn_class
361 ldst_imm9, /* immpost or immpre */
380 /* Opcode enumerators. */
424 OP_MOV_IMM_LOG, /* MOV alias for moving bitmask immediate. */
425 OP_MOV_IMM_WIDE, /* MOV alias for moving wide immediate. */
426 OP_MOV_IMM_WIDEN, /* MOV alias for moving wide immediate (negated). */
428 OP_MOV_V, /* MOV alias for moving vector register. */
457 OP_FCVTXN_S, /* Scalar version. */
466 OP_TOTAL_NUM, /* Pseudo. */
469 /* Maximum number of operands an instruction can have. */
470 #define AARCH64_MAX_OPND_NUM 6
471 /* Maximum number of qualifier sequences an instruction can have. */
472 #define AARCH64_MAX_QLF_SEQ_NUM 10
473 /* Operand qualifier typedef; optimized for the size. */
474 typedef unsigned char aarch64_opnd_qualifier_t;
475 /* Operand qualifier sequence typedef. */
476 typedef aarch64_opnd_qualifier_t \
477 aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];
479 /* FIXME: improve the efficiency. */
480 static inline bfd_boolean
481 empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
484 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
485 if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
490 /* This structure holds information for a particular opcode. */
492 struct aarch64_opcode
494 /* The name of the mnemonic. */
497 /* The opcode itself. Those bits which will be filled in with
498 operands are zeroes. */
501 /* The opcode mask. This is used by the disassembler. This is a
502 mask containing ones indicating those bits which must match the
503 opcode field, and zeroes indicating those bits which need not
504 match (and are presumably filled in by operands). */
507 /* Instruction class. */
508 enum aarch64_insn_class iclass;
510 /* Enumerator identifier. */
513 /* Which architecture variant provides this instruction. */
514 const aarch64_feature_set *avariant;
516 /* An array of operand codes. Each code is an index into the
517 operand table. They appear in the order which the operands must
518 appear in assembly code, and are terminated by a zero. */
519 enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM];
521 /* A list of operand qualifier code sequence. Each operand qualifier
522 code qualifies the corresponding operand code. Each operand
523 qualifier sequence specifies a valid opcode variant and related
524 constraint on operands. */
525 aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
527 /* Flags providing information about this instruction */
531 typedef struct aarch64_opcode aarch64_opcode;
533 /* Table describing all the AArch64 opcodes. */
534 extern aarch64_opcode aarch64_opcode_table[];
537 #define F_ALIAS (1 << 0)
538 #define F_HAS_ALIAS (1 << 1)
539 /* Disassembly preference priority 1-3 (the larger the higher). If nothing
540 is specified, it is the priority 0 by default, i.e. the lowest priority. */
541 #define F_P1 (1 << 2)
542 #define F_P2 (2 << 2)
543 #define F_P3 (3 << 2)
544 /* Flag an instruction that is truly conditional executed, e.g. b.cond. */
545 #define F_COND (1 << 4)
546 /* Instruction has the field of 'sf'. */
547 #define F_SF (1 << 5)
548 /* Instruction has the field of 'size:Q'. */
549 #define F_SIZEQ (1 << 6)
550 /* Floating-point instruction has the field of 'type'. */
551 #define F_FPTYPE (1 << 7)
552 /* AdvSIMD scalar instruction has the field of 'size'. */
553 #define F_SSIZE (1 << 8)
554 /* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q". */
556 /* Size of GPR operand in AdvSIMD instructions encoded in Q. */
557 #define F_GPRSIZE_IN_Q (1 << 10)
558 /* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22. */
559 #define F_LDS_SIZE (1 << 11)
560 /* Optional operand; assume maximum of 1 operand can be optional. */
561 #define F_OPD0_OPT (1 << 12)
562 #define F_OPD1_OPT (2 << 12)
563 #define F_OPD2_OPT (3 << 12)
564 #define F_OPD3_OPT (4 << 12)
565 #define F_OPD4_OPT (5 << 12)
566 /* Default value for the optional operand when omitted from the assembly. */
567 #define F_DEFAULT(X) (((X) & 0x1f) << 15)
568 /* Instruction that is an alias of another instruction needs to be
569 encoded/decoded by converting it to/from the real form, followed by
570 the encoding/decoding according to the rules of the real opcode.
571 This compares to the direct coding using the alias's information.
572 N.B. this flag requires F_ALIAS to be used together. */
573 #define F_CONV (1 << 20)
574 /* Use together with F_ALIAS to indicate an alias opcode is a programmer
575 friendly pseudo instruction available only in the assembly code (thus will
576 not show up in the disassembly). */
577 #define F_PSEUDO (1 << 21)
578 /* Instruction has miscellaneous encoding/decoding rules. */
579 #define F_MISC (1 << 22)
580 /* Instruction has the field of 'N'; used in conjunction with F_SF. */
581 #define F_N (1 << 23)
582 /* Opcode dependent field. */
583 #define F_OD(X) (((X) & 0x7) << 24)
584 /* Instruction has the field of 'sz'. */
585 #define F_LSE_SZ (1 << 27)
586 /* Next bit is 28. */
588 static inline bfd_boolean
589 alias_opcode_p (const aarch64_opcode *opcode)
591 return (opcode->flags & F_ALIAS) ? TRUE : FALSE;
594 static inline bfd_boolean
595 opcode_has_alias (const aarch64_opcode *opcode)
597 return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE;
600 /* Priority for disassembling preference. */
602 opcode_priority (const aarch64_opcode *opcode)
604 return (opcode->flags >> 2) & 0x3;
607 static inline bfd_boolean
608 pseudo_opcode_p (const aarch64_opcode *opcode)
610 return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE;
613 static inline bfd_boolean
614 optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
616 return (((opcode->flags >> 12) & 0x7) == idx + 1)
620 static inline aarch64_insn
621 get_optional_operand_default_value (const aarch64_opcode *opcode)
623 return (opcode->flags >> 15) & 0x1f;
626 static inline unsigned int
627 get_opcode_dependent_value (const aarch64_opcode *opcode)
629 return (opcode->flags >> 24) & 0x7;
632 static inline bfd_boolean
633 opcode_has_special_coder (const aarch64_opcode *opcode)
635 return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
636 | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
640 struct aarch64_name_value_pair
646 extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
647 extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
648 extern const struct aarch64_name_value_pair aarch64_prfops [32];
657 extern const aarch64_sys_reg aarch64_sys_regs [];
658 extern const aarch64_sys_reg aarch64_pstatefields [];
659 extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *);
660 extern bfd_boolean aarch64_sys_reg_supported_p (const aarch64_feature_set,
661 const aarch64_sys_reg *);
662 extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set,
663 const aarch64_sys_reg *);
670 } aarch64_sys_ins_reg;
672 extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
673 extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
674 extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
675 extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
677 /* Shift/extending operator kinds.
678 N.B. order is important; keep aarch64_operand_modifiers synced. */
679 enum aarch64_modifier_kind
698 aarch64_extend_operator_p (enum aarch64_modifier_kind);
700 enum aarch64_modifier_kind
701 aarch64_get_operand_modifier (const struct aarch64_name_value_pair *);
706 /* A list of names with the first one as the disassembly preference;
707 terminated by NULL if fewer than 3. */
708 const char *names[3];
712 extern const aarch64_cond aarch64_conds[16];
714 const aarch64_cond* get_cond_from_value (aarch64_insn value);
715 const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);
717 /* Structure representing an operand. */
719 struct aarch64_opnd_info
721 enum aarch64_opnd type;
722 aarch64_opnd_qualifier_t qualifier;
739 unsigned first_regno : 5;
740 unsigned num_regs : 3;
741 /* 1 if it is a list of reg element. */
742 unsigned has_index : 1;
743 /* Lane index; valid only when has_index is 1. */
746 /* e.g. immediate or pc relative address offset. */
752 /* e.g. address in STR (register offset). */
765 unsigned pcrel : 1; /* PC-relative. */
766 unsigned writeback : 1;
767 unsigned preind : 1; /* Pre-indexed. */
768 unsigned postind : 1; /* Post-indexed. */
770 const aarch64_cond *cond;
771 /* The encoding of the system register. */
773 /* The encoding of the PSTATE field. */
774 aarch64_insn pstatefield;
775 const aarch64_sys_ins_reg *sysins_op;
776 const struct aarch64_name_value_pair *barrier;
777 const struct aarch64_name_value_pair *prfop;
780 /* Operand shifter; in use when the operand is a register offset address,
781 add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}. */
784 enum aarch64_modifier_kind kind;
786 unsigned operator_present: 1; /* Only valid during encoding. */
787 /* Value of the 'S' field in ld/st reg offset; used only in decoding. */
788 unsigned amount_present: 1;
791 unsigned skip:1; /* Operand is not completed if there is a fixup needed
792 to be done on it. In some (but not all) of these
793 cases, we need to tell libopcodes to skip the
794 constraint checking and the encoding for this
795 operand, so that the libopcodes can pick up the
796 right opcode before the operand is fixed-up. This
797 flag should only be used during the
798 assembling/encoding. */
799 unsigned present:1; /* Whether this operand is present in the assembly
800 line; not used during the disassembly. */
803 typedef struct aarch64_opnd_info aarch64_opnd_info;
805 /* Structure representing an instruction.
807 It is used during both the assembling and disassembling. The assembler
808 fills an aarch64_inst after a successful parsing and then passes it to the
809 encoding routine to do the encoding. During the disassembling, the
810 disassembler calls the decoding routine to decode a binary instruction; on a
811 successful return, such a structure will be filled with information of the
812 instruction; then the disassembler uses the information to print out the
817 /* The value of the binary instruction. */
820 /* Corresponding opcode entry. */
821 const aarch64_opcode *opcode;
823 /* Condition for a truly conditional-executed instrutions, e.g. b.cond. */
824 const aarch64_cond *cond;
826 /* Operands information. */
827 aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
830 typedef struct aarch64_inst aarch64_inst;
832 /* Diagnosis related declaration and interface. */
834 /* Operand error kind enumerators.
836 AARCH64_OPDE_RECOVERABLE
837 Less severe error found during the parsing, very possibly because that
838 GAS has picked up a wrong instruction template for the parsing.
840 AARCH64_OPDE_SYNTAX_ERROR
841 General syntax error; it can be either a user error, or simply because
842 that GAS is trying a wrong instruction template.
844 AARCH64_OPDE_FATAL_SYNTAX_ERROR
845 Definitely a user syntax error.
847 AARCH64_OPDE_INVALID_VARIANT
848 No syntax error, but the operands are not a valid combination, e.g.
851 AARCH64_OPDE_OUT_OF_RANGE
852 Error about some immediate value out of a valid range.
854 AARCH64_OPDE_UNALIGNED
855 Error about some immediate value not properly aligned (i.e. not being a
856 multiple times of a certain value).
858 AARCH64_OPDE_REG_LIST
859 Error about the register list operand having unexpected number of
862 AARCH64_OPDE_OTHER_ERROR
863 Error of the highest severity and used for any severe issue that does not
864 fall into any of the above categories.
866 The enumerators are only interesting to GAS. They are declared here (in
867 libopcodes) because that some errors are detected (and then notified to GAS)
868 by libopcodes (rather than by GAS solely).
870 The first three errors are only deteced by GAS while the
871 AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
872 only libopcodes has the information about the valid variants of each
875 The enumerators have an increasing severity. This is helpful when there are
876 multiple instruction templates available for a given mnemonic name (e.g.
877 FMOV); this mechanism will help choose the most suitable template from which
878 the generated diagnostics can most closely describe the issues, if any. */
880 enum aarch64_operand_error_kind
883 AARCH64_OPDE_RECOVERABLE,
884 AARCH64_OPDE_SYNTAX_ERROR,
885 AARCH64_OPDE_FATAL_SYNTAX_ERROR,
886 AARCH64_OPDE_INVALID_VARIANT,
887 AARCH64_OPDE_OUT_OF_RANGE,
888 AARCH64_OPDE_UNALIGNED,
889 AARCH64_OPDE_REG_LIST,
890 AARCH64_OPDE_OTHER_ERROR
893 /* N.B. GAS assumes that this structure work well with shallow copy. */
894 struct aarch64_operand_error
896 enum aarch64_operand_error_kind kind;
899 int data[3]; /* Some data for extra information. */
902 typedef struct aarch64_operand_error aarch64_operand_error;
904 /* Encoding entrypoint. */
907 aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
908 aarch64_insn *, aarch64_opnd_qualifier_t *,
909 aarch64_operand_error *);
911 extern const aarch64_opcode *
912 aarch64_replace_opcode (struct aarch64_inst *,
913 const aarch64_opcode *);
915 /* Given the opcode enumerator OP, return the pointer to the corresponding
918 extern const aarch64_opcode *
919 aarch64_get_opcode (enum aarch64_op);
921 /* Generate the string representation of an operand. */
923 aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
924 const aarch64_opnd_info *, int, int *, bfd_vma *);
926 /* Miscellaneous interface. */
929 aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
931 extern aarch64_opnd_qualifier_t
932 aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
933 const aarch64_opnd_qualifier_t, int);
936 aarch64_num_of_operands (const aarch64_opcode *);
939 aarch64_stack_pointer_p (const aarch64_opnd_info *);
942 aarch64_zero_register_p (const aarch64_opnd_info *);
945 aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean);
947 /* Given an operand qualifier, return the expected data element size
948 of a qualified operand. */
950 aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
952 extern enum aarch64_operand_class
953 aarch64_get_operand_class (enum aarch64_opnd);
956 aarch64_get_operand_name (enum aarch64_opnd);
959 aarch64_get_operand_desc (enum aarch64_opnd);
962 extern int debug_dump;
965 aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
967 #define DEBUG_TRACE(M, ...) \
970 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
973 #define DEBUG_TRACE_IF(C, M, ...) \
975 if (debug_dump && (C)) \
976 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
978 #else /* !DEBUG_AARCH64 */
979 #define DEBUG_TRACE(M, ...) ;
980 #define DEBUG_TRACE_IF(C, M, ...) ;
981 #endif /* DEBUG_AARCH64 */
987 #endif /* OPCODE_AARCH64_H */