1 /* AArch64 assembler/disassembler support.
3 Copyright (C) 2009-2014 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GNU Binutils.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
22 #ifndef OPCODE_AARCH64_H
23 #define OPCODE_AARCH64_H
26 #include "bfd_stdint.h"
30 /* The offset for pc-relative addressing is currently defined to be 0. */
31 #define AARCH64_PCREL_OFFSET 0
33 typedef uint32_t aarch64_insn;
35 /* The following bitmasks control CPU features. */
36 #define AARCH64_FEATURE_V8 0x00000001 /* All processors. */
37 #define AARCH64_FEATURE_CRYPTO 0x00010000 /* Crypto instructions. */
38 #define AARCH64_FEATURE_FP 0x00020000 /* FP instructions. */
39 #define AARCH64_FEATURE_SIMD 0x00040000 /* SIMD instructions. */
40 #define AARCH64_FEATURE_CRC 0x00080000 /* CRC instructions. */
42 /* Architectures are the sum of the base and extensions. */
43 #define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
45 | AARCH64_FEATURE_SIMD)
46 #define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0)
47 #define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */
49 /* CPU-specific features. */
50 typedef unsigned long aarch64_feature_set;
52 #define AARCH64_CPU_HAS_FEATURE(CPU,FEAT) \
53 (((CPU) & (FEAT)) != 0)
55 #define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2) \
58 (TARG) = (F1) | (F2); \
62 #define AARCH64_CLEAR_FEATURE(TARG,F1,F2) \
65 (TARG) = (F1) &~ (F2); \
69 #define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
71 #define AARCH64_OPCODE_HAS_FEATURE(OPC,FEAT) \
72 (((OPC) & (FEAT)) != 0)
74 enum aarch64_operand_class
76 AARCH64_OPND_CLASS_NIL,
77 AARCH64_OPND_CLASS_INT_REG,
78 AARCH64_OPND_CLASS_MODIFIED_REG,
79 AARCH64_OPND_CLASS_FP_REG,
80 AARCH64_OPND_CLASS_SIMD_REG,
81 AARCH64_OPND_CLASS_SIMD_ELEMENT,
82 AARCH64_OPND_CLASS_SISD_REG,
83 AARCH64_OPND_CLASS_SIMD_REGLIST,
84 AARCH64_OPND_CLASS_CP_REG,
85 AARCH64_OPND_CLASS_ADDRESS,
86 AARCH64_OPND_CLASS_IMMEDIATE,
87 AARCH64_OPND_CLASS_SYSTEM,
88 AARCH64_OPND_CLASS_COND,
91 /* Operand code that helps both parsing and coding.
92 Keep AARCH64_OPERANDS synced. */
96 AARCH64_OPND_NIL, /* no operand---MUST BE FIRST!*/
98 AARCH64_OPND_Rd, /* Integer register as destination. */
99 AARCH64_OPND_Rn, /* Integer register as source. */
100 AARCH64_OPND_Rm, /* Integer register as source. */
101 AARCH64_OPND_Rt, /* Integer register used in ld/st instructions. */
102 AARCH64_OPND_Rt2, /* Integer register used in ld/st pair instructions. */
103 AARCH64_OPND_Rs, /* Integer register used in ld/st exclusive. */
104 AARCH64_OPND_Ra, /* Integer register used in ddp_3src instructions. */
105 AARCH64_OPND_Rt_SYS, /* Integer register used in system instructions. */
107 AARCH64_OPND_Rd_SP, /* Integer Rd or SP. */
108 AARCH64_OPND_Rn_SP, /* Integer Rn or SP. */
109 AARCH64_OPND_Rm_EXT, /* Integer Rm extended. */
110 AARCH64_OPND_Rm_SFT, /* Integer Rm shifted. */
112 AARCH64_OPND_Fd, /* Floating-point Fd. */
113 AARCH64_OPND_Fn, /* Floating-point Fn. */
114 AARCH64_OPND_Fm, /* Floating-point Fm. */
115 AARCH64_OPND_Fa, /* Floating-point Fa. */
116 AARCH64_OPND_Ft, /* Floating-point Ft. */
117 AARCH64_OPND_Ft2, /* Floating-point Ft2. */
119 AARCH64_OPND_Sd, /* AdvSIMD Scalar Sd. */
120 AARCH64_OPND_Sn, /* AdvSIMD Scalar Sn. */
121 AARCH64_OPND_Sm, /* AdvSIMD Scalar Sm. */
123 AARCH64_OPND_Vd, /* AdvSIMD Vector Vd. */
124 AARCH64_OPND_Vn, /* AdvSIMD Vector Vn. */
125 AARCH64_OPND_Vm, /* AdvSIMD Vector Vm. */
126 AARCH64_OPND_VdD1, /* AdvSIMD <Vd>.D[1]; for FMOV only. */
127 AARCH64_OPND_VnD1, /* AdvSIMD <Vn>.D[1]; for FMOV only. */
128 AARCH64_OPND_Ed, /* AdvSIMD Vector Element Vd. */
129 AARCH64_OPND_En, /* AdvSIMD Vector Element Vn. */
130 AARCH64_OPND_Em, /* AdvSIMD Vector Element Vm. */
131 AARCH64_OPND_LVn, /* AdvSIMD Vector register list used in e.g. TBL. */
132 AARCH64_OPND_LVt, /* AdvSIMD Vector register list used in ld/st. */
133 AARCH64_OPND_LVt_AL, /* AdvSIMD Vector register list for loading single
134 structure to all lanes. */
135 AARCH64_OPND_LEt, /* AdvSIMD Vector Element list. */
137 AARCH64_OPND_Cn, /* Co-processor register in CRn field. */
138 AARCH64_OPND_Cm, /* Co-processor register in CRm field. */
140 AARCH64_OPND_IDX, /* AdvSIMD EXT index operand. */
141 AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left. */
142 AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right. */
143 AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift. */
144 AARCH64_OPND_SIMD_IMM_SFT, /* AdvSIMD modified immediate with shift. */
145 AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate. */
146 AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction
148 AARCH64_OPND_IMM0, /* Immediate for #0. */
149 AARCH64_OPND_FPIMM0, /* Immediate for #0.0. */
150 AARCH64_OPND_FPIMM, /* Floating-point Immediate. */
151 AARCH64_OPND_IMMR, /* Immediate #<immr> in e.g. BFM. */
152 AARCH64_OPND_IMMS, /* Immediate #<imms> in e.g. BFM. */
153 AARCH64_OPND_WIDTH, /* Immediate #<width> in e.g. BFI. */
154 AARCH64_OPND_IMM, /* Immediate. */
155 AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field. */
156 AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field. */
157 AARCH64_OPND_UIMM4, /* Unsigned 4-bit immediate in the CRm field. */
158 AARCH64_OPND_UIMM7, /* Unsigned 7-bit immediate in the CRm:op2 fields. */
159 AARCH64_OPND_BIT_NUM, /* Immediate. */
160 AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions. */
161 AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions. */
162 AARCH64_OPND_NZCV, /* Flag bit specifier giving an alternative value for
163 each condition flag. */
165 AARCH64_OPND_LIMM, /* Logical Immediate. */
166 AARCH64_OPND_AIMM, /* Arithmetic immediate. */
167 AARCH64_OPND_HALF, /* #<imm16>{, LSL #<shift>} operand in move wide. */
168 AARCH64_OPND_FBITS, /* FP #<fbits> operand in e.g. SCVTF */
169 AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias. */
171 AARCH64_OPND_COND, /* Standard condition as the last operand. */
172 AARCH64_OPND_COND1, /* Same as the above, but excluding AL and NV. */
174 AARCH64_OPND_ADDR_ADRP, /* Memory address for ADRP */
175 AARCH64_OPND_ADDR_PCREL14, /* 14-bit PC-relative address for e.g. TBZ. */
176 AARCH64_OPND_ADDR_PCREL19, /* 19-bit PC-relative address for e.g. LDR. */
177 AARCH64_OPND_ADDR_PCREL21, /* 21-bit PC-relative address for e.g. ADR. */
178 AARCH64_OPND_ADDR_PCREL26, /* 26-bit PC-relative address for e.g. BL. */
180 AARCH64_OPND_ADDR_SIMPLE, /* Address of ld/st exclusive. */
181 AARCH64_OPND_ADDR_REGOFF, /* Address of register offset. */
182 AARCH64_OPND_ADDR_SIMM7, /* Address of signed 7-bit immediate. */
183 AARCH64_OPND_ADDR_SIMM9, /* Address of signed 9-bit immediate. */
184 AARCH64_OPND_ADDR_SIMM9_2, /* Same as the above, but the immediate is
185 negative or unaligned and there is
186 no writeback allowed. This operand code
187 is only used to support the programmer-
188 friendly feature of using LDR/STR as the
189 the mnemonic name for LDUR/STUR instructions
190 wherever there is no ambiguity. */
191 AARCH64_OPND_ADDR_UIMM12, /* Address of unsigned 12-bit immediate. */
192 AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures. */
193 AARCH64_OPND_SIMD_ADDR_POST, /* Address of ld/st multiple post-indexed. */
195 AARCH64_OPND_SYSREG, /* System register operand. */
196 AARCH64_OPND_PSTATEFIELD, /* PSTATE field name operand. */
197 AARCH64_OPND_SYSREG_AT, /* System register <at_op> operand. */
198 AARCH64_OPND_SYSREG_DC, /* System register <dc_op> operand. */
199 AARCH64_OPND_SYSREG_IC, /* System register <ic_op> operand. */
200 AARCH64_OPND_SYSREG_TLBI, /* System register <tlbi_op> operand. */
201 AARCH64_OPND_BARRIER, /* Barrier operand. */
202 AARCH64_OPND_BARRIER_ISB, /* Barrier operand for ISB. */
203 AARCH64_OPND_PRFOP, /* Prefetch operation. */
206 /* Qualifier constrains an operand. It either specifies a variant of an
207 operand type or limits values available to an operand type.
209 N.B. Order is important; keep aarch64_opnd_qualifiers synced. */
211 enum aarch64_opnd_qualifier
213 /* Indicating no further qualification on an operand. */
214 AARCH64_OPND_QLF_NIL,
216 /* Qualifying an operand which is a general purpose (integer) register;
217 indicating the operand data size or a specific register. */
218 AARCH64_OPND_QLF_W, /* Wn, WZR or WSP. */
219 AARCH64_OPND_QLF_X, /* Xn, XZR or XSP. */
220 AARCH64_OPND_QLF_WSP, /* WSP. */
221 AARCH64_OPND_QLF_SP, /* SP. */
223 /* Qualifying an operand which is a floating-point register, a SIMD
224 vector element or a SIMD vector element list; indicating operand data
225 size or the size of each SIMD vector element in the case of a SIMD
227 These qualifiers are also used to qualify an address operand to
228 indicate the size of data element a load/store instruction is
230 They are also used for the immediate shift operand in e.g. SSHR. Such
231 a use is only for the ease of operand encoding/decoding and qualifier
232 sequence matching; such a use should not be applied widely; use the value
233 constraint qualifiers for immediate operands wherever possible. */
234 AARCH64_OPND_QLF_S_B,
235 AARCH64_OPND_QLF_S_H,
236 AARCH64_OPND_QLF_S_S,
237 AARCH64_OPND_QLF_S_D,
238 AARCH64_OPND_QLF_S_Q,
240 /* Qualifying an operand which is a SIMD vector register or a SIMD vector
241 register list; indicating register shape.
242 They are also used for the immediate shift operand in e.g. SSHR. Such
243 a use is only for the ease of operand encoding/decoding and qualifier
244 sequence matching; such a use should not be applied widely; use the value
245 constraint qualifiers for immediate operands wherever possible. */
246 AARCH64_OPND_QLF_V_8B,
247 AARCH64_OPND_QLF_V_16B,
248 AARCH64_OPND_QLF_V_4H,
249 AARCH64_OPND_QLF_V_8H,
250 AARCH64_OPND_QLF_V_2S,
251 AARCH64_OPND_QLF_V_4S,
252 AARCH64_OPND_QLF_V_1D,
253 AARCH64_OPND_QLF_V_2D,
254 AARCH64_OPND_QLF_V_1Q,
256 /* Constraint on value. */
257 AARCH64_OPND_QLF_imm_0_7,
258 AARCH64_OPND_QLF_imm_0_15,
259 AARCH64_OPND_QLF_imm_0_31,
260 AARCH64_OPND_QLF_imm_0_63,
261 AARCH64_OPND_QLF_imm_1_32,
262 AARCH64_OPND_QLF_imm_1_64,
264 /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
266 AARCH64_OPND_QLF_LSL,
267 AARCH64_OPND_QLF_MSL,
269 /* Special qualifier helping retrieve qualifier information during the
270 decoding time (currently not in use). */
271 AARCH64_OPND_QLF_RETRIEVE,
274 /* Instruction class. */
276 enum aarch64_insn_class
331 ldst_imm9, /* immpost or immpre */
349 /* Opcode enumerators. */
393 OP_MOV_IMM_LOG, /* MOV alias for moving bitmask immediate. */
394 OP_MOV_IMM_WIDE, /* MOV alias for moving wide immediate. */
395 OP_MOV_IMM_WIDEN, /* MOV alias for moving wide immediate (negated). */
397 OP_MOV_V, /* MOV alias for moving vector register. */
426 OP_FCVTXN_S, /* Scalar version. */
435 OP_TOTAL_NUM, /* Pseudo. */
438 /* Maximum number of operands an instruction can have. */
439 #define AARCH64_MAX_OPND_NUM 6
440 /* Maximum number of qualifier sequences an instruction can have. */
441 #define AARCH64_MAX_QLF_SEQ_NUM 10
442 /* Operand qualifier typedef; optimized for the size. */
443 typedef unsigned char aarch64_opnd_qualifier_t;
444 /* Operand qualifier sequence typedef. */
445 typedef aarch64_opnd_qualifier_t \
446 aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];
448 /* FIXME: improve the efficiency. */
449 static inline bfd_boolean
450 empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
453 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
454 if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
459 /* This structure holds information for a particular opcode. */
461 struct aarch64_opcode
463 /* The name of the mnemonic. */
466 /* The opcode itself. Those bits which will be filled in with
467 operands are zeroes. */
470 /* The opcode mask. This is used by the disassembler. This is a
471 mask containing ones indicating those bits which must match the
472 opcode field, and zeroes indicating those bits which need not
473 match (and are presumably filled in by operands). */
476 /* Instruction class. */
477 enum aarch64_insn_class iclass;
479 /* Enumerator identifier. */
482 /* Which architecture variant provides this instruction. */
483 const aarch64_feature_set *avariant;
485 /* An array of operand codes. Each code is an index into the
486 operand table. They appear in the order which the operands must
487 appear in assembly code, and are terminated by a zero. */
488 enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM];
490 /* A list of operand qualifier code sequence. Each operand qualifier
491 code qualifies the corresponding operand code. Each operand
492 qualifier sequence specifies a valid opcode variant and related
493 constraint on operands. */
494 aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
496 /* Flags providing information about this instruction */
500 typedef struct aarch64_opcode aarch64_opcode;
502 /* Table describing all the AArch64 opcodes. */
503 extern aarch64_opcode aarch64_opcode_table[];
506 #define F_ALIAS (1 << 0)
507 #define F_HAS_ALIAS (1 << 1)
508 /* Disassembly preference priority 1-3 (the larger the higher). If nothing
509 is specified, it is the priority 0 by default, i.e. the lowest priority. */
510 #define F_P1 (1 << 2)
511 #define F_P2 (2 << 2)
512 #define F_P3 (3 << 2)
513 /* Flag an instruction that is truly conditional executed, e.g. b.cond. */
514 #define F_COND (1 << 4)
515 /* Instruction has the field of 'sf'. */
516 #define F_SF (1 << 5)
517 /* Instruction has the field of 'size:Q'. */
518 #define F_SIZEQ (1 << 6)
519 /* Floating-point instruction has the field of 'type'. */
520 #define F_FPTYPE (1 << 7)
521 /* AdvSIMD scalar instruction has the field of 'size'. */
522 #define F_SSIZE (1 << 8)
523 /* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q". */
525 /* Size of GPR operand in AdvSIMD instructions encoded in Q. */
526 #define F_GPRSIZE_IN_Q (1 << 10)
527 /* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22. */
528 #define F_LDS_SIZE (1 << 11)
529 /* Optional operand; assume maximum of 1 operand can be optional. */
530 #define F_OPD0_OPT (1 << 12)
531 #define F_OPD1_OPT (2 << 12)
532 #define F_OPD2_OPT (3 << 12)
533 #define F_OPD3_OPT (4 << 12)
534 #define F_OPD4_OPT (5 << 12)
535 /* Default value for the optional operand when omitted from the assembly. */
536 #define F_DEFAULT(X) (((X) & 0x1f) << 15)
537 /* Instruction that is an alias of another instruction needs to be
538 encoded/decoded by converting it to/from the real form, followed by
539 the encoding/decoding according to the rules of the real opcode.
540 This compares to the direct coding using the alias's information.
541 N.B. this flag requires F_ALIAS to be used together. */
542 #define F_CONV (1 << 20)
543 /* Use together with F_ALIAS to indicate an alias opcode is a programmer
544 friendly pseudo instruction available only in the assembly code (thus will
545 not show up in the disassembly). */
546 #define F_PSEUDO (1 << 21)
547 /* Instruction has miscellaneous encoding/decoding rules. */
548 #define F_MISC (1 << 22)
549 /* Instruction has the field of 'N'; used in conjunction with F_SF. */
550 #define F_N (1 << 23)
551 /* Opcode dependent field. */
552 #define F_OD(X) (((X) & 0x7) << 24)
553 /* Next bit is 27. */
555 static inline bfd_boolean
556 alias_opcode_p (const aarch64_opcode *opcode)
558 return (opcode->flags & F_ALIAS) ? TRUE : FALSE;
561 static inline bfd_boolean
562 opcode_has_alias (const aarch64_opcode *opcode)
564 return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE;
567 /* Priority for disassembling preference. */
569 opcode_priority (const aarch64_opcode *opcode)
571 return (opcode->flags >> 2) & 0x3;
574 static inline bfd_boolean
575 pseudo_opcode_p (const aarch64_opcode *opcode)
577 return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE;
580 static inline bfd_boolean
581 optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
583 return (((opcode->flags >> 12) & 0x7) == idx + 1)
587 static inline aarch64_insn
588 get_optional_operand_default_value (const aarch64_opcode *opcode)
590 return (opcode->flags >> 15) & 0x1f;
593 static inline unsigned int
594 get_opcode_dependent_value (const aarch64_opcode *opcode)
596 return (opcode->flags >> 24) & 0x7;
599 static inline bfd_boolean
600 opcode_has_special_coder (const aarch64_opcode *opcode)
602 return (opcode->flags & (F_SF | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
603 | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
607 struct aarch64_name_value_pair
613 extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
614 extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
615 extern const struct aarch64_name_value_pair aarch64_prfops [32];
624 extern const aarch64_sys_reg aarch64_sys_regs [];
625 extern const aarch64_sys_reg aarch64_pstatefields [];
626 extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *);
630 const char *template;
633 } aarch64_sys_ins_reg;
635 extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
636 extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
637 extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
638 extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
640 /* Shift/extending operator kinds.
641 N.B. order is important; keep aarch64_operand_modifiers synced. */
642 enum aarch64_modifier_kind
661 aarch64_extend_operator_p (enum aarch64_modifier_kind);
663 enum aarch64_modifier_kind
664 aarch64_get_operand_modifier (const struct aarch64_name_value_pair *);
669 /* A list of names with the first one as the disassembly preference;
670 terminated by NULL if fewer than 3. */
671 const char *names[3];
675 extern const aarch64_cond aarch64_conds[16];
677 const aarch64_cond* get_cond_from_value (aarch64_insn value);
678 const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);
680 /* Structure representing an operand. */
682 struct aarch64_opnd_info
684 enum aarch64_opnd type;
685 aarch64_opnd_qualifier_t qualifier;
702 unsigned first_regno : 5;
703 unsigned num_regs : 3;
704 /* 1 if it is a list of reg element. */
705 unsigned has_index : 1;
706 /* Lane index; valid only when has_index is 1. */
709 /* e.g. immediate or pc relative address offset. */
715 /* e.g. address in STR (register offset). */
728 unsigned pcrel : 1; /* PC-relative. */
729 unsigned writeback : 1;
730 unsigned preind : 1; /* Pre-indexed. */
731 unsigned postind : 1; /* Post-indexed. */
733 const aarch64_cond *cond;
734 /* The encoding of the system register. */
736 /* The encoding of the PSTATE field. */
737 aarch64_insn pstatefield;
738 const aarch64_sys_ins_reg *sysins_op;
739 const struct aarch64_name_value_pair *barrier;
740 const struct aarch64_name_value_pair *prfop;
743 /* Operand shifter; in use when the operand is a register offset address,
744 add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}. */
747 enum aarch64_modifier_kind kind;
749 unsigned operator_present: 1; /* Only valid during encoding. */
750 /* Value of the 'S' field in ld/st reg offset; used only in decoding. */
751 unsigned amount_present: 1;
754 unsigned skip:1; /* Operand is not completed if there is a fixup needed
755 to be done on it. In some (but not all) of these
756 cases, we need to tell libopcodes to skip the
757 constraint checking and the encoding for this
758 operand, so that the libopcodes can pick up the
759 right opcode before the operand is fixed-up. This
760 flag should only be used during the
761 assembling/encoding. */
762 unsigned present:1; /* Whether this operand is present in the assembly
763 line; not used during the disassembly. */
766 typedef struct aarch64_opnd_info aarch64_opnd_info;
768 /* Structure representing an instruction.
770 It is used during both the assembling and disassembling. The assembler
771 fills an aarch64_inst after a successful parsing and then passes it to the
772 encoding routine to do the encoding. During the disassembling, the
773 disassembler calls the decoding routine to decode a binary instruction; on a
774 successful return, such a structure will be filled with information of the
775 instruction; then the disassembler uses the information to print out the
780 /* The value of the binary instruction. */
783 /* Corresponding opcode entry. */
784 const aarch64_opcode *opcode;
786 /* Condition for a truly conditional-executed instrutions, e.g. b.cond. */
787 const aarch64_cond *cond;
789 /* Operands information. */
790 aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
793 typedef struct aarch64_inst aarch64_inst;
795 /* Diagnosis related declaration and interface. */
797 /* Operand error kind enumerators.
799 AARCH64_OPDE_RECOVERABLE
800 Less severe error found during the parsing, very possibly because that
801 GAS has picked up a wrong instruction template for the parsing.
803 AARCH64_OPDE_SYNTAX_ERROR
804 General syntax error; it can be either a user error, or simply because
805 that GAS is trying a wrong instruction template.
807 AARCH64_OPDE_FATAL_SYNTAX_ERROR
808 Definitely a user syntax error.
810 AARCH64_OPDE_INVALID_VARIANT
811 No syntax error, but the operands are not a valid combination, e.g.
814 AARCH64_OPDE_OUT_OF_RANGE
815 Error about some immediate value out of a valid range.
817 AARCH64_OPDE_UNALIGNED
818 Error about some immediate value not properly aligned (i.e. not being a
819 multiple times of a certain value).
821 AARCH64_OPDE_REG_LIST
822 Error about the register list operand having unexpected number of
825 AARCH64_OPDE_OTHER_ERROR
826 Error of the highest severity and used for any severe issue that does not
827 fall into any of the above categories.
829 The enumerators are only interesting to GAS. They are declared here (in
830 libopcodes) because that some errors are detected (and then notified to GAS)
831 by libopcodes (rather than by GAS solely).
833 The first three errors are only deteced by GAS while the
834 AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
835 only libopcodes has the information about the valid variants of each
838 The enumerators have an increasing severity. This is helpful when there are
839 multiple instruction templates available for a given mnemonic name (e.g.
840 FMOV); this mechanism will help choose the most suitable template from which
841 the generated diagnostics can most closely describe the issues, if any. */
843 enum aarch64_operand_error_kind
846 AARCH64_OPDE_RECOVERABLE,
847 AARCH64_OPDE_SYNTAX_ERROR,
848 AARCH64_OPDE_FATAL_SYNTAX_ERROR,
849 AARCH64_OPDE_INVALID_VARIANT,
850 AARCH64_OPDE_OUT_OF_RANGE,
851 AARCH64_OPDE_UNALIGNED,
852 AARCH64_OPDE_REG_LIST,
853 AARCH64_OPDE_OTHER_ERROR
856 /* N.B. GAS assumes that this structure work well with shallow copy. */
857 struct aarch64_operand_error
859 enum aarch64_operand_error_kind kind;
862 int data[3]; /* Some data for extra information. */
865 typedef struct aarch64_operand_error aarch64_operand_error;
867 /* Encoding entrypoint. */
870 aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
871 aarch64_insn *, aarch64_opnd_qualifier_t *,
872 aarch64_operand_error *);
874 extern const aarch64_opcode *
875 aarch64_replace_opcode (struct aarch64_inst *,
876 const aarch64_opcode *);
878 /* Given the opcode enumerator OP, return the pointer to the corresponding
881 extern const aarch64_opcode *
882 aarch64_get_opcode (enum aarch64_op);
884 /* Generate the string representation of an operand. */
886 aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
887 const aarch64_opnd_info *, int, int *, bfd_vma *);
889 /* Miscellaneous interface. */
892 aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
894 extern aarch64_opnd_qualifier_t
895 aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
896 const aarch64_opnd_qualifier_t, int);
899 aarch64_num_of_operands (const aarch64_opcode *);
902 aarch64_stack_pointer_p (const aarch64_opnd_info *);
905 int aarch64_zero_register_p (const aarch64_opnd_info *);
907 /* Given an operand qualifier, return the expected data element size
908 of a qualified operand. */
910 aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
912 extern enum aarch64_operand_class
913 aarch64_get_operand_class (enum aarch64_opnd);
916 aarch64_get_operand_name (enum aarch64_opnd);
919 aarch64_get_operand_desc (enum aarch64_opnd);
922 extern int debug_dump;
925 aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
927 #define DEBUG_TRACE(M, ...) \
930 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
933 #define DEBUG_TRACE_IF(C, M, ...) \
935 if (debug_dump && (C)) \
936 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
938 #else /* !DEBUG_AARCH64 */
939 #define DEBUG_TRACE(M, ...) ;
940 #define DEBUG_TRACE_IF(C, M, ...) ;
941 #endif /* DEBUG_AARCH64 */
943 #endif /* OPCODE_AARCH64_H */