1 /* AArch64 assembler/disassembler support.
3 Copyright (C) 2009-2015 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GNU Binutils.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
22 #ifndef OPCODE_AARCH64_H
23 #define OPCODE_AARCH64_H
26 #include "bfd_stdint.h"
34 /* The offset for pc-relative addressing is currently defined to be 0. */
35 #define AARCH64_PCREL_OFFSET 0
37 typedef uint32_t aarch64_insn;
39 /* The following bitmasks control CPU features. */
40 #define AARCH64_FEATURE_V8 0x00000001 /* All processors. */
41 #define AARCH64_FEATURE_V8_2 0x00000020 /* ARMv8.2 processors. */
42 #define AARCH64_FEATURE_CRYPTO 0x00010000 /* Crypto instructions. */
43 #define AARCH64_FEATURE_FP 0x00020000 /* FP instructions. */
44 #define AARCH64_FEATURE_SIMD 0x00040000 /* SIMD instructions. */
45 #define AARCH64_FEATURE_CRC 0x00080000 /* CRC instructions. */
46 #define AARCH64_FEATURE_LSE 0x00100000 /* LSE instructions. */
47 #define AARCH64_FEATURE_PAN 0x00200000 /* PAN instructions. */
48 #define AARCH64_FEATURE_LOR 0x00400000 /* LOR instructions. */
49 #define AARCH64_FEATURE_RDMA 0x00800000 /* v8.1 SIMD instructions. */
50 #define AARCH64_FEATURE_V8_1 0x01000000 /* v8.1 features. */
51 #define AARCH64_FEATURE_F16 0x02000000 /* v8.2 FP16 instructions. */
52 #define AARCH64_FEATURE_RAS 0x04000000 /* RAS Extensions. */
53 #define AARCH64_FEATURE_PROFILE 0x08000000 /* Statistical Profiling. */
55 /* Architectures are the sum of the base and extensions. */
56 #define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
58 | AARCH64_FEATURE_SIMD)
59 #define AARCH64_ARCH_V8_1 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
61 | AARCH64_FEATURE_SIMD \
62 | AARCH64_FEATURE_CRC \
63 | AARCH64_FEATURE_V8_1 \
64 | AARCH64_FEATURE_LSE \
65 | AARCH64_FEATURE_PAN \
66 | AARCH64_FEATURE_LOR \
67 | AARCH64_FEATURE_RDMA)
68 #define AARCH64_ARCH_V8_2 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
69 AARCH64_FEATURE_V8_2 \
70 | AARCH64_FEATURE_F16 \
71 | AARCH64_FEATURE_RAS \
72 | AARCH64_FEATURE_FP \
73 | AARCH64_FEATURE_SIMD \
74 | AARCH64_FEATURE_CRC \
75 | AARCH64_FEATURE_V8_1 \
76 | AARCH64_FEATURE_LSE \
77 | AARCH64_FEATURE_PAN \
78 | AARCH64_FEATURE_LOR \
79 | AARCH64_FEATURE_RDMA)
81 #define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0)
82 #define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */
84 /* CPU-specific features. */
85 typedef unsigned long aarch64_feature_set;
87 #define AARCH64_CPU_HAS_FEATURE(CPU,FEAT) \
88 (((CPU) & (FEAT)) != 0)
90 #define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2) \
93 (TARG) = (F1) | (F2); \
97 #define AARCH64_CLEAR_FEATURE(TARG,F1,F2) \
100 (TARG) = (F1) &~ (F2); \
104 #define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
106 #define AARCH64_OPCODE_HAS_FEATURE(OPC,FEAT) \
107 (((OPC) & (FEAT)) != 0)
109 enum aarch64_operand_class
111 AARCH64_OPND_CLASS_NIL,
112 AARCH64_OPND_CLASS_INT_REG,
113 AARCH64_OPND_CLASS_MODIFIED_REG,
114 AARCH64_OPND_CLASS_FP_REG,
115 AARCH64_OPND_CLASS_SIMD_REG,
116 AARCH64_OPND_CLASS_SIMD_ELEMENT,
117 AARCH64_OPND_CLASS_SISD_REG,
118 AARCH64_OPND_CLASS_SIMD_REGLIST,
119 AARCH64_OPND_CLASS_CP_REG,
120 AARCH64_OPND_CLASS_ADDRESS,
121 AARCH64_OPND_CLASS_IMMEDIATE,
122 AARCH64_OPND_CLASS_SYSTEM,
123 AARCH64_OPND_CLASS_COND,
126 /* Operand code that helps both parsing and coding.
127 Keep AARCH64_OPERANDS synced. */
131 AARCH64_OPND_NIL, /* no operand---MUST BE FIRST!*/
133 AARCH64_OPND_Rd, /* Integer register as destination. */
134 AARCH64_OPND_Rn, /* Integer register as source. */
135 AARCH64_OPND_Rm, /* Integer register as source. */
136 AARCH64_OPND_Rt, /* Integer register used in ld/st instructions. */
137 AARCH64_OPND_Rt2, /* Integer register used in ld/st pair instructions. */
138 AARCH64_OPND_Rs, /* Integer register used in ld/st exclusive. */
139 AARCH64_OPND_Ra, /* Integer register used in ddp_3src instructions. */
140 AARCH64_OPND_Rt_SYS, /* Integer register used in system instructions. */
142 AARCH64_OPND_Rd_SP, /* Integer Rd or SP. */
143 AARCH64_OPND_Rn_SP, /* Integer Rn or SP. */
144 AARCH64_OPND_PAIRREG, /* Paired register operand. */
145 AARCH64_OPND_Rm_EXT, /* Integer Rm extended. */
146 AARCH64_OPND_Rm_SFT, /* Integer Rm shifted. */
148 AARCH64_OPND_Fd, /* Floating-point Fd. */
149 AARCH64_OPND_Fn, /* Floating-point Fn. */
150 AARCH64_OPND_Fm, /* Floating-point Fm. */
151 AARCH64_OPND_Fa, /* Floating-point Fa. */
152 AARCH64_OPND_Ft, /* Floating-point Ft. */
153 AARCH64_OPND_Ft2, /* Floating-point Ft2. */
155 AARCH64_OPND_Sd, /* AdvSIMD Scalar Sd. */
156 AARCH64_OPND_Sn, /* AdvSIMD Scalar Sn. */
157 AARCH64_OPND_Sm, /* AdvSIMD Scalar Sm. */
159 AARCH64_OPND_Vd, /* AdvSIMD Vector Vd. */
160 AARCH64_OPND_Vn, /* AdvSIMD Vector Vn. */
161 AARCH64_OPND_Vm, /* AdvSIMD Vector Vm. */
162 AARCH64_OPND_VdD1, /* AdvSIMD <Vd>.D[1]; for FMOV only. */
163 AARCH64_OPND_VnD1, /* AdvSIMD <Vn>.D[1]; for FMOV only. */
164 AARCH64_OPND_Ed, /* AdvSIMD Vector Element Vd. */
165 AARCH64_OPND_En, /* AdvSIMD Vector Element Vn. */
166 AARCH64_OPND_Em, /* AdvSIMD Vector Element Vm. */
167 AARCH64_OPND_LVn, /* AdvSIMD Vector register list used in e.g. TBL. */
168 AARCH64_OPND_LVt, /* AdvSIMD Vector register list used in ld/st. */
169 AARCH64_OPND_LVt_AL, /* AdvSIMD Vector register list for loading single
170 structure to all lanes. */
171 AARCH64_OPND_LEt, /* AdvSIMD Vector Element list. */
173 AARCH64_OPND_Cn, /* Co-processor register in CRn field. */
174 AARCH64_OPND_Cm, /* Co-processor register in CRm field. */
176 AARCH64_OPND_IDX, /* AdvSIMD EXT index operand. */
177 AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left. */
178 AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right. */
179 AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift. */
180 AARCH64_OPND_SIMD_IMM_SFT, /* AdvSIMD modified immediate with shift. */
181 AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate. */
182 AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction
184 AARCH64_OPND_IMM0, /* Immediate for #0. */
185 AARCH64_OPND_FPIMM0, /* Immediate for #0.0. */
186 AARCH64_OPND_FPIMM, /* Floating-point Immediate. */
187 AARCH64_OPND_IMMR, /* Immediate #<immr> in e.g. BFM. */
188 AARCH64_OPND_IMMS, /* Immediate #<imms> in e.g. BFM. */
189 AARCH64_OPND_WIDTH, /* Immediate #<width> in e.g. BFI. */
190 AARCH64_OPND_IMM, /* Immediate. */
191 AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field. */
192 AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field. */
193 AARCH64_OPND_UIMM4, /* Unsigned 4-bit immediate in the CRm field. */
194 AARCH64_OPND_UIMM7, /* Unsigned 7-bit immediate in the CRm:op2 fields. */
195 AARCH64_OPND_BIT_NUM, /* Immediate. */
196 AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions. */
197 AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions. */
198 AARCH64_OPND_NZCV, /* Flag bit specifier giving an alternative value for
199 each condition flag. */
201 AARCH64_OPND_LIMM, /* Logical Immediate. */
202 AARCH64_OPND_AIMM, /* Arithmetic immediate. */
203 AARCH64_OPND_HALF, /* #<imm16>{, LSL #<shift>} operand in move wide. */
204 AARCH64_OPND_FBITS, /* FP #<fbits> operand in e.g. SCVTF */
205 AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias. */
207 AARCH64_OPND_COND, /* Standard condition as the last operand. */
208 AARCH64_OPND_COND1, /* Same as the above, but excluding AL and NV. */
210 AARCH64_OPND_ADDR_ADRP, /* Memory address for ADRP */
211 AARCH64_OPND_ADDR_PCREL14, /* 14-bit PC-relative address for e.g. TBZ. */
212 AARCH64_OPND_ADDR_PCREL19, /* 19-bit PC-relative address for e.g. LDR. */
213 AARCH64_OPND_ADDR_PCREL21, /* 21-bit PC-relative address for e.g. ADR. */
214 AARCH64_OPND_ADDR_PCREL26, /* 26-bit PC-relative address for e.g. BL. */
216 AARCH64_OPND_ADDR_SIMPLE, /* Address of ld/st exclusive. */
217 AARCH64_OPND_ADDR_REGOFF, /* Address of register offset. */
218 AARCH64_OPND_ADDR_SIMM7, /* Address of signed 7-bit immediate. */
219 AARCH64_OPND_ADDR_SIMM9, /* Address of signed 9-bit immediate. */
220 AARCH64_OPND_ADDR_SIMM9_2, /* Same as the above, but the immediate is
221 negative or unaligned and there is
222 no writeback allowed. This operand code
223 is only used to support the programmer-
224 friendly feature of using LDR/STR as the
225 the mnemonic name for LDUR/STUR instructions
226 wherever there is no ambiguity. */
227 AARCH64_OPND_ADDR_UIMM12, /* Address of unsigned 12-bit immediate. */
228 AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures. */
229 AARCH64_OPND_SIMD_ADDR_POST, /* Address of ld/st multiple post-indexed. */
231 AARCH64_OPND_SYSREG, /* System register operand. */
232 AARCH64_OPND_PSTATEFIELD, /* PSTATE field name operand. */
233 AARCH64_OPND_SYSREG_AT, /* System register <at_op> operand. */
234 AARCH64_OPND_SYSREG_DC, /* System register <dc_op> operand. */
235 AARCH64_OPND_SYSREG_IC, /* System register <ic_op> operand. */
236 AARCH64_OPND_SYSREG_TLBI, /* System register <tlbi_op> operand. */
237 AARCH64_OPND_BARRIER, /* Barrier operand. */
238 AARCH64_OPND_BARRIER_ISB, /* Barrier operand for ISB. */
239 AARCH64_OPND_PRFOP, /* Prefetch operation. */
240 AARCH64_OPND_BARRIER_PSB, /* Barrier operand for PSB. */
243 /* Qualifier constrains an operand. It either specifies a variant of an
244 operand type or limits values available to an operand type.
246 N.B. Order is important; keep aarch64_opnd_qualifiers synced. */
248 enum aarch64_opnd_qualifier
250 /* Indicating no further qualification on an operand. */
251 AARCH64_OPND_QLF_NIL,
253 /* Qualifying an operand which is a general purpose (integer) register;
254 indicating the operand data size or a specific register. */
255 AARCH64_OPND_QLF_W, /* Wn, WZR or WSP. */
256 AARCH64_OPND_QLF_X, /* Xn, XZR or XSP. */
257 AARCH64_OPND_QLF_WSP, /* WSP. */
258 AARCH64_OPND_QLF_SP, /* SP. */
260 /* Qualifying an operand which is a floating-point register, a SIMD
261 vector element or a SIMD vector element list; indicating operand data
262 size or the size of each SIMD vector element in the case of a SIMD
264 These qualifiers are also used to qualify an address operand to
265 indicate the size of data element a load/store instruction is
267 They are also used for the immediate shift operand in e.g. SSHR. Such
268 a use is only for the ease of operand encoding/decoding and qualifier
269 sequence matching; such a use should not be applied widely; use the value
270 constraint qualifiers for immediate operands wherever possible. */
271 AARCH64_OPND_QLF_S_B,
272 AARCH64_OPND_QLF_S_H,
273 AARCH64_OPND_QLF_S_S,
274 AARCH64_OPND_QLF_S_D,
275 AARCH64_OPND_QLF_S_Q,
277 /* Qualifying an operand which is a SIMD vector register or a SIMD vector
278 register list; indicating register shape.
279 They are also used for the immediate shift operand in e.g. SSHR. Such
280 a use is only for the ease of operand encoding/decoding and qualifier
281 sequence matching; such a use should not be applied widely; use the value
282 constraint qualifiers for immediate operands wherever possible. */
283 AARCH64_OPND_QLF_V_8B,
284 AARCH64_OPND_QLF_V_16B,
285 AARCH64_OPND_QLF_V_4H,
286 AARCH64_OPND_QLF_V_8H,
287 AARCH64_OPND_QLF_V_2S,
288 AARCH64_OPND_QLF_V_4S,
289 AARCH64_OPND_QLF_V_1D,
290 AARCH64_OPND_QLF_V_2D,
291 AARCH64_OPND_QLF_V_1Q,
293 /* Constraint on value. */
294 AARCH64_OPND_QLF_imm_0_7,
295 AARCH64_OPND_QLF_imm_0_15,
296 AARCH64_OPND_QLF_imm_0_31,
297 AARCH64_OPND_QLF_imm_0_63,
298 AARCH64_OPND_QLF_imm_1_32,
299 AARCH64_OPND_QLF_imm_1_64,
301 /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
303 AARCH64_OPND_QLF_LSL,
304 AARCH64_OPND_QLF_MSL,
306 /* Special qualifier helping retrieve qualifier information during the
307 decoding time (currently not in use). */
308 AARCH64_OPND_QLF_RETRIEVE,
311 /* Instruction class. */
313 enum aarch64_insn_class
368 ldst_imm9, /* immpost or immpre */
387 /* Opcode enumerators. */
431 OP_MOV_IMM_LOG, /* MOV alias for moving bitmask immediate. */
432 OP_MOV_IMM_WIDE, /* MOV alias for moving wide immediate. */
433 OP_MOV_IMM_WIDEN, /* MOV alias for moving wide immediate (negated). */
435 OP_MOV_V, /* MOV alias for moving vector register. */
448 OP_BFC, /* ARMv8.2. */
465 OP_FCVTXN_S, /* Scalar version. */
474 OP_TOTAL_NUM, /* Pseudo. */
477 /* Maximum number of operands an instruction can have. */
478 #define AARCH64_MAX_OPND_NUM 6
479 /* Maximum number of qualifier sequences an instruction can have. */
480 #define AARCH64_MAX_QLF_SEQ_NUM 10
481 /* Operand qualifier typedef; optimized for the size. */
482 typedef unsigned char aarch64_opnd_qualifier_t;
483 /* Operand qualifier sequence typedef. */
484 typedef aarch64_opnd_qualifier_t \
485 aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];
487 /* FIXME: improve the efficiency. */
488 static inline bfd_boolean
489 empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
492 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
493 if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
498 /* This structure holds information for a particular opcode. */
500 struct aarch64_opcode
502 /* The name of the mnemonic. */
505 /* The opcode itself. Those bits which will be filled in with
506 operands are zeroes. */
509 /* The opcode mask. This is used by the disassembler. This is a
510 mask containing ones indicating those bits which must match the
511 opcode field, and zeroes indicating those bits which need not
512 match (and are presumably filled in by operands). */
515 /* Instruction class. */
516 enum aarch64_insn_class iclass;
518 /* Enumerator identifier. */
521 /* Which architecture variant provides this instruction. */
522 const aarch64_feature_set *avariant;
524 /* An array of operand codes. Each code is an index into the
525 operand table. They appear in the order which the operands must
526 appear in assembly code, and are terminated by a zero. */
527 enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM];
529 /* A list of operand qualifier code sequence. Each operand qualifier
530 code qualifies the corresponding operand code. Each operand
531 qualifier sequence specifies a valid opcode variant and related
532 constraint on operands. */
533 aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
535 /* Flags providing information about this instruction */
539 typedef struct aarch64_opcode aarch64_opcode;
541 /* Table describing all the AArch64 opcodes. */
542 extern aarch64_opcode aarch64_opcode_table[];
545 #define F_ALIAS (1 << 0)
546 #define F_HAS_ALIAS (1 << 1)
547 /* Disassembly preference priority 1-3 (the larger the higher). If nothing
548 is specified, it is the priority 0 by default, i.e. the lowest priority. */
549 #define F_P1 (1 << 2)
550 #define F_P2 (2 << 2)
551 #define F_P3 (3 << 2)
552 /* Flag an instruction that is truly conditional executed, e.g. b.cond. */
553 #define F_COND (1 << 4)
554 /* Instruction has the field of 'sf'. */
555 #define F_SF (1 << 5)
556 /* Instruction has the field of 'size:Q'. */
557 #define F_SIZEQ (1 << 6)
558 /* Floating-point instruction has the field of 'type'. */
559 #define F_FPTYPE (1 << 7)
560 /* AdvSIMD scalar instruction has the field of 'size'. */
561 #define F_SSIZE (1 << 8)
562 /* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q". */
564 /* Size of GPR operand in AdvSIMD instructions encoded in Q. */
565 #define F_GPRSIZE_IN_Q (1 << 10)
566 /* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22. */
567 #define F_LDS_SIZE (1 << 11)
568 /* Optional operand; assume maximum of 1 operand can be optional. */
569 #define F_OPD0_OPT (1 << 12)
570 #define F_OPD1_OPT (2 << 12)
571 #define F_OPD2_OPT (3 << 12)
572 #define F_OPD3_OPT (4 << 12)
573 #define F_OPD4_OPT (5 << 12)
574 /* Default value for the optional operand when omitted from the assembly. */
575 #define F_DEFAULT(X) (((X) & 0x1f) << 15)
576 /* Instruction that is an alias of another instruction needs to be
577 encoded/decoded by converting it to/from the real form, followed by
578 the encoding/decoding according to the rules of the real opcode.
579 This compares to the direct coding using the alias's information.
580 N.B. this flag requires F_ALIAS to be used together. */
581 #define F_CONV (1 << 20)
582 /* Use together with F_ALIAS to indicate an alias opcode is a programmer
583 friendly pseudo instruction available only in the assembly code (thus will
584 not show up in the disassembly). */
585 #define F_PSEUDO (1 << 21)
586 /* Instruction has miscellaneous encoding/decoding rules. */
587 #define F_MISC (1 << 22)
588 /* Instruction has the field of 'N'; used in conjunction with F_SF. */
589 #define F_N (1 << 23)
590 /* Opcode dependent field. */
591 #define F_OD(X) (((X) & 0x7) << 24)
592 /* Instruction has the field of 'sz'. */
593 #define F_LSE_SZ (1 << 27)
594 /* Next bit is 28. */
596 static inline bfd_boolean
597 alias_opcode_p (const aarch64_opcode *opcode)
599 return (opcode->flags & F_ALIAS) ? TRUE : FALSE;
602 static inline bfd_boolean
603 opcode_has_alias (const aarch64_opcode *opcode)
605 return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE;
608 /* Priority for disassembling preference. */
610 opcode_priority (const aarch64_opcode *opcode)
612 return (opcode->flags >> 2) & 0x3;
615 static inline bfd_boolean
616 pseudo_opcode_p (const aarch64_opcode *opcode)
618 return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE;
621 static inline bfd_boolean
622 optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
624 return (((opcode->flags >> 12) & 0x7) == idx + 1)
628 static inline aarch64_insn
629 get_optional_operand_default_value (const aarch64_opcode *opcode)
631 return (opcode->flags >> 15) & 0x1f;
634 static inline unsigned int
635 get_opcode_dependent_value (const aarch64_opcode *opcode)
637 return (opcode->flags >> 24) & 0x7;
640 static inline bfd_boolean
641 opcode_has_special_coder (const aarch64_opcode *opcode)
643 return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
644 | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
648 struct aarch64_name_value_pair
654 extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
655 extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
656 extern const struct aarch64_name_value_pair aarch64_prfops [32];
657 extern const struct aarch64_name_value_pair aarch64_hint_options [];
666 extern const aarch64_sys_reg aarch64_sys_regs [];
667 extern const aarch64_sys_reg aarch64_pstatefields [];
668 extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *);
669 extern bfd_boolean aarch64_sys_reg_supported_p (const aarch64_feature_set,
670 const aarch64_sys_reg *);
671 extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set,
672 const aarch64_sys_reg *);
679 } aarch64_sys_ins_reg;
681 extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *);
683 aarch64_sys_ins_reg_supported_p (const aarch64_feature_set,
684 const aarch64_sys_ins_reg *);
686 extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
687 extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
688 extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
689 extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
691 /* Shift/extending operator kinds.
692 N.B. order is important; keep aarch64_operand_modifiers synced. */
693 enum aarch64_modifier_kind
712 aarch64_extend_operator_p (enum aarch64_modifier_kind);
714 enum aarch64_modifier_kind
715 aarch64_get_operand_modifier (const struct aarch64_name_value_pair *);
720 /* A list of names with the first one as the disassembly preference;
721 terminated by NULL if fewer than 3. */
722 const char *names[3];
726 extern const aarch64_cond aarch64_conds[16];
728 const aarch64_cond* get_cond_from_value (aarch64_insn value);
729 const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);
731 /* Structure representing an operand. */
733 struct aarch64_opnd_info
735 enum aarch64_opnd type;
736 aarch64_opnd_qualifier_t qualifier;
753 unsigned first_regno : 5;
754 unsigned num_regs : 3;
755 /* 1 if it is a list of reg element. */
756 unsigned has_index : 1;
757 /* Lane index; valid only when has_index is 1. */
760 /* e.g. immediate or pc relative address offset. */
766 /* e.g. address in STR (register offset). */
779 unsigned pcrel : 1; /* PC-relative. */
780 unsigned writeback : 1;
781 unsigned preind : 1; /* Pre-indexed. */
782 unsigned postind : 1; /* Post-indexed. */
784 const aarch64_cond *cond;
785 /* The encoding of the system register. */
787 /* The encoding of the PSTATE field. */
788 aarch64_insn pstatefield;
789 const aarch64_sys_ins_reg *sysins_op;
790 const struct aarch64_name_value_pair *barrier;
791 const struct aarch64_name_value_pair *hint_option;
792 const struct aarch64_name_value_pair *prfop;
795 /* Operand shifter; in use when the operand is a register offset address,
796 add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}. */
799 enum aarch64_modifier_kind kind;
801 unsigned operator_present: 1; /* Only valid during encoding. */
802 /* Value of the 'S' field in ld/st reg offset; used only in decoding. */
803 unsigned amount_present: 1;
806 unsigned skip:1; /* Operand is not completed if there is a fixup needed
807 to be done on it. In some (but not all) of these
808 cases, we need to tell libopcodes to skip the
809 constraint checking and the encoding for this
810 operand, so that the libopcodes can pick up the
811 right opcode before the operand is fixed-up. This
812 flag should only be used during the
813 assembling/encoding. */
814 unsigned present:1; /* Whether this operand is present in the assembly
815 line; not used during the disassembly. */
818 typedef struct aarch64_opnd_info aarch64_opnd_info;
820 /* Structure representing an instruction.
822 It is used during both the assembling and disassembling. The assembler
823 fills an aarch64_inst after a successful parsing and then passes it to the
824 encoding routine to do the encoding. During the disassembling, the
825 disassembler calls the decoding routine to decode a binary instruction; on a
826 successful return, such a structure will be filled with information of the
827 instruction; then the disassembler uses the information to print out the
832 /* The value of the binary instruction. */
835 /* Corresponding opcode entry. */
836 const aarch64_opcode *opcode;
838 /* Condition for a truly conditional-executed instrutions, e.g. b.cond. */
839 const aarch64_cond *cond;
841 /* Operands information. */
842 aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
845 typedef struct aarch64_inst aarch64_inst;
847 /* Diagnosis related declaration and interface. */
849 /* Operand error kind enumerators.
851 AARCH64_OPDE_RECOVERABLE
852 Less severe error found during the parsing, very possibly because that
853 GAS has picked up a wrong instruction template for the parsing.
855 AARCH64_OPDE_SYNTAX_ERROR
856 General syntax error; it can be either a user error, or simply because
857 that GAS is trying a wrong instruction template.
859 AARCH64_OPDE_FATAL_SYNTAX_ERROR
860 Definitely a user syntax error.
862 AARCH64_OPDE_INVALID_VARIANT
863 No syntax error, but the operands are not a valid combination, e.g.
866 AARCH64_OPDE_OUT_OF_RANGE
867 Error about some immediate value out of a valid range.
869 AARCH64_OPDE_UNALIGNED
870 Error about some immediate value not properly aligned (i.e. not being a
871 multiple times of a certain value).
873 AARCH64_OPDE_REG_LIST
874 Error about the register list operand having unexpected number of
877 AARCH64_OPDE_OTHER_ERROR
878 Error of the highest severity and used for any severe issue that does not
879 fall into any of the above categories.
881 The enumerators are only interesting to GAS. They are declared here (in
882 libopcodes) because that some errors are detected (and then notified to GAS)
883 by libopcodes (rather than by GAS solely).
885 The first three errors are only deteced by GAS while the
886 AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
887 only libopcodes has the information about the valid variants of each
890 The enumerators have an increasing severity. This is helpful when there are
891 multiple instruction templates available for a given mnemonic name (e.g.
892 FMOV); this mechanism will help choose the most suitable template from which
893 the generated diagnostics can most closely describe the issues, if any. */
895 enum aarch64_operand_error_kind
898 AARCH64_OPDE_RECOVERABLE,
899 AARCH64_OPDE_SYNTAX_ERROR,
900 AARCH64_OPDE_FATAL_SYNTAX_ERROR,
901 AARCH64_OPDE_INVALID_VARIANT,
902 AARCH64_OPDE_OUT_OF_RANGE,
903 AARCH64_OPDE_UNALIGNED,
904 AARCH64_OPDE_REG_LIST,
905 AARCH64_OPDE_OTHER_ERROR
908 /* N.B. GAS assumes that this structure work well with shallow copy. */
909 struct aarch64_operand_error
911 enum aarch64_operand_error_kind kind;
914 int data[3]; /* Some data for extra information. */
917 typedef struct aarch64_operand_error aarch64_operand_error;
919 /* Encoding entrypoint. */
922 aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
923 aarch64_insn *, aarch64_opnd_qualifier_t *,
924 aarch64_operand_error *);
926 extern const aarch64_opcode *
927 aarch64_replace_opcode (struct aarch64_inst *,
928 const aarch64_opcode *);
930 /* Given the opcode enumerator OP, return the pointer to the corresponding
933 extern const aarch64_opcode *
934 aarch64_get_opcode (enum aarch64_op);
936 /* Generate the string representation of an operand. */
938 aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
939 const aarch64_opnd_info *, int, int *, bfd_vma *);
941 /* Miscellaneous interface. */
944 aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
946 extern aarch64_opnd_qualifier_t
947 aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
948 const aarch64_opnd_qualifier_t, int);
951 aarch64_num_of_operands (const aarch64_opcode *);
954 aarch64_stack_pointer_p (const aarch64_opnd_info *);
957 aarch64_zero_register_p (const aarch64_opnd_info *);
960 aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean);
962 /* Given an operand qualifier, return the expected data element size
963 of a qualified operand. */
965 aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
967 extern enum aarch64_operand_class
968 aarch64_get_operand_class (enum aarch64_opnd);
971 aarch64_get_operand_name (enum aarch64_opnd);
974 aarch64_get_operand_desc (enum aarch64_opnd);
977 extern int debug_dump;
980 aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
982 #define DEBUG_TRACE(M, ...) \
985 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
988 #define DEBUG_TRACE_IF(C, M, ...) \
990 if (debug_dump && (C)) \
991 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
993 #else /* !DEBUG_AARCH64 */
994 #define DEBUG_TRACE(M, ...) ;
995 #define DEBUG_TRACE_IF(C, M, ...) ;
996 #endif /* DEBUG_AARCH64 */
1002 #endif /* OPCODE_AARCH64_H */