1 /* AArch64 assembler/disassembler support.
3 Copyright (C) 2009-2015 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GNU Binutils.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
22 #ifndef OPCODE_AARCH64_H
23 #define OPCODE_AARCH64_H
26 #include "bfd_stdint.h"
34 /* The offset for pc-relative addressing is currently defined to be 0. */
35 #define AARCH64_PCREL_OFFSET 0
37 typedef uint32_t aarch64_insn;
39 /* The following bitmasks control CPU features. */
40 #define AARCH64_FEATURE_V8 0x00000001 /* All processors. */
41 #define AARCH64_FEATURE_CRYPTO 0x00010000 /* Crypto instructions. */
42 #define AARCH64_FEATURE_FP 0x00020000 /* FP instructions. */
43 #define AARCH64_FEATURE_SIMD 0x00040000 /* SIMD instructions. */
44 #define AARCH64_FEATURE_CRC 0x00080000 /* CRC instructions. */
45 #define AARCH64_FEATURE_LSE 0x00100000 /* LSE instructions. */
46 #define AARCH64_FEATURE_PAN 0x00200000 /* PAN instructions. */
47 #define AARCH64_FEATURE_LOR 0x00400000 /* LOR instructions. */
48 #define AARCH64_FEATURE_RDMA 0x00800000 /* v8.1 SIMD instructions. */
50 /* Architectures are the sum of the base and extensions. */
51 #define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
53 | AARCH64_FEATURE_SIMD)
54 #define AARCH64_ARCH_V8_1 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
56 | AARCH64_FEATURE_SIMD \
57 | AARCH64_FEATURE_LSE \
58 | AARCH64_FEATURE_PAN \
59 | AARCH64_FEATURE_LOR \
60 | AARCH64_FEATURE_RDMA)
63 #define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0)
64 #define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */
66 /* CPU-specific features. */
67 typedef unsigned long aarch64_feature_set;
69 #define AARCH64_CPU_HAS_FEATURE(CPU,FEAT) \
70 (((CPU) & (FEAT)) != 0)
72 #define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2) \
75 (TARG) = (F1) | (F2); \
79 #define AARCH64_CLEAR_FEATURE(TARG,F1,F2) \
82 (TARG) = (F1) &~ (F2); \
86 #define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
88 #define AARCH64_OPCODE_HAS_FEATURE(OPC,FEAT) \
89 (((OPC) & (FEAT)) != 0)
91 enum aarch64_operand_class
93 AARCH64_OPND_CLASS_NIL,
94 AARCH64_OPND_CLASS_INT_REG,
95 AARCH64_OPND_CLASS_MODIFIED_REG,
96 AARCH64_OPND_CLASS_FP_REG,
97 AARCH64_OPND_CLASS_SIMD_REG,
98 AARCH64_OPND_CLASS_SIMD_ELEMENT,
99 AARCH64_OPND_CLASS_SISD_REG,
100 AARCH64_OPND_CLASS_SIMD_REGLIST,
101 AARCH64_OPND_CLASS_CP_REG,
102 AARCH64_OPND_CLASS_ADDRESS,
103 AARCH64_OPND_CLASS_IMMEDIATE,
104 AARCH64_OPND_CLASS_SYSTEM,
105 AARCH64_OPND_CLASS_COND,
108 /* Operand code that helps both parsing and coding.
109 Keep AARCH64_OPERANDS synced. */
113 AARCH64_OPND_NIL, /* no operand---MUST BE FIRST!*/
115 AARCH64_OPND_Rd, /* Integer register as destination. */
116 AARCH64_OPND_Rn, /* Integer register as source. */
117 AARCH64_OPND_Rm, /* Integer register as source. */
118 AARCH64_OPND_Rt, /* Integer register used in ld/st instructions. */
119 AARCH64_OPND_Rt2, /* Integer register used in ld/st pair instructions. */
120 AARCH64_OPND_Rs, /* Integer register used in ld/st exclusive. */
121 AARCH64_OPND_Ra, /* Integer register used in ddp_3src instructions. */
122 AARCH64_OPND_Rt_SYS, /* Integer register used in system instructions. */
124 AARCH64_OPND_Rd_SP, /* Integer Rd or SP. */
125 AARCH64_OPND_Rn_SP, /* Integer Rn or SP. */
126 AARCH64_OPND_PAIRREG, /* Paired register operand. */
127 AARCH64_OPND_Rm_EXT, /* Integer Rm extended. */
128 AARCH64_OPND_Rm_SFT, /* Integer Rm shifted. */
130 AARCH64_OPND_Fd, /* Floating-point Fd. */
131 AARCH64_OPND_Fn, /* Floating-point Fn. */
132 AARCH64_OPND_Fm, /* Floating-point Fm. */
133 AARCH64_OPND_Fa, /* Floating-point Fa. */
134 AARCH64_OPND_Ft, /* Floating-point Ft. */
135 AARCH64_OPND_Ft2, /* Floating-point Ft2. */
137 AARCH64_OPND_Sd, /* AdvSIMD Scalar Sd. */
138 AARCH64_OPND_Sn, /* AdvSIMD Scalar Sn. */
139 AARCH64_OPND_Sm, /* AdvSIMD Scalar Sm. */
141 AARCH64_OPND_Vd, /* AdvSIMD Vector Vd. */
142 AARCH64_OPND_Vn, /* AdvSIMD Vector Vn. */
143 AARCH64_OPND_Vm, /* AdvSIMD Vector Vm. */
144 AARCH64_OPND_VdD1, /* AdvSIMD <Vd>.D[1]; for FMOV only. */
145 AARCH64_OPND_VnD1, /* AdvSIMD <Vn>.D[1]; for FMOV only. */
146 AARCH64_OPND_Ed, /* AdvSIMD Vector Element Vd. */
147 AARCH64_OPND_En, /* AdvSIMD Vector Element Vn. */
148 AARCH64_OPND_Em, /* AdvSIMD Vector Element Vm. */
149 AARCH64_OPND_LVn, /* AdvSIMD Vector register list used in e.g. TBL. */
150 AARCH64_OPND_LVt, /* AdvSIMD Vector register list used in ld/st. */
151 AARCH64_OPND_LVt_AL, /* AdvSIMD Vector register list for loading single
152 structure to all lanes. */
153 AARCH64_OPND_LEt, /* AdvSIMD Vector Element list. */
155 AARCH64_OPND_Cn, /* Co-processor register in CRn field. */
156 AARCH64_OPND_Cm, /* Co-processor register in CRm field. */
158 AARCH64_OPND_IDX, /* AdvSIMD EXT index operand. */
159 AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left. */
160 AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right. */
161 AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift. */
162 AARCH64_OPND_SIMD_IMM_SFT, /* AdvSIMD modified immediate with shift. */
163 AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate. */
164 AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction
166 AARCH64_OPND_IMM0, /* Immediate for #0. */
167 AARCH64_OPND_FPIMM0, /* Immediate for #0.0. */
168 AARCH64_OPND_FPIMM, /* Floating-point Immediate. */
169 AARCH64_OPND_IMMR, /* Immediate #<immr> in e.g. BFM. */
170 AARCH64_OPND_IMMS, /* Immediate #<imms> in e.g. BFM. */
171 AARCH64_OPND_WIDTH, /* Immediate #<width> in e.g. BFI. */
172 AARCH64_OPND_IMM, /* Immediate. */
173 AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field. */
174 AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field. */
175 AARCH64_OPND_UIMM4, /* Unsigned 4-bit immediate in the CRm field. */
176 AARCH64_OPND_UIMM7, /* Unsigned 7-bit immediate in the CRm:op2 fields. */
177 AARCH64_OPND_BIT_NUM, /* Immediate. */
178 AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions. */
179 AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions. */
180 AARCH64_OPND_NZCV, /* Flag bit specifier giving an alternative value for
181 each condition flag. */
183 AARCH64_OPND_LIMM, /* Logical Immediate. */
184 AARCH64_OPND_AIMM, /* Arithmetic immediate. */
185 AARCH64_OPND_HALF, /* #<imm16>{, LSL #<shift>} operand in move wide. */
186 AARCH64_OPND_FBITS, /* FP #<fbits> operand in e.g. SCVTF */
187 AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias. */
189 AARCH64_OPND_COND, /* Standard condition as the last operand. */
190 AARCH64_OPND_COND1, /* Same as the above, but excluding AL and NV. */
192 AARCH64_OPND_ADDR_ADRP, /* Memory address for ADRP */
193 AARCH64_OPND_ADDR_PCREL14, /* 14-bit PC-relative address for e.g. TBZ. */
194 AARCH64_OPND_ADDR_PCREL19, /* 19-bit PC-relative address for e.g. LDR. */
195 AARCH64_OPND_ADDR_PCREL21, /* 21-bit PC-relative address for e.g. ADR. */
196 AARCH64_OPND_ADDR_PCREL26, /* 26-bit PC-relative address for e.g. BL. */
198 AARCH64_OPND_ADDR_SIMPLE, /* Address of ld/st exclusive. */
199 AARCH64_OPND_ADDR_REGOFF, /* Address of register offset. */
200 AARCH64_OPND_ADDR_SIMM7, /* Address of signed 7-bit immediate. */
201 AARCH64_OPND_ADDR_SIMM9, /* Address of signed 9-bit immediate. */
202 AARCH64_OPND_ADDR_SIMM9_2, /* Same as the above, but the immediate is
203 negative or unaligned and there is
204 no writeback allowed. This operand code
205 is only used to support the programmer-
206 friendly feature of using LDR/STR as the
207 the mnemonic name for LDUR/STUR instructions
208 wherever there is no ambiguity. */
209 AARCH64_OPND_ADDR_UIMM12, /* Address of unsigned 12-bit immediate. */
210 AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures. */
211 AARCH64_OPND_SIMD_ADDR_POST, /* Address of ld/st multiple post-indexed. */
213 AARCH64_OPND_SYSREG, /* System register operand. */
214 AARCH64_OPND_PSTATEFIELD, /* PSTATE field name operand. */
215 AARCH64_OPND_SYSREG_AT, /* System register <at_op> operand. */
216 AARCH64_OPND_SYSREG_DC, /* System register <dc_op> operand. */
217 AARCH64_OPND_SYSREG_IC, /* System register <ic_op> operand. */
218 AARCH64_OPND_SYSREG_TLBI, /* System register <tlbi_op> operand. */
219 AARCH64_OPND_BARRIER, /* Barrier operand. */
220 AARCH64_OPND_BARRIER_ISB, /* Barrier operand for ISB. */
221 AARCH64_OPND_PRFOP, /* Prefetch operation. */
224 /* Qualifier constrains an operand. It either specifies a variant of an
225 operand type or limits values available to an operand type.
227 N.B. Order is important; keep aarch64_opnd_qualifiers synced. */
229 enum aarch64_opnd_qualifier
231 /* Indicating no further qualification on an operand. */
232 AARCH64_OPND_QLF_NIL,
234 /* Qualifying an operand which is a general purpose (integer) register;
235 indicating the operand data size or a specific register. */
236 AARCH64_OPND_QLF_W, /* Wn, WZR or WSP. */
237 AARCH64_OPND_QLF_X, /* Xn, XZR or XSP. */
238 AARCH64_OPND_QLF_WSP, /* WSP. */
239 AARCH64_OPND_QLF_SP, /* SP. */
241 /* Qualifying an operand which is a floating-point register, a SIMD
242 vector element or a SIMD vector element list; indicating operand data
243 size or the size of each SIMD vector element in the case of a SIMD
245 These qualifiers are also used to qualify an address operand to
246 indicate the size of data element a load/store instruction is
248 They are also used for the immediate shift operand in e.g. SSHR. Such
249 a use is only for the ease of operand encoding/decoding and qualifier
250 sequence matching; such a use should not be applied widely; use the value
251 constraint qualifiers for immediate operands wherever possible. */
252 AARCH64_OPND_QLF_S_B,
253 AARCH64_OPND_QLF_S_H,
254 AARCH64_OPND_QLF_S_S,
255 AARCH64_OPND_QLF_S_D,
256 AARCH64_OPND_QLF_S_Q,
258 /* Qualifying an operand which is a SIMD vector register or a SIMD vector
259 register list; indicating register shape.
260 They are also used for the immediate shift operand in e.g. SSHR. Such
261 a use is only for the ease of operand encoding/decoding and qualifier
262 sequence matching; such a use should not be applied widely; use the value
263 constraint qualifiers for immediate operands wherever possible. */
264 AARCH64_OPND_QLF_V_8B,
265 AARCH64_OPND_QLF_V_16B,
266 AARCH64_OPND_QLF_V_4H,
267 AARCH64_OPND_QLF_V_8H,
268 AARCH64_OPND_QLF_V_2S,
269 AARCH64_OPND_QLF_V_4S,
270 AARCH64_OPND_QLF_V_1D,
271 AARCH64_OPND_QLF_V_2D,
272 AARCH64_OPND_QLF_V_1Q,
274 /* Constraint on value. */
275 AARCH64_OPND_QLF_imm_0_7,
276 AARCH64_OPND_QLF_imm_0_15,
277 AARCH64_OPND_QLF_imm_0_31,
278 AARCH64_OPND_QLF_imm_0_63,
279 AARCH64_OPND_QLF_imm_1_32,
280 AARCH64_OPND_QLF_imm_1_64,
282 /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
284 AARCH64_OPND_QLF_LSL,
285 AARCH64_OPND_QLF_MSL,
287 /* Special qualifier helping retrieve qualifier information during the
288 decoding time (currently not in use). */
289 AARCH64_OPND_QLF_RETRIEVE,
292 /* Instruction class. */
294 enum aarch64_insn_class
349 ldst_imm9, /* immpost or immpre */
368 /* Opcode enumerators. */
412 OP_MOV_IMM_LOG, /* MOV alias for moving bitmask immediate. */
413 OP_MOV_IMM_WIDE, /* MOV alias for moving wide immediate. */
414 OP_MOV_IMM_WIDEN, /* MOV alias for moving wide immediate (negated). */
416 OP_MOV_V, /* MOV alias for moving vector register. */
445 OP_FCVTXN_S, /* Scalar version. */
454 OP_TOTAL_NUM, /* Pseudo. */
457 /* Maximum number of operands an instruction can have. */
458 #define AARCH64_MAX_OPND_NUM 6
459 /* Maximum number of qualifier sequences an instruction can have. */
460 #define AARCH64_MAX_QLF_SEQ_NUM 10
461 /* Operand qualifier typedef; optimized for the size. */
462 typedef unsigned char aarch64_opnd_qualifier_t;
463 /* Operand qualifier sequence typedef. */
464 typedef aarch64_opnd_qualifier_t \
465 aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];
467 /* FIXME: improve the efficiency. */
468 static inline bfd_boolean
469 empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
472 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
473 if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
478 /* This structure holds information for a particular opcode. */
480 struct aarch64_opcode
482 /* The name of the mnemonic. */
485 /* The opcode itself. Those bits which will be filled in with
486 operands are zeroes. */
489 /* The opcode mask. This is used by the disassembler. This is a
490 mask containing ones indicating those bits which must match the
491 opcode field, and zeroes indicating those bits which need not
492 match (and are presumably filled in by operands). */
495 /* Instruction class. */
496 enum aarch64_insn_class iclass;
498 /* Enumerator identifier. */
501 /* Which architecture variant provides this instruction. */
502 const aarch64_feature_set *avariant;
504 /* An array of operand codes. Each code is an index into the
505 operand table. They appear in the order which the operands must
506 appear in assembly code, and are terminated by a zero. */
507 enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM];
509 /* A list of operand qualifier code sequence. Each operand qualifier
510 code qualifies the corresponding operand code. Each operand
511 qualifier sequence specifies a valid opcode variant and related
512 constraint on operands. */
513 aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
515 /* Flags providing information about this instruction */
519 typedef struct aarch64_opcode aarch64_opcode;
521 /* Table describing all the AArch64 opcodes. */
522 extern aarch64_opcode aarch64_opcode_table[];
525 #define F_ALIAS (1 << 0)
526 #define F_HAS_ALIAS (1 << 1)
527 /* Disassembly preference priority 1-3 (the larger the higher). If nothing
528 is specified, it is the priority 0 by default, i.e. the lowest priority. */
529 #define F_P1 (1 << 2)
530 #define F_P2 (2 << 2)
531 #define F_P3 (3 << 2)
532 /* Flag an instruction that is truly conditional executed, e.g. b.cond. */
533 #define F_COND (1 << 4)
534 /* Instruction has the field of 'sf'. */
535 #define F_SF (1 << 5)
536 /* Instruction has the field of 'size:Q'. */
537 #define F_SIZEQ (1 << 6)
538 /* Floating-point instruction has the field of 'type'. */
539 #define F_FPTYPE (1 << 7)
540 /* AdvSIMD scalar instruction has the field of 'size'. */
541 #define F_SSIZE (1 << 8)
542 /* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q". */
544 /* Size of GPR operand in AdvSIMD instructions encoded in Q. */
545 #define F_GPRSIZE_IN_Q (1 << 10)
546 /* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22. */
547 #define F_LDS_SIZE (1 << 11)
548 /* Optional operand; assume maximum of 1 operand can be optional. */
549 #define F_OPD0_OPT (1 << 12)
550 #define F_OPD1_OPT (2 << 12)
551 #define F_OPD2_OPT (3 << 12)
552 #define F_OPD3_OPT (4 << 12)
553 #define F_OPD4_OPT (5 << 12)
554 /* Default value for the optional operand when omitted from the assembly. */
555 #define F_DEFAULT(X) (((X) & 0x1f) << 15)
556 /* Instruction that is an alias of another instruction needs to be
557 encoded/decoded by converting it to/from the real form, followed by
558 the encoding/decoding according to the rules of the real opcode.
559 This compares to the direct coding using the alias's information.
560 N.B. this flag requires F_ALIAS to be used together. */
561 #define F_CONV (1 << 20)
562 /* Use together with F_ALIAS to indicate an alias opcode is a programmer
563 friendly pseudo instruction available only in the assembly code (thus will
564 not show up in the disassembly). */
565 #define F_PSEUDO (1 << 21)
566 /* Instruction has miscellaneous encoding/decoding rules. */
567 #define F_MISC (1 << 22)
568 /* Instruction has the field of 'N'; used in conjunction with F_SF. */
569 #define F_N (1 << 23)
570 /* Opcode dependent field. */
571 #define F_OD(X) (((X) & 0x7) << 24)
572 /* Instruction has the field of 'sz'. */
573 #define F_LSE_SZ (1 << 27)
574 /* Next bit is 28. */
576 static inline bfd_boolean
577 alias_opcode_p (const aarch64_opcode *opcode)
579 return (opcode->flags & F_ALIAS) ? TRUE : FALSE;
582 static inline bfd_boolean
583 opcode_has_alias (const aarch64_opcode *opcode)
585 return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE;
588 /* Priority for disassembling preference. */
590 opcode_priority (const aarch64_opcode *opcode)
592 return (opcode->flags >> 2) & 0x3;
595 static inline bfd_boolean
596 pseudo_opcode_p (const aarch64_opcode *opcode)
598 return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE;
601 static inline bfd_boolean
602 optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
604 return (((opcode->flags >> 12) & 0x7) == idx + 1)
608 static inline aarch64_insn
609 get_optional_operand_default_value (const aarch64_opcode *opcode)
611 return (opcode->flags >> 15) & 0x1f;
614 static inline unsigned int
615 get_opcode_dependent_value (const aarch64_opcode *opcode)
617 return (opcode->flags >> 24) & 0x7;
620 static inline bfd_boolean
621 opcode_has_special_coder (const aarch64_opcode *opcode)
623 return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
624 | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
628 struct aarch64_name_value_pair
634 extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
635 extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
636 extern const struct aarch64_name_value_pair aarch64_prfops [32];
645 extern const aarch64_sys_reg aarch64_sys_regs [];
646 extern const aarch64_sys_reg aarch64_pstatefields [];
647 extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *);
648 extern bfd_boolean aarch64_sys_reg_supported_p (const aarch64_feature_set,
649 const aarch64_sys_reg *);
650 extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set,
651 const aarch64_sys_reg *);
655 const char *template;
658 } aarch64_sys_ins_reg;
660 extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
661 extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
662 extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
663 extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
665 /* Shift/extending operator kinds.
666 N.B. order is important; keep aarch64_operand_modifiers synced. */
667 enum aarch64_modifier_kind
686 aarch64_extend_operator_p (enum aarch64_modifier_kind);
688 enum aarch64_modifier_kind
689 aarch64_get_operand_modifier (const struct aarch64_name_value_pair *);
694 /* A list of names with the first one as the disassembly preference;
695 terminated by NULL if fewer than 3. */
696 const char *names[3];
700 extern const aarch64_cond aarch64_conds[16];
702 const aarch64_cond* get_cond_from_value (aarch64_insn value);
703 const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);
705 /* Structure representing an operand. */
707 struct aarch64_opnd_info
709 enum aarch64_opnd type;
710 aarch64_opnd_qualifier_t qualifier;
727 unsigned first_regno : 5;
728 unsigned num_regs : 3;
729 /* 1 if it is a list of reg element. */
730 unsigned has_index : 1;
731 /* Lane index; valid only when has_index is 1. */
734 /* e.g. immediate or pc relative address offset. */
740 /* e.g. address in STR (register offset). */
753 unsigned pcrel : 1; /* PC-relative. */
754 unsigned writeback : 1;
755 unsigned preind : 1; /* Pre-indexed. */
756 unsigned postind : 1; /* Post-indexed. */
758 const aarch64_cond *cond;
759 /* The encoding of the system register. */
761 /* The encoding of the PSTATE field. */
762 aarch64_insn pstatefield;
763 const aarch64_sys_ins_reg *sysins_op;
764 const struct aarch64_name_value_pair *barrier;
765 const struct aarch64_name_value_pair *prfop;
768 /* Operand shifter; in use when the operand is a register offset address,
769 add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}. */
772 enum aarch64_modifier_kind kind;
774 unsigned operator_present: 1; /* Only valid during encoding. */
775 /* Value of the 'S' field in ld/st reg offset; used only in decoding. */
776 unsigned amount_present: 1;
779 unsigned skip:1; /* Operand is not completed if there is a fixup needed
780 to be done on it. In some (but not all) of these
781 cases, we need to tell libopcodes to skip the
782 constraint checking and the encoding for this
783 operand, so that the libopcodes can pick up the
784 right opcode before the operand is fixed-up. This
785 flag should only be used during the
786 assembling/encoding. */
787 unsigned present:1; /* Whether this operand is present in the assembly
788 line; not used during the disassembly. */
791 typedef struct aarch64_opnd_info aarch64_opnd_info;
793 /* Structure representing an instruction.
795 It is used during both the assembling and disassembling. The assembler
796 fills an aarch64_inst after a successful parsing and then passes it to the
797 encoding routine to do the encoding. During the disassembling, the
798 disassembler calls the decoding routine to decode a binary instruction; on a
799 successful return, such a structure will be filled with information of the
800 instruction; then the disassembler uses the information to print out the
805 /* The value of the binary instruction. */
808 /* Corresponding opcode entry. */
809 const aarch64_opcode *opcode;
811 /* Condition for a truly conditional-executed instrutions, e.g. b.cond. */
812 const aarch64_cond *cond;
814 /* Operands information. */
815 aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
818 typedef struct aarch64_inst aarch64_inst;
820 /* Diagnosis related declaration and interface. */
822 /* Operand error kind enumerators.
824 AARCH64_OPDE_RECOVERABLE
825 Less severe error found during the parsing, very possibly because that
826 GAS has picked up a wrong instruction template for the parsing.
828 AARCH64_OPDE_SYNTAX_ERROR
829 General syntax error; it can be either a user error, or simply because
830 that GAS is trying a wrong instruction template.
832 AARCH64_OPDE_FATAL_SYNTAX_ERROR
833 Definitely a user syntax error.
835 AARCH64_OPDE_INVALID_VARIANT
836 No syntax error, but the operands are not a valid combination, e.g.
839 AARCH64_OPDE_OUT_OF_RANGE
840 Error about some immediate value out of a valid range.
842 AARCH64_OPDE_UNALIGNED
843 Error about some immediate value not properly aligned (i.e. not being a
844 multiple times of a certain value).
846 AARCH64_OPDE_REG_LIST
847 Error about the register list operand having unexpected number of
850 AARCH64_OPDE_OTHER_ERROR
851 Error of the highest severity and used for any severe issue that does not
852 fall into any of the above categories.
854 The enumerators are only interesting to GAS. They are declared here (in
855 libopcodes) because that some errors are detected (and then notified to GAS)
856 by libopcodes (rather than by GAS solely).
858 The first three errors are only deteced by GAS while the
859 AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
860 only libopcodes has the information about the valid variants of each
863 The enumerators have an increasing severity. This is helpful when there are
864 multiple instruction templates available for a given mnemonic name (e.g.
865 FMOV); this mechanism will help choose the most suitable template from which
866 the generated diagnostics can most closely describe the issues, if any. */
868 enum aarch64_operand_error_kind
871 AARCH64_OPDE_RECOVERABLE,
872 AARCH64_OPDE_SYNTAX_ERROR,
873 AARCH64_OPDE_FATAL_SYNTAX_ERROR,
874 AARCH64_OPDE_INVALID_VARIANT,
875 AARCH64_OPDE_OUT_OF_RANGE,
876 AARCH64_OPDE_UNALIGNED,
877 AARCH64_OPDE_REG_LIST,
878 AARCH64_OPDE_OTHER_ERROR
881 /* N.B. GAS assumes that this structure work well with shallow copy. */
882 struct aarch64_operand_error
884 enum aarch64_operand_error_kind kind;
887 int data[3]; /* Some data for extra information. */
890 typedef struct aarch64_operand_error aarch64_operand_error;
892 /* Encoding entrypoint. */
895 aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
896 aarch64_insn *, aarch64_opnd_qualifier_t *,
897 aarch64_operand_error *);
899 extern const aarch64_opcode *
900 aarch64_replace_opcode (struct aarch64_inst *,
901 const aarch64_opcode *);
903 /* Given the opcode enumerator OP, return the pointer to the corresponding
906 extern const aarch64_opcode *
907 aarch64_get_opcode (enum aarch64_op);
909 /* Generate the string representation of an operand. */
911 aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
912 const aarch64_opnd_info *, int, int *, bfd_vma *);
914 /* Miscellaneous interface. */
917 aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
919 extern aarch64_opnd_qualifier_t
920 aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
921 const aarch64_opnd_qualifier_t, int);
924 aarch64_num_of_operands (const aarch64_opcode *);
927 aarch64_stack_pointer_p (const aarch64_opnd_info *);
930 aarch64_zero_register_p (const aarch64_opnd_info *);
933 aarch64_decode_insn (aarch64_insn, aarch64_inst *);
935 /* Given an operand qualifier, return the expected data element size
936 of a qualified operand. */
938 aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
940 extern enum aarch64_operand_class
941 aarch64_get_operand_class (enum aarch64_opnd);
944 aarch64_get_operand_name (enum aarch64_opnd);
947 aarch64_get_operand_desc (enum aarch64_opnd);
950 extern int debug_dump;
953 aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
955 #define DEBUG_TRACE(M, ...) \
958 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
961 #define DEBUG_TRACE_IF(C, M, ...) \
963 if (debug_dump && (C)) \
964 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
966 #else /* !DEBUG_AARCH64 */
967 #define DEBUG_TRACE(M, ...) ;
968 #define DEBUG_TRACE_IF(C, M, ...) ;
969 #endif /* DEBUG_AARCH64 */
975 #endif /* OPCODE_AARCH64_H */