1 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
3 * mips.h (INSN_LOONGSON_3A): Defined.
4 (CPU_LOONGSON_3A): Defined.
5 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
7 2010-10-09 Matt Rice <ratmice@gmail.com>
9 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
10 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
12 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
14 * arm.h (ARM_EXT_VIRT): New define.
15 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
16 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
19 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
21 * arm.h (ARM_AEXT_ADIV): New define.
22 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
24 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
26 * arm.h (ARM_EXT_OS): New define.
27 (ARM_AEXT_V6SM): Likewise.
28 (ARM_ARCH_V6SM): Likewise.
30 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
32 * arm.h (ARM_EXT_MP): Add.
33 (ARM_ARCH_V7A_MP): Likewise.
35 2010-09-22 Mike Frysinger <vapier@gentoo.org>
37 * bfin.h: Declare pseudoChr structs/defines.
39 2010-09-21 Mike Frysinger <vapier@gentoo.org>
41 * bfin.h: Strip trailing whitespace.
43 2010-07-29 DJ Delorie <dj@redhat.com>
45 * rx.h (RX_Operand_Type): Add TwoReg.
46 (RX_Opcode_ID): Remove ediv and ediv2.
48 2010-07-27 DJ Delorie <dj@redhat.com>
50 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
52 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
53 Ina Pandit <ina.pandit@kpitcummins.com>
55 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
56 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
58 Remove PROCESSOR_V850EA support.
59 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
60 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
61 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
62 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
63 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
65 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
67 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
70 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
72 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
73 (MIPS16_INSN_BRANCH): Rename to...
74 (MIPS16_INSN_COND_BRANCH): ... this.
76 2010-07-03 Alan Modra <amodra@gmail.com>
78 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
79 Renumber other PPC_OPCODE defines.
81 2010-07-03 Alan Modra <amodra@gmail.com>
83 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
85 2010-06-29 Alan Modra <amodra@gmail.com>
87 * maxq.h: Delete file.
89 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
91 * ppc.h (PPC_OPCODE_E500): Define.
93 2010-05-26 Catherine Moore <clm@codesourcery.com>
95 * opcode/mips.h (INSN_MIPS16): Remove.
97 2010-04-21 Joseph Myers <joseph@codesourcery.com>
99 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
101 2010-04-15 Nick Clifton <nickc@redhat.com>
103 * alpha.h: Update copyright notice to use GPLv3.
109 * convex.h: Likewise.
123 * m68hc11.h: Likewise.
129 * mn10200.h: Likewise.
130 * mn10300.h: Likewise.
131 * msp430.h: Likewise.
142 * score-datadep.h: Likewise.
143 * score-inst.h: Likewise.
145 * spu-insns.h: Likewise.
149 * tic54x.h: Likewise.
154 2010-03-25 Joseph Myers <joseph@codesourcery.com>
156 * tic6x-control-registers.h, tic6x-insn-formats.h,
157 tic6x-opcode-table.h, tic6x.h: New.
159 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
161 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
163 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
165 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
167 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
169 * ia64.h (ia64_find_opcode): Remove argument name.
170 (ia64_find_next_opcode): Likewise.
171 (ia64_dis_opcode): Likewise.
172 (ia64_free_opcode): Likewise.
173 (ia64_find_dependency): Likewise.
175 2009-11-22 Doug Evans <dje@sebabeach.org>
177 * cgen.h: Include bfd_stdint.h.
178 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
180 2009-11-18 Paul Brook <paul@codesourcery.com>
182 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
184 2009-11-17 Paul Brook <paul@codesourcery.com>
185 Daniel Jacobowitz <dan@codesourcery.com>
187 * arm.h (ARM_EXT_V6_DSP): Define.
188 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
189 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
191 2009-11-04 DJ Delorie <dj@redhat.com>
193 * rx.h (rx_decode_opcode) (mvtipl): Add.
194 (mvtcp, mvfcp, opecp): Remove.
196 2009-11-02 Paul Brook <paul@codesourcery.com>
198 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
199 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
200 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
201 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
202 FPU_ARCH_NEON_VFP_V4): Define.
204 2009-10-23 Doug Evans <dje@sebabeach.org>
206 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
207 * cgen.h: Update. Improve multi-inclusion macro name.
209 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
211 * ppc.h (PPC_OPCODE_476): Define.
213 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
215 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
217 2009-09-29 DJ Delorie <dj@redhat.com>
221 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
223 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
225 2009-09-21 Ben Elliston <bje@au.ibm.com>
227 * ppc.h (PPC_OPCODE_PPCA2): New.
229 2009-09-05 Martin Thuresson <martin@mtme.org>
231 * ia64.h (struct ia64_operand): Renamed member class to op_class.
233 2009-08-29 Martin Thuresson <martin@mtme.org>
235 * tic30.h (template): Rename type template to
236 insn_template. Updated code to use new name.
237 * tic54x.h (template): Rename type template to
240 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
242 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
244 2009-06-11 Anthony Green <green@moxielogic.com>
246 * moxie.h (MOXIE_F3_PCREL): Define.
247 (moxie_form3_opc_info): Grow.
249 2009-06-06 Anthony Green <green@moxielogic.com>
251 * moxie.h (MOXIE_F1_M): Define.
253 2009-04-15 Anthony Green <green@moxielogic.com>
257 2009-04-06 DJ Delorie <dj@redhat.com>
259 * h8300.h: Add relaxation attributes to MOVA opcodes.
261 2009-03-10 Alan Modra <amodra@bigpond.net.au>
263 * ppc.h (ppc_parse_cpu): Declare.
265 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
267 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
268 and _IMM11 for mbitclr and mbitset.
269 * score-datadep.h: Update dependency information.
271 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
273 * ppc.h (PPC_OPCODE_POWER7): New.
275 2009-02-06 Doug Evans <dje@google.com>
277 * i386.h: Add comment regarding sse* insns and prefixes.
279 2009-02-03 Sandip Matte <sandip@rmicorp.com>
281 * mips.h (INSN_XLR): Define.
282 (INSN_CHIP_MASK): Update.
284 (OPCODE_IS_MEMBER): Update.
285 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
287 2009-01-28 Doug Evans <dje@google.com>
289 * opcode/i386.h: Add multiple inclusion protection.
290 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
291 (EDI_REG_NUM): New macros.
292 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
293 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
294 (REX_PREFIX_P): New macro.
296 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
298 * ppc.h (struct powerpc_opcode): New field "deprecated".
299 (PPC_OPCODE_NOPOWER4): Delete.
301 2008-11-28 Joshua Kinard <kumba@gentoo.org>
303 * mips.h: Define CPU_R14000, CPU_R16000.
304 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
306 2008-11-18 Catherine Moore <clm@codesourcery.com>
308 * arm.h (FPU_NEON_FP16): New.
309 (FPU_ARCH_NEON_FP16): New.
311 2008-11-06 Chao-ying Fu <fu@mips.com>
313 * mips.h: Doucument '1' for 5-bit sync type.
315 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
317 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
320 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
322 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
324 2008-07-30 Michael J. Eager <eager@eagercon.com>
326 * ppc.h (PPC_OPCODE_405): Define.
327 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
329 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
331 * ppc.h (ppc_cpu_t): New typedef.
332 (struct powerpc_opcode <flags>): Use it.
333 (struct powerpc_operand <insert, extract>): Likewise.
334 (struct powerpc_macro <flags>): Likewise.
336 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
338 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
339 Update comment before MIPS16 field descriptors to mention MIPS16.
340 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
342 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
343 New bit masks and shift counts for cins and exts.
345 * mips.h: Document new field descriptors +Q.
346 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
348 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
350 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
351 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
353 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
355 * ppc.h: (PPC_OPCODE_E500MC): New.
357 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
359 * i386.h (MAX_OPERANDS): Set to 5.
360 (MAX_MNEM_SIZE): Changed to 20.
362 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
364 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
366 2008-03-09 Paul Brook <paul@codesourcery.com>
368 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
370 2008-03-04 Paul Brook <paul@codesourcery.com>
372 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
373 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
374 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
376 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
377 Nick Clifton <nickc@redhat.com>
380 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
381 with a 32-bit displacement but without the top bit of the 4th byte
384 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
386 * cr16.h (cr16_num_optab): Declared.
388 2008-02-14 Hakan Ardo <hakan@debian.org>
391 * avr.h (AVR_ISA_2xxe): Define.
393 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
395 * mips.h: Update copyright.
396 (INSN_CHIP_MASK): New macro.
397 (INSN_OCTEON): New macro.
398 (CPU_OCTEON): New macro.
399 (OPCODE_IS_MEMBER): Handle Octeon instructions.
401 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
403 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
405 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
407 * avr.h (AVR_ISA_USB162): Add new opcode set.
408 (AVR_ISA_AVR3): Likewise.
410 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
412 * mips.h (INSN_LOONGSON_2E): New.
413 (INSN_LOONGSON_2F): New.
414 (CPU_LOONGSON_2E): New.
415 (CPU_LOONGSON_2F): New.
416 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
418 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
420 * mips.h (INSN_ISA*): Redefine certain values as an
421 enumeration. Update comments.
422 (mips_isa_table): New.
423 (ISA_MIPS*): Redefine to match enumeration.
424 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
427 2007-08-08 Ben Elliston <bje@au.ibm.com>
429 * ppc.h (PPC_OPCODE_PPCPS): New.
431 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
433 * m68k.h: Document j K & E.
435 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
437 * cr16.h: New file for CR16 target.
439 2007-05-02 Alan Modra <amodra@bigpond.net.au>
441 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
443 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
445 * m68k.h (mcfisa_c): New.
446 (mcfusp, mcf_mask): Adjust.
448 2007-04-20 Alan Modra <amodra@bigpond.net.au>
450 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
451 (num_powerpc_operands): Declare.
452 (PPC_OPERAND_SIGNED et al): Redefine as hex.
453 (PPC_OPERAND_PLUS1): Define.
455 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
457 * i386.h (REX_MODE64): Renamed to ...
459 (REX_EXTX): Renamed to ...
461 (REX_EXTY): Renamed to ...
463 (REX_EXTZ): Renamed to ...
466 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
468 * i386.h: Add entries from config/tc-i386.h and move tables
469 to opcodes/i386-opc.h.
471 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
473 * i386.h (FloatDR): Removed.
474 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
476 2007-03-01 Alan Modra <amodra@bigpond.net.au>
478 * spu-insns.h: Add soma double-float insns.
480 2007-02-20 Thiemo Seufer <ths@mips.com>
481 Chao-Ying Fu <fu@mips.com>
483 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
484 (INSN_DSPR2): Add flag for DSP R2 instructions.
485 (M_BALIGN): New macro.
487 2007-02-14 Alan Modra <amodra@bigpond.net.au>
489 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
490 and Seg3ShortFrom with Shortform.
492 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
495 * i386.h (i386_optab): Put the real "test" before the pseudo
498 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
500 * m68k.h (m68010up): OR fido_a.
502 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
504 * m68k.h (fido_a): New.
506 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
508 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
509 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
512 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
514 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
516 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
518 * score-inst.h (enum score_insn_type): Add Insn_internal.
520 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
521 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
522 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
523 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
524 Alan Modra <amodra@bigpond.net.au>
526 * spu-insns.h: New file.
529 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
531 * ppc.h (PPC_OPCODE_CELL): Define.
533 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
535 * i386.h : Modify opcode to support for the change in POPCNT opcode
536 in amdfam10 architecture.
538 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
540 * i386.h: Replace CpuMNI with CpuSSSE3.
542 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
543 Joseph Myers <joseph@codesourcery.com>
544 Ian Lance Taylor <ian@wasabisystems.com>
545 Ben Elliston <bje@wasabisystems.com>
547 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
549 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
551 * score-datadep.h: New file.
552 * score-inst.h: New file.
554 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
556 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
557 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
560 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
561 Michael Meissner <michael.meissner@amd.com>
563 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
565 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
567 * i386.h (i386_optab): Add "nop" with memory reference.
569 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
571 * i386.h (i386_optab): Update comment for 64bit NOP.
573 2006-06-06 Ben Elliston <bje@au.ibm.com>
574 Anton Blanchard <anton@samba.org>
576 * ppc.h (PPC_OPCODE_POWER6): Define.
579 2006-06-05 Thiemo Seufer <ths@mips.com>
581 * mips.h: Improve description of MT flags.
583 2006-05-25 Richard Sandiford <richard@codesourcery.com>
585 * m68k.h (mcf_mask): Define.
587 2006-05-05 Thiemo Seufer <ths@mips.com>
588 David Ung <davidu@mips.com>
590 * mips.h (enum): Add macro M_CACHE_AB.
592 2006-05-04 Thiemo Seufer <ths@mips.com>
593 Nigel Stephens <nigel@mips.com>
594 David Ung <davidu@mips.com>
596 * mips.h: Add INSN_SMARTMIPS define.
598 2006-04-30 Thiemo Seufer <ths@mips.com>
599 David Ung <davidu@mips.com>
601 * mips.h: Defines udi bits and masks. Add description of
602 characters which may appear in the args field of udi
605 2006-04-26 Thiemo Seufer <ths@networkno.de>
607 * mips.h: Improve comments describing the bitfield instruction
610 2006-04-26 Julian Brown <julian@codesourcery.com>
612 * arm.h (FPU_VFP_EXT_V3): Define constant.
613 (FPU_NEON_EXT_V1): Likewise.
614 (FPU_VFP_HARD): Update.
615 (FPU_VFP_V3): Define macro.
616 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
618 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
620 * avr.h (AVR_ISA_PWMx): New.
622 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
624 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
625 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
626 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
627 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
628 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
630 2006-03-10 Paul Brook <paul@codesourcery.com>
632 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
634 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
636 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
637 first. Correct mask of bb "B" opcode.
639 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
641 * i386.h (i386_optab): Support Intel Merom New Instructions.
643 2006-02-24 Paul Brook <paul@codesourcery.com>
645 * arm.h: Add V7 feature bits.
647 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
649 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
651 2006-01-31 Paul Brook <paul@codesourcery.com>
652 Richard Earnshaw <rearnsha@arm.com>
654 * arm.h: Use ARM_CPU_FEATURE.
655 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
656 (arm_feature_set): Change to a structure.
657 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
658 ARM_FEATURE): New macros.
660 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
662 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
663 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
664 (ADD_PC_INCR_OPCODE): Don't define.
666 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
669 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
671 2005-11-14 David Ung <davidu@mips.com>
673 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
674 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
675 save/restore encoding of the args field.
677 2005-10-28 Dave Brolley <brolley@redhat.com>
679 Contribute the following changes:
680 2005-02-16 Dave Brolley <brolley@redhat.com>
682 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
683 cgen_isa_mask_* to cgen_bitset_*.
686 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
688 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
689 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
690 (CGEN_CPU_TABLE): Make isas a ponter.
692 2003-09-29 Dave Brolley <brolley@redhat.com>
694 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
695 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
696 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
698 2002-12-13 Dave Brolley <brolley@redhat.com>
700 * cgen.h (symcat.h): #include it.
701 (cgen-bitset.h): #include it.
702 (CGEN_ATTR_VALUE_TYPE): Now a union.
703 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
704 (CGEN_ATTR_ENTRY): 'value' now unsigned.
705 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
706 * cgen-bitset.h: New file.
708 2005-09-30 Catherine Moore <clm@cm00re.com>
712 2005-10-24 Jan Beulich <jbeulich@novell.com>
714 * ia64.h (enum ia64_opnd): Move memory operand out of set of
717 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
719 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
720 Add FLAG_STRICT to pa10 ftest opcode.
722 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
724 * hppa.h (pa_opcodes): Remove lha entries.
726 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
728 * hppa.h (FLAG_STRICT): Revise comment.
729 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
730 before corresponding pa11 opcodes. Add strict pa10 register-immediate
733 2005-09-30 Catherine Moore <clm@cm00re.com>
737 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
739 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
741 2005-09-06 Chao-ying Fu <fu@mips.com>
743 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
744 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
746 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
747 (INSN_ASE_MASK): Update to include INSN_MT.
748 (INSN_MT): New define for MT ASE.
750 2005-08-25 Chao-ying Fu <fu@mips.com>
752 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
753 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
754 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
755 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
756 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
757 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
759 (INSN_DSP): New define for DSP ASE.
761 2005-08-18 Alan Modra <amodra@bigpond.net.au>
765 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
767 * ppc.h (PPC_OPCODE_E300): Define.
769 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
771 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
773 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
776 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
779 2005-07-27 Jan Beulich <jbeulich@novell.com>
781 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
782 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
783 Add movq-s as 64-bit variants of movd-s.
785 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
787 * hppa.h: Fix punctuation in comment.
789 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
790 implicit space-register addressing. Set space-register bits on opcodes
791 using implicit space-register addressing. Add various missing pa20
792 long-immediate opcodes. Remove various opcodes using implicit 3-bit
793 space-register addressing. Use "fE" instead of "fe" in various
796 2005-07-18 Jan Beulich <jbeulich@novell.com>
798 * i386.h (i386_optab): Operands of aam and aad are unsigned.
800 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
802 * i386.h (i386_optab): Support Intel VMX Instructions.
804 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
806 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
808 2005-07-05 Jan Beulich <jbeulich@novell.com>
810 * i386.h (i386_optab): Add new insns.
812 2005-07-01 Nick Clifton <nickc@redhat.com>
814 * sparc.h: Add typedefs to structure declarations.
816 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
819 * i386.h (i386_optab): Update comments for 64bit addressing on
820 mov. Allow 64bit addressing for mov and movq.
822 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
824 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
825 respectively, in various floating-point load and store patterns.
827 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
829 * hppa.h (FLAG_STRICT): Correct comment.
830 (pa_opcodes): Update load and store entries to allow both PA 1.X and
831 PA 2.0 mneumonics when equivalent. Entries with cache control
832 completers now require PA 1.1. Adjust whitespace.
834 2005-05-19 Anton Blanchard <anton@samba.org>
836 * ppc.h (PPC_OPCODE_POWER5): Define.
838 2005-05-10 Nick Clifton <nickc@redhat.com>
840 * Update the address and phone number of the FSF organization in
841 the GPL notices in the following files:
842 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
843 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
844 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
845 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
846 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
847 tic54x.h, tic80.h, v850.h, vax.h
849 2005-05-09 Jan Beulich <jbeulich@novell.com>
851 * i386.h (i386_optab): Add ht and hnt.
853 2005-04-18 Mark Kettenis <kettenis@gnu.org>
855 * i386.h: Insert hyphens into selected VIA PadLock extensions.
856 Add xcrypt-ctr. Provide aliases without hyphens.
858 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
860 Moved from ../ChangeLog
862 2005-04-12 Paul Brook <paul@codesourcery.com>
863 * m88k.h: Rename psr macros to avoid conflicts.
865 2005-03-12 Zack Weinberg <zack@codesourcery.com>
866 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
867 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
870 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
871 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
872 Remove redundant instruction types.
873 (struct argument): X_op - new field.
874 (struct cst4_entry): Remove.
875 (no_op_insn): Declare.
877 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
878 * crx.h (enum argtype): Rename types, remove unused types.
880 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
881 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
882 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
883 (enum operand_type): Rearrange operands, edit comments.
884 replace us<N> with ui<N> for unsigned immediate.
885 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
886 displacements (respectively).
887 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
888 (instruction type): Add NO_TYPE_INS.
889 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
890 (operand_entry): New field - 'flags'.
891 (operand flags): New.
893 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
894 * crx.h (operand_type): Remove redundant types i3, i4,
896 Add new unsigned immediate types us3, us4, us5, us16.
898 2005-04-12 Mark Kettenis <kettenis@gnu.org>
900 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
901 adjust them accordingly.
903 2005-04-01 Jan Beulich <jbeulich@novell.com>
905 * i386.h (i386_optab): Add rdtscp.
907 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
909 * i386.h (i386_optab): Don't allow the `l' suffix for moving
910 between memory and segment register. Allow movq for moving between
911 general-purpose register and segment register.
913 2005-02-09 Jan Beulich <jbeulich@novell.com>
916 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
917 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
920 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
922 * m68k.h (m68008, m68ec030, m68882): Remove.
924 (cpu_m68k, cpu_cf): New.
925 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
926 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
928 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
930 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
931 * cgen.h (enum cgen_parse_operand_type): Add
932 CGEN_PARSE_OPERAND_SYMBOLIC.
934 2005-01-21 Fred Fish <fnf@specifixinc.com>
936 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
937 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
938 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
940 2005-01-19 Fred Fish <fnf@specifixinc.com>
942 * mips.h (struct mips_opcode): Add new pinfo2 member.
943 (INSN_ALIAS): New define for opcode table entries that are
944 specific instances of another entry, such as 'move' for an 'or'
946 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
947 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
949 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
951 * mips.h (CPU_RM9000): Define.
952 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
954 2004-11-25 Jan Beulich <jbeulich@novell.com>
956 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
957 to/from test registers are illegal in 64-bit mode. Add missing
958 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
959 (previously one had to explicitly encode a rex64 prefix). Re-enable
960 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
961 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
963 2004-11-23 Jan Beulich <jbeulich@novell.com>
965 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
966 available only with SSE2. Change the MMX additions introduced by SSE
967 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
968 instructions by their now designated identifier (since combining i686
969 and 3DNow! does not really imply 3DNow!A).
971 2004-11-19 Alan Modra <amodra@bigpond.net.au>
973 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
974 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
976 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
977 Vineet Sharma <vineets@noida.hcltech.com>
979 * maxq.h: New file: Disassembly information for the maxq port.
981 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
983 * i386.h (i386_optab): Put back "movzb".
985 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
987 * cris.h (enum cris_insn_version_usage): Tweak formatting and
988 comments. Remove member cris_ver_sim. Add members
989 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
990 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
991 (struct cris_support_reg, struct cris_cond15): New types.
992 (cris_conds15): Declare.
993 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
994 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
995 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
996 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
997 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1000 2004-11-04 Jan Beulich <jbeulich@novell.com>
1002 * i386.h (sldx_Suf): Remove.
1003 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1004 (q_FP): Define, implying no REX64.
1005 (x_FP, sl_FP): Imply FloatMF.
1006 (i386_optab): Split reg and mem forms of moving from segment registers
1007 so that the memory forms can ignore the 16-/32-bit operand size
1008 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1009 all non-floating-point instructions. Unite 32- and 64-bit forms of
1010 movsx, movzx, and movd. Adjust floating point operations for the above
1011 changes to the *FP macros. Add DefaultSize to floating point control
1012 insns operating on larger memory ranges. Remove left over comments
1013 hinting at certain insns being Intel-syntax ones where the ones
1014 actually meant are already gone.
1016 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1018 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1021 2004-09-30 Paul Brook <paul@codesourcery.com>
1023 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1024 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1026 2004-09-11 Theodore A. Roth <troth@openavr.org>
1028 * avr.h: Add support for
1029 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1031 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1033 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1035 2004-08-24 Dmitry Diky <diwil@spec.ru>
1037 * msp430.h (msp430_opc): Add new instructions.
1038 (msp430_rcodes): Declare new instructions.
1039 (msp430_hcodes): Likewise..
1041 2004-08-13 Nick Clifton <nickc@redhat.com>
1044 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1047 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1049 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1051 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1053 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1055 2004-07-21 Jan Beulich <jbeulich@novell.com>
1057 * i386.h: Adjust instruction descriptions to better match the
1060 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
1062 * arm.h: Remove all old content. Replace with architecture defines
1063 from gas/config/tc-arm.c.
1065 2004-07-09 Andreas Schwab <schwab@suse.de>
1067 * m68k.h: Fix comment.
1069 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1073 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1075 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1077 2004-05-24 Peter Barada <peter@the-baradas.com>
1079 * m68k.h: Add 'size' to m68k_opcode.
1081 2004-05-05 Peter Barada <peter@the-baradas.com>
1083 * m68k.h: Switch from ColdFire chip name to core variant.
1085 2004-04-22 Peter Barada <peter@the-baradas.com>
1087 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1088 descriptions for new EMAC cases.
1089 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1090 handle Motorola MAC syntax.
1091 Allow disassembly of ColdFire V4e object files.
1093 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1095 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1097 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1099 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1101 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1103 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1105 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1107 * i386.h (i386_optab): Added xstore/xcrypt insns.
1109 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1111 * h8300.h (32bit ldc/stc): Add relaxing support.
1113 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1115 * h8300.h (BITOP): Pass MEMRELAX flag.
1117 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1119 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1122 For older changes see ChangeLog-9103
1128 version-control: never