1 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
3 * mips.h (mips_decode_reg_operand): New function.
4 (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
5 (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
6 (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
8 (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
9 (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
10 (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
11 (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
12 (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
13 (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
14 (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
15 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
16 (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
17 (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
18 macros to cover the gaps.
19 (INSN2_MOD_SP): Replace with...
20 (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
21 (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
22 (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
23 (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
24 (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
27 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
29 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
30 (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
31 (MIPS16_INSN_COND_BRANCH): Delete.
33 2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
34 Kirill Yukhin <kirill.yukhin@intel.com>
35 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
37 * i386.h (BND_PREFIX_OPCODE): New.
39 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
41 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
43 (decode_mips16_operand): Declare.
45 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
47 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
48 (mips_operand, mips_int_operand, mips_mapped_int_operand)
49 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
50 (mips_pcrel_operand): New structures.
51 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
52 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
53 (decode_mips_operand, decode_micromips_operand): Declare.
55 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
57 * mips.h: Document MIPS16 "I" opcode.
59 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
61 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
62 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
63 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
64 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
65 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
66 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
67 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
68 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
69 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
70 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
71 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
72 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
73 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
75 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
78 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
80 * mips.h: Remove documentation of "[" and "]". Update documentation
81 of "k" and the MDMX formats.
83 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
85 * mips.h: Update documentation of "+s" and "+S".
87 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
89 * mips.h: Document "+i".
91 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
93 * mips.h: Remove "mi" documentation. Update "mh" documentation.
94 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
96 (INSN2_WRITE_GPR_MHI): Rename to...
97 (INSN2_WRITE_GPR_MH): ...this.
99 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
101 * mips.h: Remove documentation of "+D" and "+T".
103 2013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
105 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
106 Use "source" rather than "destination" for microMIPS "G".
108 2013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
110 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
113 2013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
115 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
117 2013-06-17 Catherine Moore <clm@codesourcery.com>
118 Maciej W. Rozycki <macro@codesourcery.com>
119 Chao-Ying Fu <fu@mips.com>
121 * mips.h (OP_SH_EVAOFFSET): Define.
122 (OP_MASK_EVAOFFSET): Define.
123 (INSN_ASE_MASK): Delete.
125 (M_CACHEE_AB, M_CACHEE_OB): New.
126 (M_LBE_OB, M_LBE_AB): New.
127 (M_LBUE_OB, M_LBUE_AB): New.
128 (M_LHE_OB, M_LHE_AB): New.
129 (M_LHUE_OB, M_LHUE_AB): New.
130 (M_LLE_AB, M_LLE_OB): New.
131 (M_LWE_OB, M_LWE_AB): New.
132 (M_LWLE_AB, M_LWLE_OB): New.
133 (M_LWRE_AB, M_LWRE_OB): New.
134 (M_PREFE_AB, M_PREFE_OB): New.
135 (M_SCE_AB, M_SCE_OB): New.
136 (M_SBE_OB, M_SBE_AB): New.
137 (M_SHE_OB, M_SHE_AB): New.
138 (M_SWE_OB, M_SWE_AB): New.
139 (M_SWLE_AB, M_SWLE_OB): New.
140 (M_SWRE_AB, M_SWRE_OB): New.
141 (MICROMIPSOP_SH_EVAOFFSET): Define.
142 (MICROMIPSOP_MASK_EVAOFFSET): Define.
144 2013-06-12 Sandra Loosemore <sandra@codesourcery.com>
146 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
148 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
150 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
152 2013-05-09 Andrew Pinski <apinski@cavium.com>
154 * mips.h (OP_MASK_CODE10): Correct definition.
155 (OP_SH_CODE10): Likewise.
156 Add a comment that "+J" is used now for OP_*CODE10.
157 (INSN_ASE_MASK): Update.
158 (INSN_VIRT): New macro.
159 (INSN_VIRT64): New macro
161 2013-05-02 Nick Clifton <nickc@redhat.com>
163 * msp430.h: Add patterns for MSP430X instructions.
165 2013-04-06 David S. Miller <davem@davemloft.net>
167 * sparc.h (F_PREFERRED): Define.
168 (F_PREF_ALIAS): Define.
170 2013-04-03 Nick Clifton <nickc@redhat.com>
172 * v850.h (V850_INVERSE_PCREL): Define.
174 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
177 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
179 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
182 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
184 * tic6xc-opcode-table.h: Add 16-bit insns.
185 * tic6x.h: Add support for 16-bit insns.
187 2013-03-21 Michael Schewe <michael.schewe@gmx.net>
189 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
190 and mov.b/w/l Rs,@(d:32,ERd).
192 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
195 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
196 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
197 tic6x_operand_xregpair operand coding type.
198 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
199 opcode field, usu ORXREGD1324 for the src2 operand and remove the
202 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
205 * tic6x.h (enum tic6x_coding_method): Add
206 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
207 separately the msb and lsb of a register pair. This is needed to
208 encode the opcodes in the same way as TI assembler does.
209 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
210 and rsqrdp opcodes to use the new field coding types.
212 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
214 * arm.h (CRC_EXT_ARMV8): New constant.
215 (ARCH_CRC_ARMV8): New macro.
217 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
219 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
221 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
222 Andrew Jenner <andrew@codesourcery.com>
224 Based on patches from Altera Corporation.
228 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
230 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
232 2013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
235 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
237 2013-01-24 Nick Clifton <nickc@redhat.com>
239 * v850.h: Add e3v5 support.
241 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
243 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
245 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
247 * ppc.h (PPC_OPCODE_POWER8): New define.
248 (PPC_OPCODE_HTM): Likewise.
250 2013-01-10 Will Newton <will.newton@imgtec.com>
254 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
256 * cr16.h (make_instruction): Rename to cr16_make_instruction.
257 (match_opcode): Rename to cr16_match_opcode.
259 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
261 * mips.h: Add support for r5900 instructions including lq and sq.
263 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
265 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
266 (make_instruction,match_opcode): Added function prototypes.
267 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
269 2012-11-23 Alan Modra <amodra@gmail.com>
271 * ppc.h (ppc_parse_cpu): Update prototype.
273 2012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
275 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
276 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
278 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
280 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
282 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
284 * ia64.h (ia64_opnd): Add new operand types.
286 2012-08-21 David S. Miller <davem@davemloft.net>
288 * sparc.h (F3F4): New macro.
290 2012-08-13 Ian Bolton <ian.bolton@arm.com>
291 Laurent Desnogues <laurent.desnogues@arm.com>
292 Jim MacArthur <jim.macarthur@arm.com>
293 Marcus Shawcroft <marcus.shawcroft@arm.com>
294 Nigel Stephens <nigel.stephens@arm.com>
295 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
296 Richard Earnshaw <rearnsha@arm.com>
297 Sofiane Naci <sofiane.naci@arm.com>
298 Tejas Belagod <tejas.belagod@arm.com>
299 Yufeng Zhang <yufeng.zhang@arm.com>
301 * aarch64.h: New file.
303 2012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
304 Maciej W. Rozycki <macro@codesourcery.com>
306 * mips.h (mips_opcode): Add the exclusions field.
307 (OPCODE_IS_MEMBER): Remove macro.
308 (cpu_is_member): New inline function.
309 (opcode_is_member): Likewise.
311 2012-07-31 Chao-Ying Fu <fu@mips.com>
312 Catherine Moore <clm@codesourcery.com>
313 Maciej W. Rozycki <macro@codesourcery.com>
315 * mips.h: Document microMIPS DSP ASE usage.
316 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
317 microMIPS DSP ASE support.
318 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
319 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
320 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
321 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
322 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
323 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
324 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
326 2012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
328 * mips.h: Fix a typo in description.
330 2012-06-07 Georg-Johann Lay <avr@gjlay.de>
332 * avr.h: (AVR_ISA_XCH): New define.
333 (AVR_ISA_XMEGA): Use it.
334 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
336 2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
338 * m68hc11.h: Add XGate definitions.
339 (struct m68hc11_opcode): Add xg_mask field.
341 2012-05-14 Catherine Moore <clm@codesourcery.com>
342 Maciej W. Rozycki <macro@codesourcery.com>
343 Rhonda Wittels <rhonda@codesourcery.com>
345 * ppc.h (PPC_OPCODE_VLE): New definition.
346 (PPC_OP_SA): New macro.
347 (PPC_OP_SE_VLE): New macro.
348 (PPC_OP): Use a variable shift amount.
349 (powerpc_operand): Update comments.
350 (PPC_OPSHIFT_INV): New macro.
351 (PPC_OPERAND_CR): Replace with...
352 (PPC_OPERAND_CR_BIT): ...this and
353 (PPC_OPERAND_CR_REG): ...this.
356 2012-05-03 Sean Keys <skeys@ipdatasys.com>
358 * xgate.h: Header file for XGATE assembler.
360 2012-04-27 David S. Miller <davem@davemloft.net>
362 * sparc.h: Document new arg code' )' for crypto RS3
365 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
366 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
367 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
368 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
369 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
370 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
371 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
372 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
373 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
374 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
375 HWCAP_CBCOND, HWCAP_CRC32): New defines.
377 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
379 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
381 2012-02-27 Alan Modra <amodra@gmail.com>
383 * crx.h (cst4_map): Update declaration.
385 2012-02-25 Walter Lee <walt@tilera.com>
387 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
389 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
390 TILEPRO_OPC_LW_TLS_SN.
392 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
394 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
395 (XRELEASE_PREFIX_OPCODE): Likewise.
397 2011-12-08 Andrew Pinski <apinski@cavium.com>
398 Adam Nemet <anemet@caviumnetworks.com>
400 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
401 (INSN_OCTEON2): New macro.
402 (CPU_OCTEON2): New macro.
403 (OPCODE_IS_MEMBER): Add Octeon2.
405 2011-11-29 Andrew Pinski <apinski@cavium.com>
407 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
408 (INSN_OCTEONP): New macro.
409 (CPU_OCTEONP): New macro.
410 (OPCODE_IS_MEMBER): Add Octeon+.
411 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
413 2011-11-01 DJ Delorie <dj@redhat.com>
417 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
419 * mips.h: Fix a typo in description.
421 2011-09-21 David S. Miller <davem@davemloft.net>
423 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
424 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
425 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
426 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
428 2011-08-09 Chao-ying Fu <fu@mips.com>
429 Maciej W. Rozycki <macro@codesourcery.com>
431 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
432 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
433 (INSN_ASE_MASK): Add the MCU bit.
434 (INSN_MCU): New macro.
435 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
436 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
438 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
440 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
441 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
442 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
443 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
444 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
445 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
446 (INSN2_READ_GPR_MMN): Likewise.
447 (INSN2_READ_FPR_D): Change the bit used.
448 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
449 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
450 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
451 (INSN2_COND_BRANCH): Likewise.
452 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
453 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
454 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
455 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
456 (INSN2_MOD_GPR_MN): Likewise.
458 2011-08-05 David S. Miller <davem@davemloft.net>
460 * sparc.h: Document new format codes '4', '5', and '('.
461 (OPF_LOW4, RS3): New macros.
463 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
465 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
466 order of flags documented.
468 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
470 * mips.h: Clarify the description of microMIPS instruction
472 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
474 2011-07-24 Chao-ying Fu <fu@mips.com>
475 Maciej W. Rozycki <macro@codesourcery.com>
477 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
478 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
479 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
480 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
481 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
482 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
483 (OP_MASK_RS3, OP_SH_RS3): Likewise.
484 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
485 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
486 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
487 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
488 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
489 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
490 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
491 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
492 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
493 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
494 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
495 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
496 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
497 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
498 (INSN_WRITE_GPR_S): New macro.
499 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
500 (INSN2_READ_FPR_D): Likewise.
501 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
502 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
503 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
504 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
505 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
506 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
507 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
508 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
509 (CPU_MICROMIPS): New macro.
510 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
511 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
512 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
513 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
514 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
515 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
516 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
517 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
518 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
519 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
520 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
521 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
522 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
523 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
524 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
525 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
526 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
527 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
528 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
529 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
530 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
531 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
532 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
533 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
534 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
535 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
536 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
537 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
538 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
539 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
540 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
541 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
542 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
543 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
544 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
545 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
546 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
547 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
548 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
549 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
550 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
551 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
552 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
553 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
554 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
555 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
556 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
557 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
558 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
559 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
560 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
561 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
562 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
563 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
564 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
565 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
566 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
567 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
568 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
569 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
570 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
571 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
572 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
573 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
574 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
575 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
576 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
577 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
578 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
579 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
580 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
581 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
582 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
583 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
584 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
585 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
586 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
587 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
588 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
589 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
590 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
591 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
592 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
593 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
594 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
595 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
596 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
597 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
598 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
599 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
600 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
601 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
602 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
603 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
604 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
605 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
606 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
607 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
608 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
609 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
610 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
611 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
612 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
613 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
614 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
615 (micromips_opcodes): New declaration.
616 (bfd_micromips_num_opcodes): Likewise.
618 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
620 * mips.h (INSN_TRAP): Rename to...
621 (INSN_NO_DELAY_SLOT): ... this.
622 (INSN_SYNC): Remove macro.
624 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
626 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
627 a duplicate of AVR_ISA_SPM.
629 2011-07-01 Nick Clifton <nickc@redhat.com>
631 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
633 2011-06-18 Robin Getz <robin.getz@analog.com>
635 * bfin.h (is_macmod_signed): New func
637 2011-06-18 Mike Frysinger <vapier@gentoo.org>
639 * bfin.h (is_macmod_pmove): Add missing space before func args.
640 (is_macmod_hmove): Likewise.
642 2011-06-13 Walter Lee <walt@tilera.com>
644 * tilegx.h: New file.
645 * tilepro.h: New file.
647 2011-05-31 Paul Brook <paul@codesourcery.com>
649 * arm.h (ARM_ARCH_V7R_IDIV): Define.
651 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
653 * s390.h: Replace S390_OPERAND_REG_EVEN with
654 S390_OPERAND_REG_PAIR.
656 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
658 * s390.h: Add S390_OPCODE_REG_EVEN flag.
660 2011-04-18 Julian Brown <julian@codesourcery.com>
662 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
664 2011-04-11 Dan McDonald <dan@wellkeeper.com>
667 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
669 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
671 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
672 New instruction set flags.
673 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
675 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
677 * mips.h (M_PREF_AB): New enum value.
679 2011-02-12 Mike Frysinger <vapier@gentoo.org>
681 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
683 (is_macmod_pmove, is_macmod_hmove): New functions.
685 2011-02-11 Mike Frysinger <vapier@gentoo.org>
687 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
689 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
691 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
692 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
694 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
697 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
700 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
703 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
705 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
707 * mips.h: Update commentary after last commit.
709 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
711 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
712 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
713 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
715 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
717 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
719 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
721 * mips.h: Fix previous commit.
723 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
725 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
726 (INSN_LOONGSON_3A): Clear bit 31.
728 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
731 * arm.h (ARM_AEXT_V6M_ONLY): New define.
732 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
733 (ARM_ARCH_V6M_ONLY): New define.
735 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
737 * mips.h (INSN_LOONGSON_3A): Defined.
738 (CPU_LOONGSON_3A): Defined.
739 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
741 2010-10-09 Matt Rice <ratmice@gmail.com>
743 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
744 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
746 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
748 * arm.h (ARM_EXT_VIRT): New define.
749 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
750 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
753 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
755 * arm.h (ARM_AEXT_ADIV): New define.
756 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
758 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
760 * arm.h (ARM_EXT_OS): New define.
761 (ARM_AEXT_V6SM): Likewise.
762 (ARM_ARCH_V6SM): Likewise.
764 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
766 * arm.h (ARM_EXT_MP): Add.
767 (ARM_ARCH_V7A_MP): Likewise.
769 2010-09-22 Mike Frysinger <vapier@gentoo.org>
771 * bfin.h: Declare pseudoChr structs/defines.
773 2010-09-21 Mike Frysinger <vapier@gentoo.org>
775 * bfin.h: Strip trailing whitespace.
777 2010-07-29 DJ Delorie <dj@redhat.com>
779 * rx.h (RX_Operand_Type): Add TwoReg.
780 (RX_Opcode_ID): Remove ediv and ediv2.
782 2010-07-27 DJ Delorie <dj@redhat.com>
784 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
786 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
787 Ina Pandit <ina.pandit@kpitcummins.com>
789 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
790 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
791 PROCESSOR_V850E2_ALL.
792 Remove PROCESSOR_V850EA support.
793 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
794 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
795 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
796 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
797 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
798 V850_OPERAND_PERCENT.
799 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
801 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
804 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
806 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
807 (MIPS16_INSN_BRANCH): Rename to...
808 (MIPS16_INSN_COND_BRANCH): ... this.
810 2010-07-03 Alan Modra <amodra@gmail.com>
812 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
813 Renumber other PPC_OPCODE defines.
815 2010-07-03 Alan Modra <amodra@gmail.com>
817 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
819 2010-06-29 Alan Modra <amodra@gmail.com>
821 * maxq.h: Delete file.
823 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
825 * ppc.h (PPC_OPCODE_E500): Define.
827 2010-05-26 Catherine Moore <clm@codesourcery.com>
829 * opcode/mips.h (INSN_MIPS16): Remove.
831 2010-04-21 Joseph Myers <joseph@codesourcery.com>
833 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
835 2010-04-15 Nick Clifton <nickc@redhat.com>
837 * alpha.h: Update copyright notice to use GPLv3.
843 * convex.h: Likewise.
857 * m68hc11.h: Likewise.
863 * mn10200.h: Likewise.
864 * mn10300.h: Likewise.
865 * msp430.h: Likewise.
876 * score-datadep.h: Likewise.
877 * score-inst.h: Likewise.
879 * spu-insns.h: Likewise.
883 * tic54x.h: Likewise.
888 2010-03-25 Joseph Myers <joseph@codesourcery.com>
890 * tic6x-control-registers.h, tic6x-insn-formats.h,
891 tic6x-opcode-table.h, tic6x.h: New.
893 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
895 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
897 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
899 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
901 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
903 * ia64.h (ia64_find_opcode): Remove argument name.
904 (ia64_find_next_opcode): Likewise.
905 (ia64_dis_opcode): Likewise.
906 (ia64_free_opcode): Likewise.
907 (ia64_find_dependency): Likewise.
909 2009-11-22 Doug Evans <dje@sebabeach.org>
911 * cgen.h: Include bfd_stdint.h.
912 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
914 2009-11-18 Paul Brook <paul@codesourcery.com>
916 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
918 2009-11-17 Paul Brook <paul@codesourcery.com>
919 Daniel Jacobowitz <dan@codesourcery.com>
921 * arm.h (ARM_EXT_V6_DSP): Define.
922 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
923 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
925 2009-11-04 DJ Delorie <dj@redhat.com>
927 * rx.h (rx_decode_opcode) (mvtipl): Add.
928 (mvtcp, mvfcp, opecp): Remove.
930 2009-11-02 Paul Brook <paul@codesourcery.com>
932 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
933 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
934 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
935 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
936 FPU_ARCH_NEON_VFP_V4): Define.
938 2009-10-23 Doug Evans <dje@sebabeach.org>
940 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
941 * cgen.h: Update. Improve multi-inclusion macro name.
943 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
945 * ppc.h (PPC_OPCODE_476): Define.
947 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
949 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
951 2009-09-29 DJ Delorie <dj@redhat.com>
955 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
957 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
959 2009-09-21 Ben Elliston <bje@au.ibm.com>
961 * ppc.h (PPC_OPCODE_PPCA2): New.
963 2009-09-05 Martin Thuresson <martin@mtme.org>
965 * ia64.h (struct ia64_operand): Renamed member class to op_class.
967 2009-08-29 Martin Thuresson <martin@mtme.org>
969 * tic30.h (template): Rename type template to
970 insn_template. Updated code to use new name.
971 * tic54x.h (template): Rename type template to
974 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
976 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
978 2009-06-11 Anthony Green <green@moxielogic.com>
980 * moxie.h (MOXIE_F3_PCREL): Define.
981 (moxie_form3_opc_info): Grow.
983 2009-06-06 Anthony Green <green@moxielogic.com>
985 * moxie.h (MOXIE_F1_M): Define.
987 2009-04-15 Anthony Green <green@moxielogic.com>
991 2009-04-06 DJ Delorie <dj@redhat.com>
993 * h8300.h: Add relaxation attributes to MOVA opcodes.
995 2009-03-10 Alan Modra <amodra@bigpond.net.au>
997 * ppc.h (ppc_parse_cpu): Declare.
999 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
1001 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1002 and _IMM11 for mbitclr and mbitset.
1003 * score-datadep.h: Update dependency information.
1005 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
1007 * ppc.h (PPC_OPCODE_POWER7): New.
1009 2009-02-06 Doug Evans <dje@google.com>
1011 * i386.h: Add comment regarding sse* insns and prefixes.
1013 2009-02-03 Sandip Matte <sandip@rmicorp.com>
1015 * mips.h (INSN_XLR): Define.
1016 (INSN_CHIP_MASK): Update.
1018 (OPCODE_IS_MEMBER): Update.
1019 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1021 2009-01-28 Doug Evans <dje@google.com>
1023 * opcode/i386.h: Add multiple inclusion protection.
1024 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1025 (EDI_REG_NUM): New macros.
1026 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1027 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1028 (REX_PREFIX_P): New macro.
1030 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
1032 * ppc.h (struct powerpc_opcode): New field "deprecated".
1033 (PPC_OPCODE_NOPOWER4): Delete.
1035 2008-11-28 Joshua Kinard <kumba@gentoo.org>
1037 * mips.h: Define CPU_R14000, CPU_R16000.
1038 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
1040 2008-11-18 Catherine Moore <clm@codesourcery.com>
1042 * arm.h (FPU_NEON_FP16): New.
1043 (FPU_ARCH_NEON_FP16): New.
1045 2008-11-06 Chao-ying Fu <fu@mips.com>
1047 * mips.h: Doucument '1' for 5-bit sync type.
1049 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1051 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1054 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1056 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1058 2008-07-30 Michael J. Eager <eager@eagercon.com>
1060 * ppc.h (PPC_OPCODE_405): Define.
1061 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1063 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1065 * ppc.h (ppc_cpu_t): New typedef.
1066 (struct powerpc_opcode <flags>): Use it.
1067 (struct powerpc_operand <insert, extract>): Likewise.
1068 (struct powerpc_macro <flags>): Likewise.
1070 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1072 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1073 Update comment before MIPS16 field descriptors to mention MIPS16.
1074 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1076 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1077 New bit masks and shift counts for cins and exts.
1079 * mips.h: Document new field descriptors +Q.
1080 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1082 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1084 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
1085 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1087 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
1089 * ppc.h: (PPC_OPCODE_E500MC): New.
1091 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1093 * i386.h (MAX_OPERANDS): Set to 5.
1094 (MAX_MNEM_SIZE): Changed to 20.
1096 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1098 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1100 2008-03-09 Paul Brook <paul@codesourcery.com>
1102 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1104 2008-03-04 Paul Brook <paul@codesourcery.com>
1106 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1107 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1108 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1110 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
1111 Nick Clifton <nickc@redhat.com>
1114 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1115 with a 32-bit displacement but without the top bit of the 4th byte
1118 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1120 * cr16.h (cr16_num_optab): Declared.
1122 2008-02-14 Hakan Ardo <hakan@debian.org>
1125 * avr.h (AVR_ISA_2xxe): Define.
1127 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1129 * mips.h: Update copyright.
1130 (INSN_CHIP_MASK): New macro.
1131 (INSN_OCTEON): New macro.
1132 (CPU_OCTEON): New macro.
1133 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1135 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1137 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1139 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1141 * avr.h (AVR_ISA_USB162): Add new opcode set.
1142 (AVR_ISA_AVR3): Likewise.
1144 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1146 * mips.h (INSN_LOONGSON_2E): New.
1147 (INSN_LOONGSON_2F): New.
1148 (CPU_LOONGSON_2E): New.
1149 (CPU_LOONGSON_2F): New.
1150 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1152 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1154 * mips.h (INSN_ISA*): Redefine certain values as an
1155 enumeration. Update comments.
1156 (mips_isa_table): New.
1157 (ISA_MIPS*): Redefine to match enumeration.
1158 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1161 2007-08-08 Ben Elliston <bje@au.ibm.com>
1163 * ppc.h (PPC_OPCODE_PPCPS): New.
1165 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1167 * m68k.h: Document j K & E.
1169 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1171 * cr16.h: New file for CR16 target.
1173 2007-05-02 Alan Modra <amodra@bigpond.net.au>
1175 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1177 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1179 * m68k.h (mcfisa_c): New.
1180 (mcfusp, mcf_mask): Adjust.
1182 2007-04-20 Alan Modra <amodra@bigpond.net.au>
1184 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1185 (num_powerpc_operands): Declare.
1186 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1187 (PPC_OPERAND_PLUS1): Define.
1189 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
1191 * i386.h (REX_MODE64): Renamed to ...
1193 (REX_EXTX): Renamed to ...
1195 (REX_EXTY): Renamed to ...
1197 (REX_EXTZ): Renamed to ...
1200 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1202 * i386.h: Add entries from config/tc-i386.h and move tables
1203 to opcodes/i386-opc.h.
1205 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1207 * i386.h (FloatDR): Removed.
1208 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1210 2007-03-01 Alan Modra <amodra@bigpond.net.au>
1212 * spu-insns.h: Add soma double-float insns.
1214 2007-02-20 Thiemo Seufer <ths@mips.com>
1215 Chao-Ying Fu <fu@mips.com>
1217 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1218 (INSN_DSPR2): Add flag for DSP R2 instructions.
1219 (M_BALIGN): New macro.
1221 2007-02-14 Alan Modra <amodra@bigpond.net.au>
1223 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1224 and Seg3ShortFrom with Shortform.
1226 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1229 * i386.h (i386_optab): Put the real "test" before the pseudo
1232 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
1234 * m68k.h (m68010up): OR fido_a.
1236 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
1238 * m68k.h (fido_a): New.
1240 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
1242 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1243 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1246 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1248 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1250 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1252 * score-inst.h (enum score_insn_type): Add Insn_internal.
1254 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1255 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1256 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1257 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1258 Alan Modra <amodra@bigpond.net.au>
1260 * spu-insns.h: New file.
1263 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1265 * ppc.h (PPC_OPCODE_CELL): Define.
1267 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1269 * i386.h : Modify opcode to support for the change in POPCNT opcode
1270 in amdfam10 architecture.
1272 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1274 * i386.h: Replace CpuMNI with CpuSSSE3.
1276 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
1277 Joseph Myers <joseph@codesourcery.com>
1278 Ian Lance Taylor <ian@wasabisystems.com>
1279 Ben Elliston <bje@wasabisystems.com>
1281 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1283 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1285 * score-datadep.h: New file.
1286 * score-inst.h: New file.
1288 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1290 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1291 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1292 movdq2q and movq2dq.
1294 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1295 Michael Meissner <michael.meissner@amd.com>
1297 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1299 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1301 * i386.h (i386_optab): Add "nop" with memory reference.
1303 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1305 * i386.h (i386_optab): Update comment for 64bit NOP.
1307 2006-06-06 Ben Elliston <bje@au.ibm.com>
1308 Anton Blanchard <anton@samba.org>
1310 * ppc.h (PPC_OPCODE_POWER6): Define.
1313 2006-06-05 Thiemo Seufer <ths@mips.com>
1315 * mips.h: Improve description of MT flags.
1317 2006-05-25 Richard Sandiford <richard@codesourcery.com>
1319 * m68k.h (mcf_mask): Define.
1321 2006-05-05 Thiemo Seufer <ths@mips.com>
1322 David Ung <davidu@mips.com>
1324 * mips.h (enum): Add macro M_CACHE_AB.
1326 2006-05-04 Thiemo Seufer <ths@mips.com>
1327 Nigel Stephens <nigel@mips.com>
1328 David Ung <davidu@mips.com>
1330 * mips.h: Add INSN_SMARTMIPS define.
1332 2006-04-30 Thiemo Seufer <ths@mips.com>
1333 David Ung <davidu@mips.com>
1335 * mips.h: Defines udi bits and masks. Add description of
1336 characters which may appear in the args field of udi
1339 2006-04-26 Thiemo Seufer <ths@networkno.de>
1341 * mips.h: Improve comments describing the bitfield instruction
1344 2006-04-26 Julian Brown <julian@codesourcery.com>
1346 * arm.h (FPU_VFP_EXT_V3): Define constant.
1347 (FPU_NEON_EXT_V1): Likewise.
1348 (FPU_VFP_HARD): Update.
1349 (FPU_VFP_V3): Define macro.
1350 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1352 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
1354 * avr.h (AVR_ISA_PWMx): New.
1356 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1358 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1359 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1360 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1361 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1362 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1364 2006-03-10 Paul Brook <paul@codesourcery.com>
1366 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1368 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1370 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1371 first. Correct mask of bb "B" opcode.
1373 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1375 * i386.h (i386_optab): Support Intel Merom New Instructions.
1377 2006-02-24 Paul Brook <paul@codesourcery.com>
1379 * arm.h: Add V7 feature bits.
1381 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1383 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1385 2006-01-31 Paul Brook <paul@codesourcery.com>
1386 Richard Earnshaw <rearnsha@arm.com>
1388 * arm.h: Use ARM_CPU_FEATURE.
1389 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1390 (arm_feature_set): Change to a structure.
1391 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1392 ARM_FEATURE): New macros.
1394 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
1396 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1397 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1398 (ADD_PC_INCR_OPCODE): Don't define.
1400 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1403 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1405 2005-11-14 David Ung <davidu@mips.com>
1407 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1408 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1409 save/restore encoding of the args field.
1411 2005-10-28 Dave Brolley <brolley@redhat.com>
1413 Contribute the following changes:
1414 2005-02-16 Dave Brolley <brolley@redhat.com>
1416 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1417 cgen_isa_mask_* to cgen_bitset_*.
1420 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1422 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1423 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1424 (CGEN_CPU_TABLE): Make isas a ponter.
1426 2003-09-29 Dave Brolley <brolley@redhat.com>
1428 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1429 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1430 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1432 2002-12-13 Dave Brolley <brolley@redhat.com>
1434 * cgen.h (symcat.h): #include it.
1435 (cgen-bitset.h): #include it.
1436 (CGEN_ATTR_VALUE_TYPE): Now a union.
1437 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1438 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1439 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1440 * cgen-bitset.h: New file.
1442 2005-09-30 Catherine Moore <clm@cm00re.com>
1446 2005-10-24 Jan Beulich <jbeulich@novell.com>
1448 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1451 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1453 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1454 Add FLAG_STRICT to pa10 ftest opcode.
1456 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1458 * hppa.h (pa_opcodes): Remove lha entries.
1460 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1462 * hppa.h (FLAG_STRICT): Revise comment.
1463 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1464 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1467 2005-09-30 Catherine Moore <clm@cm00re.com>
1471 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1473 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1475 2005-09-06 Chao-ying Fu <fu@mips.com>
1477 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1478 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1480 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1481 (INSN_ASE_MASK): Update to include INSN_MT.
1482 (INSN_MT): New define for MT ASE.
1484 2005-08-25 Chao-ying Fu <fu@mips.com>
1486 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1487 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1488 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1489 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1490 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1491 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1493 (INSN_DSP): New define for DSP ASE.
1495 2005-08-18 Alan Modra <amodra@bigpond.net.au>
1499 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1501 * ppc.h (PPC_OPCODE_E300): Define.
1503 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1505 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1507 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1510 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1513 2005-07-27 Jan Beulich <jbeulich@novell.com>
1515 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1516 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1517 Add movq-s as 64-bit variants of movd-s.
1519 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1521 * hppa.h: Fix punctuation in comment.
1523 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1524 implicit space-register addressing. Set space-register bits on opcodes
1525 using implicit space-register addressing. Add various missing pa20
1526 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1527 space-register addressing. Use "fE" instead of "fe" in various
1530 2005-07-18 Jan Beulich <jbeulich@novell.com>
1532 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1534 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1536 * i386.h (i386_optab): Support Intel VMX Instructions.
1538 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1540 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1542 2005-07-05 Jan Beulich <jbeulich@novell.com>
1544 * i386.h (i386_optab): Add new insns.
1546 2005-07-01 Nick Clifton <nickc@redhat.com>
1548 * sparc.h: Add typedefs to structure declarations.
1550 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1553 * i386.h (i386_optab): Update comments for 64bit addressing on
1554 mov. Allow 64bit addressing for mov and movq.
1556 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1558 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1559 respectively, in various floating-point load and store patterns.
1561 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1563 * hppa.h (FLAG_STRICT): Correct comment.
1564 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1565 PA 2.0 mneumonics when equivalent. Entries with cache control
1566 completers now require PA 1.1. Adjust whitespace.
1568 2005-05-19 Anton Blanchard <anton@samba.org>
1570 * ppc.h (PPC_OPCODE_POWER5): Define.
1572 2005-05-10 Nick Clifton <nickc@redhat.com>
1574 * Update the address and phone number of the FSF organization in
1575 the GPL notices in the following files:
1576 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1577 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1578 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1579 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1580 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1581 tic54x.h, tic80.h, v850.h, vax.h
1583 2005-05-09 Jan Beulich <jbeulich@novell.com>
1585 * i386.h (i386_optab): Add ht and hnt.
1587 2005-04-18 Mark Kettenis <kettenis@gnu.org>
1589 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1590 Add xcrypt-ctr. Provide aliases without hyphens.
1592 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1594 Moved from ../ChangeLog
1596 2005-04-12 Paul Brook <paul@codesourcery.com>
1597 * m88k.h: Rename psr macros to avoid conflicts.
1599 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1600 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1601 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1602 and ARM_ARCH_V6ZKT2.
1604 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1605 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1606 Remove redundant instruction types.
1607 (struct argument): X_op - new field.
1608 (struct cst4_entry): Remove.
1609 (no_op_insn): Declare.
1611 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1612 * crx.h (enum argtype): Rename types, remove unused types.
1614 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1615 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1616 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1617 (enum operand_type): Rearrange operands, edit comments.
1618 replace us<N> with ui<N> for unsigned immediate.
1619 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1620 displacements (respectively).
1621 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1622 (instruction type): Add NO_TYPE_INS.
1623 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1624 (operand_entry): New field - 'flags'.
1625 (operand flags): New.
1627 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1628 * crx.h (operand_type): Remove redundant types i3, i4,
1630 Add new unsigned immediate types us3, us4, us5, us16.
1632 2005-04-12 Mark Kettenis <kettenis@gnu.org>
1634 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1635 adjust them accordingly.
1637 2005-04-01 Jan Beulich <jbeulich@novell.com>
1639 * i386.h (i386_optab): Add rdtscp.
1641 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1643 * i386.h (i386_optab): Don't allow the `l' suffix for moving
1644 between memory and segment register. Allow movq for moving between
1645 general-purpose register and segment register.
1647 2005-02-09 Jan Beulich <jbeulich@novell.com>
1650 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1651 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1654 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1656 * m68k.h (m68008, m68ec030, m68882): Remove.
1658 (cpu_m68k, cpu_cf): New.
1659 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1660 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1662 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
1664 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1665 * cgen.h (enum cgen_parse_operand_type): Add
1666 CGEN_PARSE_OPERAND_SYMBOLIC.
1668 2005-01-21 Fred Fish <fnf@specifixinc.com>
1670 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1671 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1672 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1674 2005-01-19 Fred Fish <fnf@specifixinc.com>
1676 * mips.h (struct mips_opcode): Add new pinfo2 member.
1677 (INSN_ALIAS): New define for opcode table entries that are
1678 specific instances of another entry, such as 'move' for an 'or'
1679 with a zero operand.
1680 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1681 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1683 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1685 * mips.h (CPU_RM9000): Define.
1686 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1688 2004-11-25 Jan Beulich <jbeulich@novell.com>
1690 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1691 to/from test registers are illegal in 64-bit mode. Add missing
1692 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1693 (previously one had to explicitly encode a rex64 prefix). Re-enable
1694 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1695 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1697 2004-11-23 Jan Beulich <jbeulich@novell.com>
1699 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1700 available only with SSE2. Change the MMX additions introduced by SSE
1701 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1702 instructions by their now designated identifier (since combining i686
1703 and 3DNow! does not really imply 3DNow!A).
1705 2004-11-19 Alan Modra <amodra@bigpond.net.au>
1707 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1708 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1710 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1711 Vineet Sharma <vineets@noida.hcltech.com>
1713 * maxq.h: New file: Disassembly information for the maxq port.
1715 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1717 * i386.h (i386_optab): Put back "movzb".
1719 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
1721 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1722 comments. Remove member cris_ver_sim. Add members
1723 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1724 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1725 (struct cris_support_reg, struct cris_cond15): New types.
1726 (cris_conds15): Declare.
1727 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1728 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1729 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1730 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1731 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1732 SIZE_FIELD_UNSIGNED.
1734 2004-11-04 Jan Beulich <jbeulich@novell.com>
1736 * i386.h (sldx_Suf): Remove.
1737 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1738 (q_FP): Define, implying no REX64.
1739 (x_FP, sl_FP): Imply FloatMF.
1740 (i386_optab): Split reg and mem forms of moving from segment registers
1741 so that the memory forms can ignore the 16-/32-bit operand size
1742 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1743 all non-floating-point instructions. Unite 32- and 64-bit forms of
1744 movsx, movzx, and movd. Adjust floating point operations for the above
1745 changes to the *FP macros. Add DefaultSize to floating point control
1746 insns operating on larger memory ranges. Remove left over comments
1747 hinting at certain insns being Intel-syntax ones where the ones
1748 actually meant are already gone.
1750 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1752 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1755 2004-09-30 Paul Brook <paul@codesourcery.com>
1757 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1758 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1760 2004-09-11 Theodore A. Roth <troth@openavr.org>
1762 * avr.h: Add support for
1763 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1765 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1767 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1769 2004-08-24 Dmitry Diky <diwil@spec.ru>
1771 * msp430.h (msp430_opc): Add new instructions.
1772 (msp430_rcodes): Declare new instructions.
1773 (msp430_hcodes): Likewise..
1775 2004-08-13 Nick Clifton <nickc@redhat.com>
1778 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1781 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1783 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1785 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1787 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1789 2004-07-21 Jan Beulich <jbeulich@novell.com>
1791 * i386.h: Adjust instruction descriptions to better match the
1794 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
1796 * arm.h: Remove all old content. Replace with architecture defines
1797 from gas/config/tc-arm.c.
1799 2004-07-09 Andreas Schwab <schwab@suse.de>
1801 * m68k.h: Fix comment.
1803 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1807 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1809 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1811 2004-05-24 Peter Barada <peter@the-baradas.com>
1813 * m68k.h: Add 'size' to m68k_opcode.
1815 2004-05-05 Peter Barada <peter@the-baradas.com>
1817 * m68k.h: Switch from ColdFire chip name to core variant.
1819 2004-04-22 Peter Barada <peter@the-baradas.com>
1821 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1822 descriptions for new EMAC cases.
1823 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1824 handle Motorola MAC syntax.
1825 Allow disassembly of ColdFire V4e object files.
1827 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1829 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1831 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1833 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1835 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1837 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1839 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1841 * i386.h (i386_optab): Added xstore/xcrypt insns.
1843 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1845 * h8300.h (32bit ldc/stc): Add relaxing support.
1847 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1849 * h8300.h (BITOP): Pass MEMRELAX flag.
1851 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1853 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1856 For older changes see ChangeLog-9103
1858 Copyright (C) 2004-2012 Free Software Foundation, Inc.
1860 Copying and distribution of this file, with or without modification,
1861 are permitted in any medium without royalty provided the copyright
1862 notice and this notice are preserved.
1868 version-control: never