1 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
3 * arm.h (ARM_AEXT_ADIV): New define.
4 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
6 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
8 * arm.h (ARM_EXT_OS): New define.
9 (ARM_AEXT_V6SM): Likewise.
10 (ARM_ARCH_V6SM): Likewise.
12 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
14 * arm.h (ARM_EXT_MP): Add.
15 (ARM_ARCH_V7A_MP): Likewise.
17 2010-09-22 Mike Frysinger <vapier@gentoo.org>
19 * bfin.h: Declare pseudoChr structs/defines.
21 2010-09-21 Mike Frysinger <vapier@gentoo.org>
23 * bfin.h: Strip trailing whitespace.
25 2010-07-29 DJ Delorie <dj@redhat.com>
27 * rx.h (RX_Operand_Type): Add TwoReg.
28 (RX_Opcode_ID): Remove ediv and ediv2.
30 2010-07-27 DJ Delorie <dj@redhat.com>
32 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
34 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
35 Ina Pandit <ina.pandit@kpitcummins.com>
37 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
38 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
40 Remove PROCESSOR_V850EA support.
41 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
42 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
43 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
44 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
45 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
47 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
49 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
52 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
54 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
55 (MIPS16_INSN_BRANCH): Rename to...
56 (MIPS16_INSN_COND_BRANCH): ... this.
58 2010-07-03 Alan Modra <amodra@gmail.com>
60 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
61 Renumber other PPC_OPCODE defines.
63 2010-07-03 Alan Modra <amodra@gmail.com>
65 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
67 2010-06-29 Alan Modra <amodra@gmail.com>
69 * maxq.h: Delete file.
71 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
73 * ppc.h (PPC_OPCODE_E500): Define.
75 2010-05-26 Catherine Moore <clm@codesourcery.com>
77 * opcode/mips.h (INSN_MIPS16): Remove.
79 2010-04-21 Joseph Myers <joseph@codesourcery.com>
81 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
83 2010-04-15 Nick Clifton <nickc@redhat.com>
85 * alpha.h: Update copyright notice to use GPLv3.
105 * m68hc11.h: Likewise.
111 * mn10200.h: Likewise.
112 * mn10300.h: Likewise.
113 * msp430.h: Likewise.
124 * score-datadep.h: Likewise.
125 * score-inst.h: Likewise.
127 * spu-insns.h: Likewise.
131 * tic54x.h: Likewise.
136 2010-03-25 Joseph Myers <joseph@codesourcery.com>
138 * tic6x-control-registers.h, tic6x-insn-formats.h,
139 tic6x-opcode-table.h, tic6x.h: New.
141 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
143 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
145 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
147 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
149 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
151 * ia64.h (ia64_find_opcode): Remove argument name.
152 (ia64_find_next_opcode): Likewise.
153 (ia64_dis_opcode): Likewise.
154 (ia64_free_opcode): Likewise.
155 (ia64_find_dependency): Likewise.
157 2009-11-22 Doug Evans <dje@sebabeach.org>
159 * cgen.h: Include bfd_stdint.h.
160 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
162 2009-11-18 Paul Brook <paul@codesourcery.com>
164 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
166 2009-11-17 Paul Brook <paul@codesourcery.com>
167 Daniel Jacobowitz <dan@codesourcery.com>
169 * arm.h (ARM_EXT_V6_DSP): Define.
170 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
171 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
173 2009-11-04 DJ Delorie <dj@redhat.com>
175 * rx.h (rx_decode_opcode) (mvtipl): Add.
176 (mvtcp, mvfcp, opecp): Remove.
178 2009-11-02 Paul Brook <paul@codesourcery.com>
180 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
181 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
182 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
183 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
184 FPU_ARCH_NEON_VFP_V4): Define.
186 2009-10-23 Doug Evans <dje@sebabeach.org>
188 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
189 * cgen.h: Update. Improve multi-inclusion macro name.
191 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
193 * ppc.h (PPC_OPCODE_476): Define.
195 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
197 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
199 2009-09-29 DJ Delorie <dj@redhat.com>
203 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
205 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
207 2009-09-21 Ben Elliston <bje@au.ibm.com>
209 * ppc.h (PPC_OPCODE_PPCA2): New.
211 2009-09-05 Martin Thuresson <martin@mtme.org>
213 * ia64.h (struct ia64_operand): Renamed member class to op_class.
215 2009-08-29 Martin Thuresson <martin@mtme.org>
217 * tic30.h (template): Rename type template to
218 insn_template. Updated code to use new name.
219 * tic54x.h (template): Rename type template to
222 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
224 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
226 2009-06-11 Anthony Green <green@moxielogic.com>
228 * moxie.h (MOXIE_F3_PCREL): Define.
229 (moxie_form3_opc_info): Grow.
231 2009-06-06 Anthony Green <green@moxielogic.com>
233 * moxie.h (MOXIE_F1_M): Define.
235 2009-04-15 Anthony Green <green@moxielogic.com>
239 2009-04-06 DJ Delorie <dj@redhat.com>
241 * h8300.h: Add relaxation attributes to MOVA opcodes.
243 2009-03-10 Alan Modra <amodra@bigpond.net.au>
245 * ppc.h (ppc_parse_cpu): Declare.
247 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
249 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
250 and _IMM11 for mbitclr and mbitset.
251 * score-datadep.h: Update dependency information.
253 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
255 * ppc.h (PPC_OPCODE_POWER7): New.
257 2009-02-06 Doug Evans <dje@google.com>
259 * i386.h: Add comment regarding sse* insns and prefixes.
261 2009-02-03 Sandip Matte <sandip@rmicorp.com>
263 * mips.h (INSN_XLR): Define.
264 (INSN_CHIP_MASK): Update.
266 (OPCODE_IS_MEMBER): Update.
267 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
269 2009-01-28 Doug Evans <dje@google.com>
271 * opcode/i386.h: Add multiple inclusion protection.
272 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
273 (EDI_REG_NUM): New macros.
274 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
275 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
276 (REX_PREFIX_P): New macro.
278 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
280 * ppc.h (struct powerpc_opcode): New field "deprecated".
281 (PPC_OPCODE_NOPOWER4): Delete.
283 2008-11-28 Joshua Kinard <kumba@gentoo.org>
285 * mips.h: Define CPU_R14000, CPU_R16000.
286 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
288 2008-11-18 Catherine Moore <clm@codesourcery.com>
290 * arm.h (FPU_NEON_FP16): New.
291 (FPU_ARCH_NEON_FP16): New.
293 2008-11-06 Chao-ying Fu <fu@mips.com>
295 * mips.h: Doucument '1' for 5-bit sync type.
297 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
299 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
302 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
304 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
306 2008-07-30 Michael J. Eager <eager@eagercon.com>
308 * ppc.h (PPC_OPCODE_405): Define.
309 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
311 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
313 * ppc.h (ppc_cpu_t): New typedef.
314 (struct powerpc_opcode <flags>): Use it.
315 (struct powerpc_operand <insert, extract>): Likewise.
316 (struct powerpc_macro <flags>): Likewise.
318 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
320 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
321 Update comment before MIPS16 field descriptors to mention MIPS16.
322 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
324 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
325 New bit masks and shift counts for cins and exts.
327 * mips.h: Document new field descriptors +Q.
328 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
330 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
332 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
333 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
335 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
337 * ppc.h: (PPC_OPCODE_E500MC): New.
339 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
341 * i386.h (MAX_OPERANDS): Set to 5.
342 (MAX_MNEM_SIZE): Changed to 20.
344 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
346 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
348 2008-03-09 Paul Brook <paul@codesourcery.com>
350 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
352 2008-03-04 Paul Brook <paul@codesourcery.com>
354 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
355 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
356 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
358 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
359 Nick Clifton <nickc@redhat.com>
362 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
363 with a 32-bit displacement but without the top bit of the 4th byte
366 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
368 * cr16.h (cr16_num_optab): Declared.
370 2008-02-14 Hakan Ardo <hakan@debian.org>
373 * avr.h (AVR_ISA_2xxe): Define.
375 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
377 * mips.h: Update copyright.
378 (INSN_CHIP_MASK): New macro.
379 (INSN_OCTEON): New macro.
380 (CPU_OCTEON): New macro.
381 (OPCODE_IS_MEMBER): Handle Octeon instructions.
383 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
385 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
387 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
389 * avr.h (AVR_ISA_USB162): Add new opcode set.
390 (AVR_ISA_AVR3): Likewise.
392 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
394 * mips.h (INSN_LOONGSON_2E): New.
395 (INSN_LOONGSON_2F): New.
396 (CPU_LOONGSON_2E): New.
397 (CPU_LOONGSON_2F): New.
398 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
400 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
402 * mips.h (INSN_ISA*): Redefine certain values as an
403 enumeration. Update comments.
404 (mips_isa_table): New.
405 (ISA_MIPS*): Redefine to match enumeration.
406 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
409 2007-08-08 Ben Elliston <bje@au.ibm.com>
411 * ppc.h (PPC_OPCODE_PPCPS): New.
413 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
415 * m68k.h: Document j K & E.
417 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
419 * cr16.h: New file for CR16 target.
421 2007-05-02 Alan Modra <amodra@bigpond.net.au>
423 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
425 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
427 * m68k.h (mcfisa_c): New.
428 (mcfusp, mcf_mask): Adjust.
430 2007-04-20 Alan Modra <amodra@bigpond.net.au>
432 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
433 (num_powerpc_operands): Declare.
434 (PPC_OPERAND_SIGNED et al): Redefine as hex.
435 (PPC_OPERAND_PLUS1): Define.
437 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
439 * i386.h (REX_MODE64): Renamed to ...
441 (REX_EXTX): Renamed to ...
443 (REX_EXTY): Renamed to ...
445 (REX_EXTZ): Renamed to ...
448 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
450 * i386.h: Add entries from config/tc-i386.h and move tables
451 to opcodes/i386-opc.h.
453 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
455 * i386.h (FloatDR): Removed.
456 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
458 2007-03-01 Alan Modra <amodra@bigpond.net.au>
460 * spu-insns.h: Add soma double-float insns.
462 2007-02-20 Thiemo Seufer <ths@mips.com>
463 Chao-Ying Fu <fu@mips.com>
465 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
466 (INSN_DSPR2): Add flag for DSP R2 instructions.
467 (M_BALIGN): New macro.
469 2007-02-14 Alan Modra <amodra@bigpond.net.au>
471 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
472 and Seg3ShortFrom with Shortform.
474 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
477 * i386.h (i386_optab): Put the real "test" before the pseudo
480 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
482 * m68k.h (m68010up): OR fido_a.
484 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
486 * m68k.h (fido_a): New.
488 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
490 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
491 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
494 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
496 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
498 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
500 * score-inst.h (enum score_insn_type): Add Insn_internal.
502 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
503 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
504 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
505 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
506 Alan Modra <amodra@bigpond.net.au>
508 * spu-insns.h: New file.
511 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
513 * ppc.h (PPC_OPCODE_CELL): Define.
515 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
517 * i386.h : Modify opcode to support for the change in POPCNT opcode
518 in amdfam10 architecture.
520 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
522 * i386.h: Replace CpuMNI with CpuSSSE3.
524 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
525 Joseph Myers <joseph@codesourcery.com>
526 Ian Lance Taylor <ian@wasabisystems.com>
527 Ben Elliston <bje@wasabisystems.com>
529 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
531 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
533 * score-datadep.h: New file.
534 * score-inst.h: New file.
536 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
538 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
539 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
542 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
543 Michael Meissner <michael.meissner@amd.com>
545 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
547 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
549 * i386.h (i386_optab): Add "nop" with memory reference.
551 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
553 * i386.h (i386_optab): Update comment for 64bit NOP.
555 2006-06-06 Ben Elliston <bje@au.ibm.com>
556 Anton Blanchard <anton@samba.org>
558 * ppc.h (PPC_OPCODE_POWER6): Define.
561 2006-06-05 Thiemo Seufer <ths@mips.com>
563 * mips.h: Improve description of MT flags.
565 2006-05-25 Richard Sandiford <richard@codesourcery.com>
567 * m68k.h (mcf_mask): Define.
569 2006-05-05 Thiemo Seufer <ths@mips.com>
570 David Ung <davidu@mips.com>
572 * mips.h (enum): Add macro M_CACHE_AB.
574 2006-05-04 Thiemo Seufer <ths@mips.com>
575 Nigel Stephens <nigel@mips.com>
576 David Ung <davidu@mips.com>
578 * mips.h: Add INSN_SMARTMIPS define.
580 2006-04-30 Thiemo Seufer <ths@mips.com>
581 David Ung <davidu@mips.com>
583 * mips.h: Defines udi bits and masks. Add description of
584 characters which may appear in the args field of udi
587 2006-04-26 Thiemo Seufer <ths@networkno.de>
589 * mips.h: Improve comments describing the bitfield instruction
592 2006-04-26 Julian Brown <julian@codesourcery.com>
594 * arm.h (FPU_VFP_EXT_V3): Define constant.
595 (FPU_NEON_EXT_V1): Likewise.
596 (FPU_VFP_HARD): Update.
597 (FPU_VFP_V3): Define macro.
598 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
600 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
602 * avr.h (AVR_ISA_PWMx): New.
604 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
606 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
607 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
608 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
609 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
610 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
612 2006-03-10 Paul Brook <paul@codesourcery.com>
614 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
616 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
618 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
619 first. Correct mask of bb "B" opcode.
621 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
623 * i386.h (i386_optab): Support Intel Merom New Instructions.
625 2006-02-24 Paul Brook <paul@codesourcery.com>
627 * arm.h: Add V7 feature bits.
629 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
631 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
633 2006-01-31 Paul Brook <paul@codesourcery.com>
634 Richard Earnshaw <rearnsha@arm.com>
636 * arm.h: Use ARM_CPU_FEATURE.
637 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
638 (arm_feature_set): Change to a structure.
639 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
640 ARM_FEATURE): New macros.
642 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
644 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
645 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
646 (ADD_PC_INCR_OPCODE): Don't define.
648 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
651 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
653 2005-11-14 David Ung <davidu@mips.com>
655 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
656 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
657 save/restore encoding of the args field.
659 2005-10-28 Dave Brolley <brolley@redhat.com>
661 Contribute the following changes:
662 2005-02-16 Dave Brolley <brolley@redhat.com>
664 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
665 cgen_isa_mask_* to cgen_bitset_*.
668 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
670 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
671 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
672 (CGEN_CPU_TABLE): Make isas a ponter.
674 2003-09-29 Dave Brolley <brolley@redhat.com>
676 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
677 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
678 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
680 2002-12-13 Dave Brolley <brolley@redhat.com>
682 * cgen.h (symcat.h): #include it.
683 (cgen-bitset.h): #include it.
684 (CGEN_ATTR_VALUE_TYPE): Now a union.
685 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
686 (CGEN_ATTR_ENTRY): 'value' now unsigned.
687 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
688 * cgen-bitset.h: New file.
690 2005-09-30 Catherine Moore <clm@cm00re.com>
694 2005-10-24 Jan Beulich <jbeulich@novell.com>
696 * ia64.h (enum ia64_opnd): Move memory operand out of set of
699 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
701 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
702 Add FLAG_STRICT to pa10 ftest opcode.
704 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
706 * hppa.h (pa_opcodes): Remove lha entries.
708 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
710 * hppa.h (FLAG_STRICT): Revise comment.
711 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
712 before corresponding pa11 opcodes. Add strict pa10 register-immediate
715 2005-09-30 Catherine Moore <clm@cm00re.com>
719 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
721 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
723 2005-09-06 Chao-ying Fu <fu@mips.com>
725 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
726 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
728 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
729 (INSN_ASE_MASK): Update to include INSN_MT.
730 (INSN_MT): New define for MT ASE.
732 2005-08-25 Chao-ying Fu <fu@mips.com>
734 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
735 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
736 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
737 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
738 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
739 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
741 (INSN_DSP): New define for DSP ASE.
743 2005-08-18 Alan Modra <amodra@bigpond.net.au>
747 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
749 * ppc.h (PPC_OPCODE_E300): Define.
751 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
753 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
755 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
758 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
761 2005-07-27 Jan Beulich <jbeulich@novell.com>
763 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
764 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
765 Add movq-s as 64-bit variants of movd-s.
767 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
769 * hppa.h: Fix punctuation in comment.
771 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
772 implicit space-register addressing. Set space-register bits on opcodes
773 using implicit space-register addressing. Add various missing pa20
774 long-immediate opcodes. Remove various opcodes using implicit 3-bit
775 space-register addressing. Use "fE" instead of "fe" in various
778 2005-07-18 Jan Beulich <jbeulich@novell.com>
780 * i386.h (i386_optab): Operands of aam and aad are unsigned.
782 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
784 * i386.h (i386_optab): Support Intel VMX Instructions.
786 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
788 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
790 2005-07-05 Jan Beulich <jbeulich@novell.com>
792 * i386.h (i386_optab): Add new insns.
794 2005-07-01 Nick Clifton <nickc@redhat.com>
796 * sparc.h: Add typedefs to structure declarations.
798 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
801 * i386.h (i386_optab): Update comments for 64bit addressing on
802 mov. Allow 64bit addressing for mov and movq.
804 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
806 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
807 respectively, in various floating-point load and store patterns.
809 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
811 * hppa.h (FLAG_STRICT): Correct comment.
812 (pa_opcodes): Update load and store entries to allow both PA 1.X and
813 PA 2.0 mneumonics when equivalent. Entries with cache control
814 completers now require PA 1.1. Adjust whitespace.
816 2005-05-19 Anton Blanchard <anton@samba.org>
818 * ppc.h (PPC_OPCODE_POWER5): Define.
820 2005-05-10 Nick Clifton <nickc@redhat.com>
822 * Update the address and phone number of the FSF organization in
823 the GPL notices in the following files:
824 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
825 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
826 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
827 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
828 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
829 tic54x.h, tic80.h, v850.h, vax.h
831 2005-05-09 Jan Beulich <jbeulich@novell.com>
833 * i386.h (i386_optab): Add ht and hnt.
835 2005-04-18 Mark Kettenis <kettenis@gnu.org>
837 * i386.h: Insert hyphens into selected VIA PadLock extensions.
838 Add xcrypt-ctr. Provide aliases without hyphens.
840 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
842 Moved from ../ChangeLog
844 2005-04-12 Paul Brook <paul@codesourcery.com>
845 * m88k.h: Rename psr macros to avoid conflicts.
847 2005-03-12 Zack Weinberg <zack@codesourcery.com>
848 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
849 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
852 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
853 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
854 Remove redundant instruction types.
855 (struct argument): X_op - new field.
856 (struct cst4_entry): Remove.
857 (no_op_insn): Declare.
859 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
860 * crx.h (enum argtype): Rename types, remove unused types.
862 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
863 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
864 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
865 (enum operand_type): Rearrange operands, edit comments.
866 replace us<N> with ui<N> for unsigned immediate.
867 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
868 displacements (respectively).
869 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
870 (instruction type): Add NO_TYPE_INS.
871 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
872 (operand_entry): New field - 'flags'.
873 (operand flags): New.
875 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
876 * crx.h (operand_type): Remove redundant types i3, i4,
878 Add new unsigned immediate types us3, us4, us5, us16.
880 2005-04-12 Mark Kettenis <kettenis@gnu.org>
882 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
883 adjust them accordingly.
885 2005-04-01 Jan Beulich <jbeulich@novell.com>
887 * i386.h (i386_optab): Add rdtscp.
889 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
891 * i386.h (i386_optab): Don't allow the `l' suffix for moving
892 between memory and segment register. Allow movq for moving between
893 general-purpose register and segment register.
895 2005-02-09 Jan Beulich <jbeulich@novell.com>
898 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
899 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
902 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
904 * m68k.h (m68008, m68ec030, m68882): Remove.
906 (cpu_m68k, cpu_cf): New.
907 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
908 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
910 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
912 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
913 * cgen.h (enum cgen_parse_operand_type): Add
914 CGEN_PARSE_OPERAND_SYMBOLIC.
916 2005-01-21 Fred Fish <fnf@specifixinc.com>
918 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
919 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
920 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
922 2005-01-19 Fred Fish <fnf@specifixinc.com>
924 * mips.h (struct mips_opcode): Add new pinfo2 member.
925 (INSN_ALIAS): New define for opcode table entries that are
926 specific instances of another entry, such as 'move' for an 'or'
928 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
929 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
931 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
933 * mips.h (CPU_RM9000): Define.
934 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
936 2004-11-25 Jan Beulich <jbeulich@novell.com>
938 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
939 to/from test registers are illegal in 64-bit mode. Add missing
940 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
941 (previously one had to explicitly encode a rex64 prefix). Re-enable
942 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
943 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
945 2004-11-23 Jan Beulich <jbeulich@novell.com>
947 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
948 available only with SSE2. Change the MMX additions introduced by SSE
949 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
950 instructions by their now designated identifier (since combining i686
951 and 3DNow! does not really imply 3DNow!A).
953 2004-11-19 Alan Modra <amodra@bigpond.net.au>
955 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
956 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
958 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
959 Vineet Sharma <vineets@noida.hcltech.com>
961 * maxq.h: New file: Disassembly information for the maxq port.
963 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
965 * i386.h (i386_optab): Put back "movzb".
967 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
969 * cris.h (enum cris_insn_version_usage): Tweak formatting and
970 comments. Remove member cris_ver_sim. Add members
971 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
972 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
973 (struct cris_support_reg, struct cris_cond15): New types.
974 (cris_conds15): Declare.
975 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
976 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
977 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
978 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
979 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
982 2004-11-04 Jan Beulich <jbeulich@novell.com>
984 * i386.h (sldx_Suf): Remove.
985 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
986 (q_FP): Define, implying no REX64.
987 (x_FP, sl_FP): Imply FloatMF.
988 (i386_optab): Split reg and mem forms of moving from segment registers
989 so that the memory forms can ignore the 16-/32-bit operand size
990 distinction. Adjust a few others for Intel mode. Remove *FP uses from
991 all non-floating-point instructions. Unite 32- and 64-bit forms of
992 movsx, movzx, and movd. Adjust floating point operations for the above
993 changes to the *FP macros. Add DefaultSize to floating point control
994 insns operating on larger memory ranges. Remove left over comments
995 hinting at certain insns being Intel-syntax ones where the ones
996 actually meant are already gone.
998 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1000 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1003 2004-09-30 Paul Brook <paul@codesourcery.com>
1005 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1006 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1008 2004-09-11 Theodore A. Roth <troth@openavr.org>
1010 * avr.h: Add support for
1011 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1013 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1015 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1017 2004-08-24 Dmitry Diky <diwil@spec.ru>
1019 * msp430.h (msp430_opc): Add new instructions.
1020 (msp430_rcodes): Declare new instructions.
1021 (msp430_hcodes): Likewise..
1023 2004-08-13 Nick Clifton <nickc@redhat.com>
1026 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1029 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1031 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1033 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1035 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1037 2004-07-21 Jan Beulich <jbeulich@novell.com>
1039 * i386.h: Adjust instruction descriptions to better match the
1042 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
1044 * arm.h: Remove all old content. Replace with architecture defines
1045 from gas/config/tc-arm.c.
1047 2004-07-09 Andreas Schwab <schwab@suse.de>
1049 * m68k.h: Fix comment.
1051 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1055 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1057 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1059 2004-05-24 Peter Barada <peter@the-baradas.com>
1061 * m68k.h: Add 'size' to m68k_opcode.
1063 2004-05-05 Peter Barada <peter@the-baradas.com>
1065 * m68k.h: Switch from ColdFire chip name to core variant.
1067 2004-04-22 Peter Barada <peter@the-baradas.com>
1069 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1070 descriptions for new EMAC cases.
1071 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1072 handle Motorola MAC syntax.
1073 Allow disassembly of ColdFire V4e object files.
1075 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1077 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1079 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1081 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1083 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1085 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1087 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1089 * i386.h (i386_optab): Added xstore/xcrypt insns.
1091 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1093 * h8300.h (32bit ldc/stc): Add relaxing support.
1095 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1097 * h8300.h (BITOP): Pass MEMRELAX flag.
1099 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1101 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1104 For older changes see ChangeLog-9103
1110 version-control: never