1 2012-04-27 David S. Miller <davem@davemloft.net>
3 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
4 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
5 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
6 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
7 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
8 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
9 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
10 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
11 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
12 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
13 HWCAP_CBCOND, HWCAP_CRC32): New defines.
15 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
17 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
19 2012-02-27 Alan Modra <amodra@gmail.com>
21 * crx.h (cst4_map): Update declaration.
23 2012-02-25 Walter Lee <walt@tilera.com>
25 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
27 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
28 TILEPRO_OPC_LW_TLS_SN.
30 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
32 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
33 (XRELEASE_PREFIX_OPCODE): Likewise.
35 2011-12-08 Andrew Pinski <apinski@cavium.com>
36 Adam Nemet <anemet@caviumnetworks.com>
38 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
39 (INSN_OCTEON2): New macro.
40 (CPU_OCTEON2): New macro.
41 (OPCODE_IS_MEMBER): Add Octeon2.
43 2011-11-29 Andrew Pinski <apinski@cavium.com>
45 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
46 (INSN_OCTEONP): New macro.
47 (CPU_OCTEONP): New macro.
48 (OPCODE_IS_MEMBER): Add Octeon+.
49 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
51 2011-11-01 DJ Delorie <dj@redhat.com>
55 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
57 * mips.h: Fix a typo in description.
59 2011-09-21 David S. Miller <davem@davemloft.net>
61 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
62 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
63 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
64 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
66 2011-08-09 Chao-ying Fu <fu@mips.com>
67 Maciej W. Rozycki <macro@codesourcery.com>
69 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
70 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
71 (INSN_ASE_MASK): Add the MCU bit.
72 (INSN_MCU): New macro.
73 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
74 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
76 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
78 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
79 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
80 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
81 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
82 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
83 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
84 (INSN2_READ_GPR_MMN): Likewise.
85 (INSN2_READ_FPR_D): Change the bit used.
86 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
87 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
88 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
89 (INSN2_COND_BRANCH): Likewise.
90 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
91 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
92 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
93 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
94 (INSN2_MOD_GPR_MN): Likewise.
96 2011-08-05 David S. Miller <davem@davemloft.net>
98 * sparc.h: Document new format codes '4', '5', and '('.
99 (OPF_LOW4, RS3): New macros.
101 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
103 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
104 order of flags documented.
106 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
108 * mips.h: Clarify the description of microMIPS instruction
110 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
112 2011-07-24 Chao-ying Fu <fu@mips.com>
113 Maciej W. Rozycki <macro@codesourcery.com>
115 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
116 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
117 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
118 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
119 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
120 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
121 (OP_MASK_RS3, OP_SH_RS3): Likewise.
122 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
123 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
124 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
125 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
126 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
127 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
128 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
129 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
130 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
131 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
132 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
133 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
134 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
135 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
136 (INSN_WRITE_GPR_S): New macro.
137 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
138 (INSN2_READ_FPR_D): Likewise.
139 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
140 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
141 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
142 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
143 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
144 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
145 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
146 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
147 (CPU_MICROMIPS): New macro.
148 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
149 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
150 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
151 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
152 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
153 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
154 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
155 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
156 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
157 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
158 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
159 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
160 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
161 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
162 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
163 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
164 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
165 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
166 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
167 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
168 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
169 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
170 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
171 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
172 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
173 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
174 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
175 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
176 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
177 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
178 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
179 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
180 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
181 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
182 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
183 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
184 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
185 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
186 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
187 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
188 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
189 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
190 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
191 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
192 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
193 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
194 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
195 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
196 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
197 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
198 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
199 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
200 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
201 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
202 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
203 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
204 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
205 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
206 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
207 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
208 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
209 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
210 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
211 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
212 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
213 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
214 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
215 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
216 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
217 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
218 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
219 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
220 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
221 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
222 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
223 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
224 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
225 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
226 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
227 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
228 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
229 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
230 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
231 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
232 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
233 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
234 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
235 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
236 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
237 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
238 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
239 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
240 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
241 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
242 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
243 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
244 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
245 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
246 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
247 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
248 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
249 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
250 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
251 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
252 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
253 (micromips_opcodes): New declaration.
254 (bfd_micromips_num_opcodes): Likewise.
256 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
258 * mips.h (INSN_TRAP): Rename to...
259 (INSN_NO_DELAY_SLOT): ... this.
260 (INSN_SYNC): Remove macro.
262 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
264 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
265 a duplicate of AVR_ISA_SPM.
267 2011-07-01 Nick Clifton <nickc@redhat.com>
269 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
271 2011-06-18 Robin Getz <robin.getz@analog.com>
273 * bfin.h (is_macmod_signed): New func
275 2011-06-18 Mike Frysinger <vapier@gentoo.org>
277 * bfin.h (is_macmod_pmove): Add missing space before func args.
278 (is_macmod_hmove): Likewise.
280 2011-06-13 Walter Lee <walt@tilera.com>
282 * tilegx.h: New file.
283 * tilepro.h: New file.
285 2011-05-31 Paul Brook <paul@codesourcery.com>
287 * arm.h (ARM_ARCH_V7R_IDIV): Define.
289 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
291 * s390.h: Replace S390_OPERAND_REG_EVEN with
292 S390_OPERAND_REG_PAIR.
294 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
296 * s390.h: Add S390_OPCODE_REG_EVEN flag.
298 2011-04-18 Julian Brown <julian@codesourcery.com>
300 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
302 2011-04-11 Dan McDonald <dan@wellkeeper.com>
305 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
307 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
309 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
310 New instruction set flags.
311 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
313 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
315 * mips.h (M_PREF_AB): New enum value.
317 2011-02-12 Mike Frysinger <vapier@gentoo.org>
319 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
321 (is_macmod_pmove, is_macmod_hmove): New functions.
323 2011-02-11 Mike Frysinger <vapier@gentoo.org>
325 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
327 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
329 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
330 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
332 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
335 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
338 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
341 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
343 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
345 * mips.h: Update commentary after last commit.
347 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
349 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
350 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
351 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
353 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
355 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
357 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
359 * mips.h: Fix previous commit.
361 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
363 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
364 (INSN_LOONGSON_3A): Clear bit 31.
366 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
369 * arm.h (ARM_AEXT_V6M_ONLY): New define.
370 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
371 (ARM_ARCH_V6M_ONLY): New define.
373 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
375 * mips.h (INSN_LOONGSON_3A): Defined.
376 (CPU_LOONGSON_3A): Defined.
377 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
379 2010-10-09 Matt Rice <ratmice@gmail.com>
381 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
382 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
384 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
386 * arm.h (ARM_EXT_VIRT): New define.
387 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
388 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
391 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
393 * arm.h (ARM_AEXT_ADIV): New define.
394 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
396 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
398 * arm.h (ARM_EXT_OS): New define.
399 (ARM_AEXT_V6SM): Likewise.
400 (ARM_ARCH_V6SM): Likewise.
402 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
404 * arm.h (ARM_EXT_MP): Add.
405 (ARM_ARCH_V7A_MP): Likewise.
407 2010-09-22 Mike Frysinger <vapier@gentoo.org>
409 * bfin.h: Declare pseudoChr structs/defines.
411 2010-09-21 Mike Frysinger <vapier@gentoo.org>
413 * bfin.h: Strip trailing whitespace.
415 2010-07-29 DJ Delorie <dj@redhat.com>
417 * rx.h (RX_Operand_Type): Add TwoReg.
418 (RX_Opcode_ID): Remove ediv and ediv2.
420 2010-07-27 DJ Delorie <dj@redhat.com>
422 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
424 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
425 Ina Pandit <ina.pandit@kpitcummins.com>
427 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
428 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
429 PROCESSOR_V850E2_ALL.
430 Remove PROCESSOR_V850EA support.
431 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
432 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
433 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
434 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
435 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
436 V850_OPERAND_PERCENT.
437 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
439 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
442 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
444 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
445 (MIPS16_INSN_BRANCH): Rename to...
446 (MIPS16_INSN_COND_BRANCH): ... this.
448 2010-07-03 Alan Modra <amodra@gmail.com>
450 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
451 Renumber other PPC_OPCODE defines.
453 2010-07-03 Alan Modra <amodra@gmail.com>
455 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
457 2010-06-29 Alan Modra <amodra@gmail.com>
459 * maxq.h: Delete file.
461 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
463 * ppc.h (PPC_OPCODE_E500): Define.
465 2010-05-26 Catherine Moore <clm@codesourcery.com>
467 * opcode/mips.h (INSN_MIPS16): Remove.
469 2010-04-21 Joseph Myers <joseph@codesourcery.com>
471 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
473 2010-04-15 Nick Clifton <nickc@redhat.com>
475 * alpha.h: Update copyright notice to use GPLv3.
481 * convex.h: Likewise.
495 * m68hc11.h: Likewise.
501 * mn10200.h: Likewise.
502 * mn10300.h: Likewise.
503 * msp430.h: Likewise.
514 * score-datadep.h: Likewise.
515 * score-inst.h: Likewise.
517 * spu-insns.h: Likewise.
521 * tic54x.h: Likewise.
526 2010-03-25 Joseph Myers <joseph@codesourcery.com>
528 * tic6x-control-registers.h, tic6x-insn-formats.h,
529 tic6x-opcode-table.h, tic6x.h: New.
531 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
533 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
535 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
537 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
539 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
541 * ia64.h (ia64_find_opcode): Remove argument name.
542 (ia64_find_next_opcode): Likewise.
543 (ia64_dis_opcode): Likewise.
544 (ia64_free_opcode): Likewise.
545 (ia64_find_dependency): Likewise.
547 2009-11-22 Doug Evans <dje@sebabeach.org>
549 * cgen.h: Include bfd_stdint.h.
550 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
552 2009-11-18 Paul Brook <paul@codesourcery.com>
554 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
556 2009-11-17 Paul Brook <paul@codesourcery.com>
557 Daniel Jacobowitz <dan@codesourcery.com>
559 * arm.h (ARM_EXT_V6_DSP): Define.
560 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
561 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
563 2009-11-04 DJ Delorie <dj@redhat.com>
565 * rx.h (rx_decode_opcode) (mvtipl): Add.
566 (mvtcp, mvfcp, opecp): Remove.
568 2009-11-02 Paul Brook <paul@codesourcery.com>
570 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
571 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
572 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
573 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
574 FPU_ARCH_NEON_VFP_V4): Define.
576 2009-10-23 Doug Evans <dje@sebabeach.org>
578 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
579 * cgen.h: Update. Improve multi-inclusion macro name.
581 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
583 * ppc.h (PPC_OPCODE_476): Define.
585 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
587 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
589 2009-09-29 DJ Delorie <dj@redhat.com>
593 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
595 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
597 2009-09-21 Ben Elliston <bje@au.ibm.com>
599 * ppc.h (PPC_OPCODE_PPCA2): New.
601 2009-09-05 Martin Thuresson <martin@mtme.org>
603 * ia64.h (struct ia64_operand): Renamed member class to op_class.
605 2009-08-29 Martin Thuresson <martin@mtme.org>
607 * tic30.h (template): Rename type template to
608 insn_template. Updated code to use new name.
609 * tic54x.h (template): Rename type template to
612 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
614 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
616 2009-06-11 Anthony Green <green@moxielogic.com>
618 * moxie.h (MOXIE_F3_PCREL): Define.
619 (moxie_form3_opc_info): Grow.
621 2009-06-06 Anthony Green <green@moxielogic.com>
623 * moxie.h (MOXIE_F1_M): Define.
625 2009-04-15 Anthony Green <green@moxielogic.com>
629 2009-04-06 DJ Delorie <dj@redhat.com>
631 * h8300.h: Add relaxation attributes to MOVA opcodes.
633 2009-03-10 Alan Modra <amodra@bigpond.net.au>
635 * ppc.h (ppc_parse_cpu): Declare.
637 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
639 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
640 and _IMM11 for mbitclr and mbitset.
641 * score-datadep.h: Update dependency information.
643 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
645 * ppc.h (PPC_OPCODE_POWER7): New.
647 2009-02-06 Doug Evans <dje@google.com>
649 * i386.h: Add comment regarding sse* insns and prefixes.
651 2009-02-03 Sandip Matte <sandip@rmicorp.com>
653 * mips.h (INSN_XLR): Define.
654 (INSN_CHIP_MASK): Update.
656 (OPCODE_IS_MEMBER): Update.
657 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
659 2009-01-28 Doug Evans <dje@google.com>
661 * opcode/i386.h: Add multiple inclusion protection.
662 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
663 (EDI_REG_NUM): New macros.
664 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
665 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
666 (REX_PREFIX_P): New macro.
668 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
670 * ppc.h (struct powerpc_opcode): New field "deprecated".
671 (PPC_OPCODE_NOPOWER4): Delete.
673 2008-11-28 Joshua Kinard <kumba@gentoo.org>
675 * mips.h: Define CPU_R14000, CPU_R16000.
676 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
678 2008-11-18 Catherine Moore <clm@codesourcery.com>
680 * arm.h (FPU_NEON_FP16): New.
681 (FPU_ARCH_NEON_FP16): New.
683 2008-11-06 Chao-ying Fu <fu@mips.com>
685 * mips.h: Doucument '1' for 5-bit sync type.
687 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
689 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
692 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
694 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
696 2008-07-30 Michael J. Eager <eager@eagercon.com>
698 * ppc.h (PPC_OPCODE_405): Define.
699 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
701 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
703 * ppc.h (ppc_cpu_t): New typedef.
704 (struct powerpc_opcode <flags>): Use it.
705 (struct powerpc_operand <insert, extract>): Likewise.
706 (struct powerpc_macro <flags>): Likewise.
708 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
710 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
711 Update comment before MIPS16 field descriptors to mention MIPS16.
712 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
714 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
715 New bit masks and shift counts for cins and exts.
717 * mips.h: Document new field descriptors +Q.
718 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
720 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
722 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
723 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
725 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
727 * ppc.h: (PPC_OPCODE_E500MC): New.
729 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
731 * i386.h (MAX_OPERANDS): Set to 5.
732 (MAX_MNEM_SIZE): Changed to 20.
734 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
736 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
738 2008-03-09 Paul Brook <paul@codesourcery.com>
740 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
742 2008-03-04 Paul Brook <paul@codesourcery.com>
744 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
745 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
746 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
748 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
749 Nick Clifton <nickc@redhat.com>
752 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
753 with a 32-bit displacement but without the top bit of the 4th byte
756 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
758 * cr16.h (cr16_num_optab): Declared.
760 2008-02-14 Hakan Ardo <hakan@debian.org>
763 * avr.h (AVR_ISA_2xxe): Define.
765 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
767 * mips.h: Update copyright.
768 (INSN_CHIP_MASK): New macro.
769 (INSN_OCTEON): New macro.
770 (CPU_OCTEON): New macro.
771 (OPCODE_IS_MEMBER): Handle Octeon instructions.
773 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
775 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
777 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
779 * avr.h (AVR_ISA_USB162): Add new opcode set.
780 (AVR_ISA_AVR3): Likewise.
782 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
784 * mips.h (INSN_LOONGSON_2E): New.
785 (INSN_LOONGSON_2F): New.
786 (CPU_LOONGSON_2E): New.
787 (CPU_LOONGSON_2F): New.
788 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
790 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
792 * mips.h (INSN_ISA*): Redefine certain values as an
793 enumeration. Update comments.
794 (mips_isa_table): New.
795 (ISA_MIPS*): Redefine to match enumeration.
796 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
799 2007-08-08 Ben Elliston <bje@au.ibm.com>
801 * ppc.h (PPC_OPCODE_PPCPS): New.
803 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
805 * m68k.h: Document j K & E.
807 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
809 * cr16.h: New file for CR16 target.
811 2007-05-02 Alan Modra <amodra@bigpond.net.au>
813 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
815 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
817 * m68k.h (mcfisa_c): New.
818 (mcfusp, mcf_mask): Adjust.
820 2007-04-20 Alan Modra <amodra@bigpond.net.au>
822 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
823 (num_powerpc_operands): Declare.
824 (PPC_OPERAND_SIGNED et al): Redefine as hex.
825 (PPC_OPERAND_PLUS1): Define.
827 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
829 * i386.h (REX_MODE64): Renamed to ...
831 (REX_EXTX): Renamed to ...
833 (REX_EXTY): Renamed to ...
835 (REX_EXTZ): Renamed to ...
838 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
840 * i386.h: Add entries from config/tc-i386.h and move tables
841 to opcodes/i386-opc.h.
843 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
845 * i386.h (FloatDR): Removed.
846 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
848 2007-03-01 Alan Modra <amodra@bigpond.net.au>
850 * spu-insns.h: Add soma double-float insns.
852 2007-02-20 Thiemo Seufer <ths@mips.com>
853 Chao-Ying Fu <fu@mips.com>
855 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
856 (INSN_DSPR2): Add flag for DSP R2 instructions.
857 (M_BALIGN): New macro.
859 2007-02-14 Alan Modra <amodra@bigpond.net.au>
861 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
862 and Seg3ShortFrom with Shortform.
864 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
867 * i386.h (i386_optab): Put the real "test" before the pseudo
870 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
872 * m68k.h (m68010up): OR fido_a.
874 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
876 * m68k.h (fido_a): New.
878 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
880 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
881 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
884 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
886 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
888 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
890 * score-inst.h (enum score_insn_type): Add Insn_internal.
892 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
893 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
894 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
895 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
896 Alan Modra <amodra@bigpond.net.au>
898 * spu-insns.h: New file.
901 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
903 * ppc.h (PPC_OPCODE_CELL): Define.
905 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
907 * i386.h : Modify opcode to support for the change in POPCNT opcode
908 in amdfam10 architecture.
910 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
912 * i386.h: Replace CpuMNI with CpuSSSE3.
914 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
915 Joseph Myers <joseph@codesourcery.com>
916 Ian Lance Taylor <ian@wasabisystems.com>
917 Ben Elliston <bje@wasabisystems.com>
919 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
921 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
923 * score-datadep.h: New file.
924 * score-inst.h: New file.
926 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
928 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
929 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
932 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
933 Michael Meissner <michael.meissner@amd.com>
935 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
937 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
939 * i386.h (i386_optab): Add "nop" with memory reference.
941 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
943 * i386.h (i386_optab): Update comment for 64bit NOP.
945 2006-06-06 Ben Elliston <bje@au.ibm.com>
946 Anton Blanchard <anton@samba.org>
948 * ppc.h (PPC_OPCODE_POWER6): Define.
951 2006-06-05 Thiemo Seufer <ths@mips.com>
953 * mips.h: Improve description of MT flags.
955 2006-05-25 Richard Sandiford <richard@codesourcery.com>
957 * m68k.h (mcf_mask): Define.
959 2006-05-05 Thiemo Seufer <ths@mips.com>
960 David Ung <davidu@mips.com>
962 * mips.h (enum): Add macro M_CACHE_AB.
964 2006-05-04 Thiemo Seufer <ths@mips.com>
965 Nigel Stephens <nigel@mips.com>
966 David Ung <davidu@mips.com>
968 * mips.h: Add INSN_SMARTMIPS define.
970 2006-04-30 Thiemo Seufer <ths@mips.com>
971 David Ung <davidu@mips.com>
973 * mips.h: Defines udi bits and masks. Add description of
974 characters which may appear in the args field of udi
977 2006-04-26 Thiemo Seufer <ths@networkno.de>
979 * mips.h: Improve comments describing the bitfield instruction
982 2006-04-26 Julian Brown <julian@codesourcery.com>
984 * arm.h (FPU_VFP_EXT_V3): Define constant.
985 (FPU_NEON_EXT_V1): Likewise.
986 (FPU_VFP_HARD): Update.
987 (FPU_VFP_V3): Define macro.
988 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
990 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
992 * avr.h (AVR_ISA_PWMx): New.
994 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
996 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
997 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
998 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
999 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1000 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1002 2006-03-10 Paul Brook <paul@codesourcery.com>
1004 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1006 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1008 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1009 first. Correct mask of bb "B" opcode.
1011 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1013 * i386.h (i386_optab): Support Intel Merom New Instructions.
1015 2006-02-24 Paul Brook <paul@codesourcery.com>
1017 * arm.h: Add V7 feature bits.
1019 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1021 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1023 2006-01-31 Paul Brook <paul@codesourcery.com>
1024 Richard Earnshaw <rearnsha@arm.com>
1026 * arm.h: Use ARM_CPU_FEATURE.
1027 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1028 (arm_feature_set): Change to a structure.
1029 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1030 ARM_FEATURE): New macros.
1032 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
1034 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1035 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1036 (ADD_PC_INCR_OPCODE): Don't define.
1038 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1041 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1043 2005-11-14 David Ung <davidu@mips.com>
1045 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1046 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1047 save/restore encoding of the args field.
1049 2005-10-28 Dave Brolley <brolley@redhat.com>
1051 Contribute the following changes:
1052 2005-02-16 Dave Brolley <brolley@redhat.com>
1054 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1055 cgen_isa_mask_* to cgen_bitset_*.
1058 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1060 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1061 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1062 (CGEN_CPU_TABLE): Make isas a ponter.
1064 2003-09-29 Dave Brolley <brolley@redhat.com>
1066 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1067 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1068 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1070 2002-12-13 Dave Brolley <brolley@redhat.com>
1072 * cgen.h (symcat.h): #include it.
1073 (cgen-bitset.h): #include it.
1074 (CGEN_ATTR_VALUE_TYPE): Now a union.
1075 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1076 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1077 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1078 * cgen-bitset.h: New file.
1080 2005-09-30 Catherine Moore <clm@cm00re.com>
1084 2005-10-24 Jan Beulich <jbeulich@novell.com>
1086 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1089 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1091 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1092 Add FLAG_STRICT to pa10 ftest opcode.
1094 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1096 * hppa.h (pa_opcodes): Remove lha entries.
1098 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1100 * hppa.h (FLAG_STRICT): Revise comment.
1101 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1102 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1105 2005-09-30 Catherine Moore <clm@cm00re.com>
1109 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1111 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1113 2005-09-06 Chao-ying Fu <fu@mips.com>
1115 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1116 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1118 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1119 (INSN_ASE_MASK): Update to include INSN_MT.
1120 (INSN_MT): New define for MT ASE.
1122 2005-08-25 Chao-ying Fu <fu@mips.com>
1124 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1125 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1126 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1127 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1128 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1129 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1131 (INSN_DSP): New define for DSP ASE.
1133 2005-08-18 Alan Modra <amodra@bigpond.net.au>
1137 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1139 * ppc.h (PPC_OPCODE_E300): Define.
1141 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1143 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1145 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1148 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1151 2005-07-27 Jan Beulich <jbeulich@novell.com>
1153 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1154 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1155 Add movq-s as 64-bit variants of movd-s.
1157 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1159 * hppa.h: Fix punctuation in comment.
1161 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1162 implicit space-register addressing. Set space-register bits on opcodes
1163 using implicit space-register addressing. Add various missing pa20
1164 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1165 space-register addressing. Use "fE" instead of "fe" in various
1168 2005-07-18 Jan Beulich <jbeulich@novell.com>
1170 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1172 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1174 * i386.h (i386_optab): Support Intel VMX Instructions.
1176 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1178 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1180 2005-07-05 Jan Beulich <jbeulich@novell.com>
1182 * i386.h (i386_optab): Add new insns.
1184 2005-07-01 Nick Clifton <nickc@redhat.com>
1186 * sparc.h: Add typedefs to structure declarations.
1188 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1191 * i386.h (i386_optab): Update comments for 64bit addressing on
1192 mov. Allow 64bit addressing for mov and movq.
1194 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1196 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1197 respectively, in various floating-point load and store patterns.
1199 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1201 * hppa.h (FLAG_STRICT): Correct comment.
1202 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1203 PA 2.0 mneumonics when equivalent. Entries with cache control
1204 completers now require PA 1.1. Adjust whitespace.
1206 2005-05-19 Anton Blanchard <anton@samba.org>
1208 * ppc.h (PPC_OPCODE_POWER5): Define.
1210 2005-05-10 Nick Clifton <nickc@redhat.com>
1212 * Update the address and phone number of the FSF organization in
1213 the GPL notices in the following files:
1214 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1215 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1216 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1217 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1218 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1219 tic54x.h, tic80.h, v850.h, vax.h
1221 2005-05-09 Jan Beulich <jbeulich@novell.com>
1223 * i386.h (i386_optab): Add ht and hnt.
1225 2005-04-18 Mark Kettenis <kettenis@gnu.org>
1227 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1228 Add xcrypt-ctr. Provide aliases without hyphens.
1230 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1232 Moved from ../ChangeLog
1234 2005-04-12 Paul Brook <paul@codesourcery.com>
1235 * m88k.h: Rename psr macros to avoid conflicts.
1237 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1238 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1239 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1240 and ARM_ARCH_V6ZKT2.
1242 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1243 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1244 Remove redundant instruction types.
1245 (struct argument): X_op - new field.
1246 (struct cst4_entry): Remove.
1247 (no_op_insn): Declare.
1249 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1250 * crx.h (enum argtype): Rename types, remove unused types.
1252 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1253 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1254 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1255 (enum operand_type): Rearrange operands, edit comments.
1256 replace us<N> with ui<N> for unsigned immediate.
1257 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1258 displacements (respectively).
1259 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1260 (instruction type): Add NO_TYPE_INS.
1261 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1262 (operand_entry): New field - 'flags'.
1263 (operand flags): New.
1265 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1266 * crx.h (operand_type): Remove redundant types i3, i4,
1268 Add new unsigned immediate types us3, us4, us5, us16.
1270 2005-04-12 Mark Kettenis <kettenis@gnu.org>
1272 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1273 adjust them accordingly.
1275 2005-04-01 Jan Beulich <jbeulich@novell.com>
1277 * i386.h (i386_optab): Add rdtscp.
1279 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1281 * i386.h (i386_optab): Don't allow the `l' suffix for moving
1282 between memory and segment register. Allow movq for moving between
1283 general-purpose register and segment register.
1285 2005-02-09 Jan Beulich <jbeulich@novell.com>
1288 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1289 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1292 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1294 * m68k.h (m68008, m68ec030, m68882): Remove.
1296 (cpu_m68k, cpu_cf): New.
1297 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1298 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1300 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
1302 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1303 * cgen.h (enum cgen_parse_operand_type): Add
1304 CGEN_PARSE_OPERAND_SYMBOLIC.
1306 2005-01-21 Fred Fish <fnf@specifixinc.com>
1308 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1309 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1310 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1312 2005-01-19 Fred Fish <fnf@specifixinc.com>
1314 * mips.h (struct mips_opcode): Add new pinfo2 member.
1315 (INSN_ALIAS): New define for opcode table entries that are
1316 specific instances of another entry, such as 'move' for an 'or'
1317 with a zero operand.
1318 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1319 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1321 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1323 * mips.h (CPU_RM9000): Define.
1324 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1326 2004-11-25 Jan Beulich <jbeulich@novell.com>
1328 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1329 to/from test registers are illegal in 64-bit mode. Add missing
1330 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1331 (previously one had to explicitly encode a rex64 prefix). Re-enable
1332 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1333 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1335 2004-11-23 Jan Beulich <jbeulich@novell.com>
1337 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1338 available only with SSE2. Change the MMX additions introduced by SSE
1339 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1340 instructions by their now designated identifier (since combining i686
1341 and 3DNow! does not really imply 3DNow!A).
1343 2004-11-19 Alan Modra <amodra@bigpond.net.au>
1345 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1346 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1348 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1349 Vineet Sharma <vineets@noida.hcltech.com>
1351 * maxq.h: New file: Disassembly information for the maxq port.
1353 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1355 * i386.h (i386_optab): Put back "movzb".
1357 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
1359 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1360 comments. Remove member cris_ver_sim. Add members
1361 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1362 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1363 (struct cris_support_reg, struct cris_cond15): New types.
1364 (cris_conds15): Declare.
1365 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1366 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1367 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1368 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1369 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1370 SIZE_FIELD_UNSIGNED.
1372 2004-11-04 Jan Beulich <jbeulich@novell.com>
1374 * i386.h (sldx_Suf): Remove.
1375 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1376 (q_FP): Define, implying no REX64.
1377 (x_FP, sl_FP): Imply FloatMF.
1378 (i386_optab): Split reg and mem forms of moving from segment registers
1379 so that the memory forms can ignore the 16-/32-bit operand size
1380 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1381 all non-floating-point instructions. Unite 32- and 64-bit forms of
1382 movsx, movzx, and movd. Adjust floating point operations for the above
1383 changes to the *FP macros. Add DefaultSize to floating point control
1384 insns operating on larger memory ranges. Remove left over comments
1385 hinting at certain insns being Intel-syntax ones where the ones
1386 actually meant are already gone.
1388 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1390 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1393 2004-09-30 Paul Brook <paul@codesourcery.com>
1395 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1396 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1398 2004-09-11 Theodore A. Roth <troth@openavr.org>
1400 * avr.h: Add support for
1401 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1403 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1405 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1407 2004-08-24 Dmitry Diky <diwil@spec.ru>
1409 * msp430.h (msp430_opc): Add new instructions.
1410 (msp430_rcodes): Declare new instructions.
1411 (msp430_hcodes): Likewise..
1413 2004-08-13 Nick Clifton <nickc@redhat.com>
1416 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1419 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1421 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1423 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1425 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1427 2004-07-21 Jan Beulich <jbeulich@novell.com>
1429 * i386.h: Adjust instruction descriptions to better match the
1432 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
1434 * arm.h: Remove all old content. Replace with architecture defines
1435 from gas/config/tc-arm.c.
1437 2004-07-09 Andreas Schwab <schwab@suse.de>
1439 * m68k.h: Fix comment.
1441 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1445 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1447 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1449 2004-05-24 Peter Barada <peter@the-baradas.com>
1451 * m68k.h: Add 'size' to m68k_opcode.
1453 2004-05-05 Peter Barada <peter@the-baradas.com>
1455 * m68k.h: Switch from ColdFire chip name to core variant.
1457 2004-04-22 Peter Barada <peter@the-baradas.com>
1459 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1460 descriptions for new EMAC cases.
1461 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1462 handle Motorola MAC syntax.
1463 Allow disassembly of ColdFire V4e object files.
1465 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1467 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1469 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1471 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1473 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1475 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1477 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1479 * i386.h (i386_optab): Added xstore/xcrypt insns.
1481 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1483 * h8300.h (32bit ldc/stc): Add relaxing support.
1485 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1487 * h8300.h (BITOP): Pass MEMRELAX flag.
1489 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1491 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1494 For older changes see ChangeLog-9103
1500 version-control: never