1 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
3 * mips.h: Remove "mi" documentation. Update "mh" documentation.
4 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
6 (INSN2_WRITE_GPR_MHI): Rename to...
7 (INSN2_WRITE_GPR_MH): ...this.
9 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
11 * mips.h: Remove documentation of "+D" and "+T".
13 2013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
15 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
16 Use "source" rather than "destination" for microMIPS "G".
18 2013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
20 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
23 2013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
25 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
27 2013-06-17 Catherine Moore <clm@codesourcery.com>
28 Maciej W. Rozycki <macro@codesourcery.com>
29 Chao-Ying Fu <fu@mips.com>
31 * mips.h (OP_SH_EVAOFFSET): Define.
32 (OP_MASK_EVAOFFSET): Define.
33 (INSN_ASE_MASK): Delete.
35 (M_CACHEE_AB, M_CACHEE_OB): New.
36 (M_LBE_OB, M_LBE_AB): New.
37 (M_LBUE_OB, M_LBUE_AB): New.
38 (M_LHE_OB, M_LHE_AB): New.
39 (M_LHUE_OB, M_LHUE_AB): New.
40 (M_LLE_AB, M_LLE_OB): New.
41 (M_LWE_OB, M_LWE_AB): New.
42 (M_LWLE_AB, M_LWLE_OB): New.
43 (M_LWRE_AB, M_LWRE_OB): New.
44 (M_PREFE_AB, M_PREFE_OB): New.
45 (M_SCE_AB, M_SCE_OB): New.
46 (M_SBE_OB, M_SBE_AB): New.
47 (M_SHE_OB, M_SHE_AB): New.
48 (M_SWE_OB, M_SWE_AB): New.
49 (M_SWLE_AB, M_SWLE_OB): New.
50 (M_SWRE_AB, M_SWRE_OB): New.
51 (MICROMIPSOP_SH_EVAOFFSET): Define.
52 (MICROMIPSOP_MASK_EVAOFFSET): Define.
54 2013-06-12 Sandra Loosemore <sandra@codesourcery.com>
56 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
58 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
60 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
62 2013-05-09 Andrew Pinski <apinski@cavium.com>
64 * mips.h (OP_MASK_CODE10): Correct definition.
65 (OP_SH_CODE10): Likewise.
66 Add a comment that "+J" is used now for OP_*CODE10.
67 (INSN_ASE_MASK): Update.
68 (INSN_VIRT): New macro.
69 (INSN_VIRT64): New macro
71 2013-05-02 Nick Clifton <nickc@redhat.com>
73 * msp430.h: Add patterns for MSP430X instructions.
75 2013-04-06 David S. Miller <davem@davemloft.net>
77 * sparc.h (F_PREFERRED): Define.
78 (F_PREF_ALIAS): Define.
80 2013-04-03 Nick Clifton <nickc@redhat.com>
82 * v850.h (V850_INVERSE_PCREL): Define.
84 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
87 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
89 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
92 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
94 * tic6xc-opcode-table.h: Add 16-bit insns.
95 * tic6x.h: Add support for 16-bit insns.
97 2013-03-21 Michael Schewe <michael.schewe@gmx.net>
99 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
100 and mov.b/w/l Rs,@(d:32,ERd).
102 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
105 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
106 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
107 tic6x_operand_xregpair operand coding type.
108 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
109 opcode field, usu ORXREGD1324 for the src2 operand and remove the
112 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
115 * tic6x.h (enum tic6x_coding_method): Add
116 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
117 separately the msb and lsb of a register pair. This is needed to
118 encode the opcodes in the same way as TI assembler does.
119 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
120 and rsqrdp opcodes to use the new field coding types.
122 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
124 * arm.h (CRC_EXT_ARMV8): New constant.
125 (ARCH_CRC_ARMV8): New macro.
127 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
129 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
131 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
132 Andrew Jenner <andrew@codesourcery.com>
134 Based on patches from Altera Corporation.
138 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
140 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
142 2013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
145 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
147 2013-01-24 Nick Clifton <nickc@redhat.com>
149 * v850.h: Add e3v5 support.
151 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
153 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
155 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
157 * ppc.h (PPC_OPCODE_POWER8): New define.
158 (PPC_OPCODE_HTM): Likewise.
160 2013-01-10 Will Newton <will.newton@imgtec.com>
164 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
166 * cr16.h (make_instruction): Rename to cr16_make_instruction.
167 (match_opcode): Rename to cr16_match_opcode.
169 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
171 * mips.h: Add support for r5900 instructions including lq and sq.
173 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
175 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
176 (make_instruction,match_opcode): Added function prototypes.
177 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
179 2012-11-23 Alan Modra <amodra@gmail.com>
181 * ppc.h (ppc_parse_cpu): Update prototype.
183 2012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
185 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
186 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
188 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
190 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
192 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
194 * ia64.h (ia64_opnd): Add new operand types.
196 2012-08-21 David S. Miller <davem@davemloft.net>
198 * sparc.h (F3F4): New macro.
200 2012-08-13 Ian Bolton <ian.bolton@arm.com>
201 Laurent Desnogues <laurent.desnogues@arm.com>
202 Jim MacArthur <jim.macarthur@arm.com>
203 Marcus Shawcroft <marcus.shawcroft@arm.com>
204 Nigel Stephens <nigel.stephens@arm.com>
205 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
206 Richard Earnshaw <rearnsha@arm.com>
207 Sofiane Naci <sofiane.naci@arm.com>
208 Tejas Belagod <tejas.belagod@arm.com>
209 Yufeng Zhang <yufeng.zhang@arm.com>
211 * aarch64.h: New file.
213 2012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
214 Maciej W. Rozycki <macro@codesourcery.com>
216 * mips.h (mips_opcode): Add the exclusions field.
217 (OPCODE_IS_MEMBER): Remove macro.
218 (cpu_is_member): New inline function.
219 (opcode_is_member): Likewise.
221 2012-07-31 Chao-Ying Fu <fu@mips.com>
222 Catherine Moore <clm@codesourcery.com>
223 Maciej W. Rozycki <macro@codesourcery.com>
225 * mips.h: Document microMIPS DSP ASE usage.
226 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
227 microMIPS DSP ASE support.
228 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
229 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
230 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
231 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
232 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
233 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
234 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
236 2012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
238 * mips.h: Fix a typo in description.
240 2012-06-07 Georg-Johann Lay <avr@gjlay.de>
242 * avr.h: (AVR_ISA_XCH): New define.
243 (AVR_ISA_XMEGA): Use it.
244 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
246 2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
248 * m68hc11.h: Add XGate definitions.
249 (struct m68hc11_opcode): Add xg_mask field.
251 2012-05-14 Catherine Moore <clm@codesourcery.com>
252 Maciej W. Rozycki <macro@codesourcery.com>
253 Rhonda Wittels <rhonda@codesourcery.com>
255 * ppc.h (PPC_OPCODE_VLE): New definition.
256 (PPC_OP_SA): New macro.
257 (PPC_OP_SE_VLE): New macro.
258 (PPC_OP): Use a variable shift amount.
259 (powerpc_operand): Update comments.
260 (PPC_OPSHIFT_INV): New macro.
261 (PPC_OPERAND_CR): Replace with...
262 (PPC_OPERAND_CR_BIT): ...this and
263 (PPC_OPERAND_CR_REG): ...this.
266 2012-05-03 Sean Keys <skeys@ipdatasys.com>
268 * xgate.h: Header file for XGATE assembler.
270 2012-04-27 David S. Miller <davem@davemloft.net>
272 * sparc.h: Document new arg code' )' for crypto RS3
275 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
276 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
277 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
278 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
279 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
280 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
281 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
282 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
283 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
284 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
285 HWCAP_CBCOND, HWCAP_CRC32): New defines.
287 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
289 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
291 2012-02-27 Alan Modra <amodra@gmail.com>
293 * crx.h (cst4_map): Update declaration.
295 2012-02-25 Walter Lee <walt@tilera.com>
297 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
299 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
300 TILEPRO_OPC_LW_TLS_SN.
302 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
304 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
305 (XRELEASE_PREFIX_OPCODE): Likewise.
307 2011-12-08 Andrew Pinski <apinski@cavium.com>
308 Adam Nemet <anemet@caviumnetworks.com>
310 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
311 (INSN_OCTEON2): New macro.
312 (CPU_OCTEON2): New macro.
313 (OPCODE_IS_MEMBER): Add Octeon2.
315 2011-11-29 Andrew Pinski <apinski@cavium.com>
317 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
318 (INSN_OCTEONP): New macro.
319 (CPU_OCTEONP): New macro.
320 (OPCODE_IS_MEMBER): Add Octeon+.
321 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
323 2011-11-01 DJ Delorie <dj@redhat.com>
327 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
329 * mips.h: Fix a typo in description.
331 2011-09-21 David S. Miller <davem@davemloft.net>
333 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
334 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
335 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
336 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
338 2011-08-09 Chao-ying Fu <fu@mips.com>
339 Maciej W. Rozycki <macro@codesourcery.com>
341 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
342 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
343 (INSN_ASE_MASK): Add the MCU bit.
344 (INSN_MCU): New macro.
345 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
346 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
348 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
350 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
351 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
352 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
353 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
354 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
355 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
356 (INSN2_READ_GPR_MMN): Likewise.
357 (INSN2_READ_FPR_D): Change the bit used.
358 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
359 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
360 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
361 (INSN2_COND_BRANCH): Likewise.
362 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
363 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
364 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
365 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
366 (INSN2_MOD_GPR_MN): Likewise.
368 2011-08-05 David S. Miller <davem@davemloft.net>
370 * sparc.h: Document new format codes '4', '5', and '('.
371 (OPF_LOW4, RS3): New macros.
373 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
375 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
376 order of flags documented.
378 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
380 * mips.h: Clarify the description of microMIPS instruction
382 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
384 2011-07-24 Chao-ying Fu <fu@mips.com>
385 Maciej W. Rozycki <macro@codesourcery.com>
387 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
388 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
389 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
390 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
391 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
392 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
393 (OP_MASK_RS3, OP_SH_RS3): Likewise.
394 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
395 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
396 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
397 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
398 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
399 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
400 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
401 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
402 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
403 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
404 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
405 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
406 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
407 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
408 (INSN_WRITE_GPR_S): New macro.
409 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
410 (INSN2_READ_FPR_D): Likewise.
411 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
412 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
413 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
414 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
415 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
416 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
417 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
418 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
419 (CPU_MICROMIPS): New macro.
420 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
421 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
422 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
423 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
424 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
425 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
426 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
427 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
428 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
429 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
430 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
431 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
432 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
433 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
434 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
435 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
436 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
437 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
438 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
439 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
440 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
441 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
442 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
443 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
444 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
445 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
446 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
447 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
448 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
449 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
450 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
451 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
452 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
453 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
454 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
455 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
456 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
457 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
458 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
459 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
460 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
461 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
462 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
463 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
464 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
465 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
466 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
467 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
468 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
469 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
470 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
471 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
472 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
473 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
474 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
475 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
476 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
477 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
478 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
479 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
480 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
481 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
482 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
483 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
484 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
485 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
486 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
487 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
488 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
489 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
490 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
491 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
492 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
493 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
494 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
495 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
496 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
497 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
498 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
499 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
500 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
501 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
502 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
503 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
504 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
505 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
506 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
507 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
508 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
509 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
510 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
511 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
512 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
513 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
514 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
515 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
516 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
517 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
518 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
519 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
520 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
521 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
522 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
523 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
524 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
525 (micromips_opcodes): New declaration.
526 (bfd_micromips_num_opcodes): Likewise.
528 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
530 * mips.h (INSN_TRAP): Rename to...
531 (INSN_NO_DELAY_SLOT): ... this.
532 (INSN_SYNC): Remove macro.
534 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
536 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
537 a duplicate of AVR_ISA_SPM.
539 2011-07-01 Nick Clifton <nickc@redhat.com>
541 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
543 2011-06-18 Robin Getz <robin.getz@analog.com>
545 * bfin.h (is_macmod_signed): New func
547 2011-06-18 Mike Frysinger <vapier@gentoo.org>
549 * bfin.h (is_macmod_pmove): Add missing space before func args.
550 (is_macmod_hmove): Likewise.
552 2011-06-13 Walter Lee <walt@tilera.com>
554 * tilegx.h: New file.
555 * tilepro.h: New file.
557 2011-05-31 Paul Brook <paul@codesourcery.com>
559 * arm.h (ARM_ARCH_V7R_IDIV): Define.
561 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
563 * s390.h: Replace S390_OPERAND_REG_EVEN with
564 S390_OPERAND_REG_PAIR.
566 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
568 * s390.h: Add S390_OPCODE_REG_EVEN flag.
570 2011-04-18 Julian Brown <julian@codesourcery.com>
572 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
574 2011-04-11 Dan McDonald <dan@wellkeeper.com>
577 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
579 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
581 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
582 New instruction set flags.
583 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
585 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
587 * mips.h (M_PREF_AB): New enum value.
589 2011-02-12 Mike Frysinger <vapier@gentoo.org>
591 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
593 (is_macmod_pmove, is_macmod_hmove): New functions.
595 2011-02-11 Mike Frysinger <vapier@gentoo.org>
597 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
599 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
601 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
602 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
604 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
607 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
610 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
613 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
615 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
617 * mips.h: Update commentary after last commit.
619 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
621 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
622 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
623 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
625 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
627 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
629 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
631 * mips.h: Fix previous commit.
633 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
635 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
636 (INSN_LOONGSON_3A): Clear bit 31.
638 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
641 * arm.h (ARM_AEXT_V6M_ONLY): New define.
642 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
643 (ARM_ARCH_V6M_ONLY): New define.
645 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
647 * mips.h (INSN_LOONGSON_3A): Defined.
648 (CPU_LOONGSON_3A): Defined.
649 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
651 2010-10-09 Matt Rice <ratmice@gmail.com>
653 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
654 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
656 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
658 * arm.h (ARM_EXT_VIRT): New define.
659 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
660 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
663 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
665 * arm.h (ARM_AEXT_ADIV): New define.
666 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
668 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
670 * arm.h (ARM_EXT_OS): New define.
671 (ARM_AEXT_V6SM): Likewise.
672 (ARM_ARCH_V6SM): Likewise.
674 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
676 * arm.h (ARM_EXT_MP): Add.
677 (ARM_ARCH_V7A_MP): Likewise.
679 2010-09-22 Mike Frysinger <vapier@gentoo.org>
681 * bfin.h: Declare pseudoChr structs/defines.
683 2010-09-21 Mike Frysinger <vapier@gentoo.org>
685 * bfin.h: Strip trailing whitespace.
687 2010-07-29 DJ Delorie <dj@redhat.com>
689 * rx.h (RX_Operand_Type): Add TwoReg.
690 (RX_Opcode_ID): Remove ediv and ediv2.
692 2010-07-27 DJ Delorie <dj@redhat.com>
694 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
696 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
697 Ina Pandit <ina.pandit@kpitcummins.com>
699 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
700 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
701 PROCESSOR_V850E2_ALL.
702 Remove PROCESSOR_V850EA support.
703 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
704 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
705 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
706 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
707 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
708 V850_OPERAND_PERCENT.
709 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
711 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
714 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
716 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
717 (MIPS16_INSN_BRANCH): Rename to...
718 (MIPS16_INSN_COND_BRANCH): ... this.
720 2010-07-03 Alan Modra <amodra@gmail.com>
722 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
723 Renumber other PPC_OPCODE defines.
725 2010-07-03 Alan Modra <amodra@gmail.com>
727 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
729 2010-06-29 Alan Modra <amodra@gmail.com>
731 * maxq.h: Delete file.
733 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
735 * ppc.h (PPC_OPCODE_E500): Define.
737 2010-05-26 Catherine Moore <clm@codesourcery.com>
739 * opcode/mips.h (INSN_MIPS16): Remove.
741 2010-04-21 Joseph Myers <joseph@codesourcery.com>
743 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
745 2010-04-15 Nick Clifton <nickc@redhat.com>
747 * alpha.h: Update copyright notice to use GPLv3.
753 * convex.h: Likewise.
767 * m68hc11.h: Likewise.
773 * mn10200.h: Likewise.
774 * mn10300.h: Likewise.
775 * msp430.h: Likewise.
786 * score-datadep.h: Likewise.
787 * score-inst.h: Likewise.
789 * spu-insns.h: Likewise.
793 * tic54x.h: Likewise.
798 2010-03-25 Joseph Myers <joseph@codesourcery.com>
800 * tic6x-control-registers.h, tic6x-insn-formats.h,
801 tic6x-opcode-table.h, tic6x.h: New.
803 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
805 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
807 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
809 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
811 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
813 * ia64.h (ia64_find_opcode): Remove argument name.
814 (ia64_find_next_opcode): Likewise.
815 (ia64_dis_opcode): Likewise.
816 (ia64_free_opcode): Likewise.
817 (ia64_find_dependency): Likewise.
819 2009-11-22 Doug Evans <dje@sebabeach.org>
821 * cgen.h: Include bfd_stdint.h.
822 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
824 2009-11-18 Paul Brook <paul@codesourcery.com>
826 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
828 2009-11-17 Paul Brook <paul@codesourcery.com>
829 Daniel Jacobowitz <dan@codesourcery.com>
831 * arm.h (ARM_EXT_V6_DSP): Define.
832 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
833 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
835 2009-11-04 DJ Delorie <dj@redhat.com>
837 * rx.h (rx_decode_opcode) (mvtipl): Add.
838 (mvtcp, mvfcp, opecp): Remove.
840 2009-11-02 Paul Brook <paul@codesourcery.com>
842 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
843 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
844 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
845 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
846 FPU_ARCH_NEON_VFP_V4): Define.
848 2009-10-23 Doug Evans <dje@sebabeach.org>
850 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
851 * cgen.h: Update. Improve multi-inclusion macro name.
853 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
855 * ppc.h (PPC_OPCODE_476): Define.
857 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
859 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
861 2009-09-29 DJ Delorie <dj@redhat.com>
865 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
867 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
869 2009-09-21 Ben Elliston <bje@au.ibm.com>
871 * ppc.h (PPC_OPCODE_PPCA2): New.
873 2009-09-05 Martin Thuresson <martin@mtme.org>
875 * ia64.h (struct ia64_operand): Renamed member class to op_class.
877 2009-08-29 Martin Thuresson <martin@mtme.org>
879 * tic30.h (template): Rename type template to
880 insn_template. Updated code to use new name.
881 * tic54x.h (template): Rename type template to
884 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
886 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
888 2009-06-11 Anthony Green <green@moxielogic.com>
890 * moxie.h (MOXIE_F3_PCREL): Define.
891 (moxie_form3_opc_info): Grow.
893 2009-06-06 Anthony Green <green@moxielogic.com>
895 * moxie.h (MOXIE_F1_M): Define.
897 2009-04-15 Anthony Green <green@moxielogic.com>
901 2009-04-06 DJ Delorie <dj@redhat.com>
903 * h8300.h: Add relaxation attributes to MOVA opcodes.
905 2009-03-10 Alan Modra <amodra@bigpond.net.au>
907 * ppc.h (ppc_parse_cpu): Declare.
909 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
911 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
912 and _IMM11 for mbitclr and mbitset.
913 * score-datadep.h: Update dependency information.
915 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
917 * ppc.h (PPC_OPCODE_POWER7): New.
919 2009-02-06 Doug Evans <dje@google.com>
921 * i386.h: Add comment regarding sse* insns and prefixes.
923 2009-02-03 Sandip Matte <sandip@rmicorp.com>
925 * mips.h (INSN_XLR): Define.
926 (INSN_CHIP_MASK): Update.
928 (OPCODE_IS_MEMBER): Update.
929 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
931 2009-01-28 Doug Evans <dje@google.com>
933 * opcode/i386.h: Add multiple inclusion protection.
934 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
935 (EDI_REG_NUM): New macros.
936 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
937 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
938 (REX_PREFIX_P): New macro.
940 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
942 * ppc.h (struct powerpc_opcode): New field "deprecated".
943 (PPC_OPCODE_NOPOWER4): Delete.
945 2008-11-28 Joshua Kinard <kumba@gentoo.org>
947 * mips.h: Define CPU_R14000, CPU_R16000.
948 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
950 2008-11-18 Catherine Moore <clm@codesourcery.com>
952 * arm.h (FPU_NEON_FP16): New.
953 (FPU_ARCH_NEON_FP16): New.
955 2008-11-06 Chao-ying Fu <fu@mips.com>
957 * mips.h: Doucument '1' for 5-bit sync type.
959 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
961 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
964 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
966 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
968 2008-07-30 Michael J. Eager <eager@eagercon.com>
970 * ppc.h (PPC_OPCODE_405): Define.
971 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
973 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
975 * ppc.h (ppc_cpu_t): New typedef.
976 (struct powerpc_opcode <flags>): Use it.
977 (struct powerpc_operand <insert, extract>): Likewise.
978 (struct powerpc_macro <flags>): Likewise.
980 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
982 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
983 Update comment before MIPS16 field descriptors to mention MIPS16.
984 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
986 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
987 New bit masks and shift counts for cins and exts.
989 * mips.h: Document new field descriptors +Q.
990 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
992 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
994 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
995 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
997 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
999 * ppc.h: (PPC_OPCODE_E500MC): New.
1001 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1003 * i386.h (MAX_OPERANDS): Set to 5.
1004 (MAX_MNEM_SIZE): Changed to 20.
1006 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1008 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1010 2008-03-09 Paul Brook <paul@codesourcery.com>
1012 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1014 2008-03-04 Paul Brook <paul@codesourcery.com>
1016 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1017 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1018 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1020 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
1021 Nick Clifton <nickc@redhat.com>
1024 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1025 with a 32-bit displacement but without the top bit of the 4th byte
1028 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1030 * cr16.h (cr16_num_optab): Declared.
1032 2008-02-14 Hakan Ardo <hakan@debian.org>
1035 * avr.h (AVR_ISA_2xxe): Define.
1037 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1039 * mips.h: Update copyright.
1040 (INSN_CHIP_MASK): New macro.
1041 (INSN_OCTEON): New macro.
1042 (CPU_OCTEON): New macro.
1043 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1045 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1047 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1049 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1051 * avr.h (AVR_ISA_USB162): Add new opcode set.
1052 (AVR_ISA_AVR3): Likewise.
1054 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1056 * mips.h (INSN_LOONGSON_2E): New.
1057 (INSN_LOONGSON_2F): New.
1058 (CPU_LOONGSON_2E): New.
1059 (CPU_LOONGSON_2F): New.
1060 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1062 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1064 * mips.h (INSN_ISA*): Redefine certain values as an
1065 enumeration. Update comments.
1066 (mips_isa_table): New.
1067 (ISA_MIPS*): Redefine to match enumeration.
1068 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1071 2007-08-08 Ben Elliston <bje@au.ibm.com>
1073 * ppc.h (PPC_OPCODE_PPCPS): New.
1075 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1077 * m68k.h: Document j K & E.
1079 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1081 * cr16.h: New file for CR16 target.
1083 2007-05-02 Alan Modra <amodra@bigpond.net.au>
1085 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1087 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1089 * m68k.h (mcfisa_c): New.
1090 (mcfusp, mcf_mask): Adjust.
1092 2007-04-20 Alan Modra <amodra@bigpond.net.au>
1094 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1095 (num_powerpc_operands): Declare.
1096 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1097 (PPC_OPERAND_PLUS1): Define.
1099 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
1101 * i386.h (REX_MODE64): Renamed to ...
1103 (REX_EXTX): Renamed to ...
1105 (REX_EXTY): Renamed to ...
1107 (REX_EXTZ): Renamed to ...
1110 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1112 * i386.h: Add entries from config/tc-i386.h and move tables
1113 to opcodes/i386-opc.h.
1115 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1117 * i386.h (FloatDR): Removed.
1118 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1120 2007-03-01 Alan Modra <amodra@bigpond.net.au>
1122 * spu-insns.h: Add soma double-float insns.
1124 2007-02-20 Thiemo Seufer <ths@mips.com>
1125 Chao-Ying Fu <fu@mips.com>
1127 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1128 (INSN_DSPR2): Add flag for DSP R2 instructions.
1129 (M_BALIGN): New macro.
1131 2007-02-14 Alan Modra <amodra@bigpond.net.au>
1133 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1134 and Seg3ShortFrom with Shortform.
1136 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1139 * i386.h (i386_optab): Put the real "test" before the pseudo
1142 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
1144 * m68k.h (m68010up): OR fido_a.
1146 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
1148 * m68k.h (fido_a): New.
1150 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
1152 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1153 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1156 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1158 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1160 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1162 * score-inst.h (enum score_insn_type): Add Insn_internal.
1164 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1165 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1166 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1167 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1168 Alan Modra <amodra@bigpond.net.au>
1170 * spu-insns.h: New file.
1173 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1175 * ppc.h (PPC_OPCODE_CELL): Define.
1177 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1179 * i386.h : Modify opcode to support for the change in POPCNT opcode
1180 in amdfam10 architecture.
1182 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1184 * i386.h: Replace CpuMNI with CpuSSSE3.
1186 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
1187 Joseph Myers <joseph@codesourcery.com>
1188 Ian Lance Taylor <ian@wasabisystems.com>
1189 Ben Elliston <bje@wasabisystems.com>
1191 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1193 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1195 * score-datadep.h: New file.
1196 * score-inst.h: New file.
1198 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1200 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1201 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1202 movdq2q and movq2dq.
1204 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1205 Michael Meissner <michael.meissner@amd.com>
1207 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1209 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1211 * i386.h (i386_optab): Add "nop" with memory reference.
1213 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1215 * i386.h (i386_optab): Update comment for 64bit NOP.
1217 2006-06-06 Ben Elliston <bje@au.ibm.com>
1218 Anton Blanchard <anton@samba.org>
1220 * ppc.h (PPC_OPCODE_POWER6): Define.
1223 2006-06-05 Thiemo Seufer <ths@mips.com>
1225 * mips.h: Improve description of MT flags.
1227 2006-05-25 Richard Sandiford <richard@codesourcery.com>
1229 * m68k.h (mcf_mask): Define.
1231 2006-05-05 Thiemo Seufer <ths@mips.com>
1232 David Ung <davidu@mips.com>
1234 * mips.h (enum): Add macro M_CACHE_AB.
1236 2006-05-04 Thiemo Seufer <ths@mips.com>
1237 Nigel Stephens <nigel@mips.com>
1238 David Ung <davidu@mips.com>
1240 * mips.h: Add INSN_SMARTMIPS define.
1242 2006-04-30 Thiemo Seufer <ths@mips.com>
1243 David Ung <davidu@mips.com>
1245 * mips.h: Defines udi bits and masks. Add description of
1246 characters which may appear in the args field of udi
1249 2006-04-26 Thiemo Seufer <ths@networkno.de>
1251 * mips.h: Improve comments describing the bitfield instruction
1254 2006-04-26 Julian Brown <julian@codesourcery.com>
1256 * arm.h (FPU_VFP_EXT_V3): Define constant.
1257 (FPU_NEON_EXT_V1): Likewise.
1258 (FPU_VFP_HARD): Update.
1259 (FPU_VFP_V3): Define macro.
1260 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1262 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
1264 * avr.h (AVR_ISA_PWMx): New.
1266 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1268 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1269 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1270 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1271 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1272 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1274 2006-03-10 Paul Brook <paul@codesourcery.com>
1276 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1278 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1280 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1281 first. Correct mask of bb "B" opcode.
1283 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1285 * i386.h (i386_optab): Support Intel Merom New Instructions.
1287 2006-02-24 Paul Brook <paul@codesourcery.com>
1289 * arm.h: Add V7 feature bits.
1291 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1293 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1295 2006-01-31 Paul Brook <paul@codesourcery.com>
1296 Richard Earnshaw <rearnsha@arm.com>
1298 * arm.h: Use ARM_CPU_FEATURE.
1299 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1300 (arm_feature_set): Change to a structure.
1301 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1302 ARM_FEATURE): New macros.
1304 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
1306 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1307 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1308 (ADD_PC_INCR_OPCODE): Don't define.
1310 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1313 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1315 2005-11-14 David Ung <davidu@mips.com>
1317 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1318 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1319 save/restore encoding of the args field.
1321 2005-10-28 Dave Brolley <brolley@redhat.com>
1323 Contribute the following changes:
1324 2005-02-16 Dave Brolley <brolley@redhat.com>
1326 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1327 cgen_isa_mask_* to cgen_bitset_*.
1330 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1332 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1333 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1334 (CGEN_CPU_TABLE): Make isas a ponter.
1336 2003-09-29 Dave Brolley <brolley@redhat.com>
1338 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1339 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1340 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1342 2002-12-13 Dave Brolley <brolley@redhat.com>
1344 * cgen.h (symcat.h): #include it.
1345 (cgen-bitset.h): #include it.
1346 (CGEN_ATTR_VALUE_TYPE): Now a union.
1347 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1348 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1349 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1350 * cgen-bitset.h: New file.
1352 2005-09-30 Catherine Moore <clm@cm00re.com>
1356 2005-10-24 Jan Beulich <jbeulich@novell.com>
1358 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1361 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1363 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1364 Add FLAG_STRICT to pa10 ftest opcode.
1366 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1368 * hppa.h (pa_opcodes): Remove lha entries.
1370 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1372 * hppa.h (FLAG_STRICT): Revise comment.
1373 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1374 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1377 2005-09-30 Catherine Moore <clm@cm00re.com>
1381 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1383 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1385 2005-09-06 Chao-ying Fu <fu@mips.com>
1387 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1388 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1390 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1391 (INSN_ASE_MASK): Update to include INSN_MT.
1392 (INSN_MT): New define for MT ASE.
1394 2005-08-25 Chao-ying Fu <fu@mips.com>
1396 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1397 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1398 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1399 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1400 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1401 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1403 (INSN_DSP): New define for DSP ASE.
1405 2005-08-18 Alan Modra <amodra@bigpond.net.au>
1409 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1411 * ppc.h (PPC_OPCODE_E300): Define.
1413 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1415 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1417 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1420 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1423 2005-07-27 Jan Beulich <jbeulich@novell.com>
1425 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1426 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1427 Add movq-s as 64-bit variants of movd-s.
1429 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1431 * hppa.h: Fix punctuation in comment.
1433 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1434 implicit space-register addressing. Set space-register bits on opcodes
1435 using implicit space-register addressing. Add various missing pa20
1436 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1437 space-register addressing. Use "fE" instead of "fe" in various
1440 2005-07-18 Jan Beulich <jbeulich@novell.com>
1442 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1444 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1446 * i386.h (i386_optab): Support Intel VMX Instructions.
1448 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1450 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1452 2005-07-05 Jan Beulich <jbeulich@novell.com>
1454 * i386.h (i386_optab): Add new insns.
1456 2005-07-01 Nick Clifton <nickc@redhat.com>
1458 * sparc.h: Add typedefs to structure declarations.
1460 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1463 * i386.h (i386_optab): Update comments for 64bit addressing on
1464 mov. Allow 64bit addressing for mov and movq.
1466 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1468 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1469 respectively, in various floating-point load and store patterns.
1471 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1473 * hppa.h (FLAG_STRICT): Correct comment.
1474 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1475 PA 2.0 mneumonics when equivalent. Entries with cache control
1476 completers now require PA 1.1. Adjust whitespace.
1478 2005-05-19 Anton Blanchard <anton@samba.org>
1480 * ppc.h (PPC_OPCODE_POWER5): Define.
1482 2005-05-10 Nick Clifton <nickc@redhat.com>
1484 * Update the address and phone number of the FSF organization in
1485 the GPL notices in the following files:
1486 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1487 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1488 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1489 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1490 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1491 tic54x.h, tic80.h, v850.h, vax.h
1493 2005-05-09 Jan Beulich <jbeulich@novell.com>
1495 * i386.h (i386_optab): Add ht and hnt.
1497 2005-04-18 Mark Kettenis <kettenis@gnu.org>
1499 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1500 Add xcrypt-ctr. Provide aliases without hyphens.
1502 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1504 Moved from ../ChangeLog
1506 2005-04-12 Paul Brook <paul@codesourcery.com>
1507 * m88k.h: Rename psr macros to avoid conflicts.
1509 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1510 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1511 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1512 and ARM_ARCH_V6ZKT2.
1514 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1515 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1516 Remove redundant instruction types.
1517 (struct argument): X_op - new field.
1518 (struct cst4_entry): Remove.
1519 (no_op_insn): Declare.
1521 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1522 * crx.h (enum argtype): Rename types, remove unused types.
1524 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1525 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1526 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1527 (enum operand_type): Rearrange operands, edit comments.
1528 replace us<N> with ui<N> for unsigned immediate.
1529 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1530 displacements (respectively).
1531 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1532 (instruction type): Add NO_TYPE_INS.
1533 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1534 (operand_entry): New field - 'flags'.
1535 (operand flags): New.
1537 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1538 * crx.h (operand_type): Remove redundant types i3, i4,
1540 Add new unsigned immediate types us3, us4, us5, us16.
1542 2005-04-12 Mark Kettenis <kettenis@gnu.org>
1544 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1545 adjust them accordingly.
1547 2005-04-01 Jan Beulich <jbeulich@novell.com>
1549 * i386.h (i386_optab): Add rdtscp.
1551 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1553 * i386.h (i386_optab): Don't allow the `l' suffix for moving
1554 between memory and segment register. Allow movq for moving between
1555 general-purpose register and segment register.
1557 2005-02-09 Jan Beulich <jbeulich@novell.com>
1560 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1561 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1564 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1566 * m68k.h (m68008, m68ec030, m68882): Remove.
1568 (cpu_m68k, cpu_cf): New.
1569 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1570 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1572 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
1574 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1575 * cgen.h (enum cgen_parse_operand_type): Add
1576 CGEN_PARSE_OPERAND_SYMBOLIC.
1578 2005-01-21 Fred Fish <fnf@specifixinc.com>
1580 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1581 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1582 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1584 2005-01-19 Fred Fish <fnf@specifixinc.com>
1586 * mips.h (struct mips_opcode): Add new pinfo2 member.
1587 (INSN_ALIAS): New define for opcode table entries that are
1588 specific instances of another entry, such as 'move' for an 'or'
1589 with a zero operand.
1590 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1591 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1593 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1595 * mips.h (CPU_RM9000): Define.
1596 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1598 2004-11-25 Jan Beulich <jbeulich@novell.com>
1600 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1601 to/from test registers are illegal in 64-bit mode. Add missing
1602 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1603 (previously one had to explicitly encode a rex64 prefix). Re-enable
1604 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1605 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1607 2004-11-23 Jan Beulich <jbeulich@novell.com>
1609 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1610 available only with SSE2. Change the MMX additions introduced by SSE
1611 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1612 instructions by their now designated identifier (since combining i686
1613 and 3DNow! does not really imply 3DNow!A).
1615 2004-11-19 Alan Modra <amodra@bigpond.net.au>
1617 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1618 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1620 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1621 Vineet Sharma <vineets@noida.hcltech.com>
1623 * maxq.h: New file: Disassembly information for the maxq port.
1625 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1627 * i386.h (i386_optab): Put back "movzb".
1629 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
1631 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1632 comments. Remove member cris_ver_sim. Add members
1633 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1634 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1635 (struct cris_support_reg, struct cris_cond15): New types.
1636 (cris_conds15): Declare.
1637 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1638 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1639 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1640 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1641 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1642 SIZE_FIELD_UNSIGNED.
1644 2004-11-04 Jan Beulich <jbeulich@novell.com>
1646 * i386.h (sldx_Suf): Remove.
1647 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1648 (q_FP): Define, implying no REX64.
1649 (x_FP, sl_FP): Imply FloatMF.
1650 (i386_optab): Split reg and mem forms of moving from segment registers
1651 so that the memory forms can ignore the 16-/32-bit operand size
1652 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1653 all non-floating-point instructions. Unite 32- and 64-bit forms of
1654 movsx, movzx, and movd. Adjust floating point operations for the above
1655 changes to the *FP macros. Add DefaultSize to floating point control
1656 insns operating on larger memory ranges. Remove left over comments
1657 hinting at certain insns being Intel-syntax ones where the ones
1658 actually meant are already gone.
1660 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1662 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1665 2004-09-30 Paul Brook <paul@codesourcery.com>
1667 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1668 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1670 2004-09-11 Theodore A. Roth <troth@openavr.org>
1672 * avr.h: Add support for
1673 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1675 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1677 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1679 2004-08-24 Dmitry Diky <diwil@spec.ru>
1681 * msp430.h (msp430_opc): Add new instructions.
1682 (msp430_rcodes): Declare new instructions.
1683 (msp430_hcodes): Likewise..
1685 2004-08-13 Nick Clifton <nickc@redhat.com>
1688 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1691 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1693 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1695 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1697 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1699 2004-07-21 Jan Beulich <jbeulich@novell.com>
1701 * i386.h: Adjust instruction descriptions to better match the
1704 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
1706 * arm.h: Remove all old content. Replace with architecture defines
1707 from gas/config/tc-arm.c.
1709 2004-07-09 Andreas Schwab <schwab@suse.de>
1711 * m68k.h: Fix comment.
1713 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1717 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1719 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1721 2004-05-24 Peter Barada <peter@the-baradas.com>
1723 * m68k.h: Add 'size' to m68k_opcode.
1725 2004-05-05 Peter Barada <peter@the-baradas.com>
1727 * m68k.h: Switch from ColdFire chip name to core variant.
1729 2004-04-22 Peter Barada <peter@the-baradas.com>
1731 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1732 descriptions for new EMAC cases.
1733 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1734 handle Motorola MAC syntax.
1735 Allow disassembly of ColdFire V4e object files.
1737 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1739 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1741 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1743 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1745 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1747 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1749 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1751 * i386.h (i386_optab): Added xstore/xcrypt insns.
1753 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1755 * h8300.h (32bit ldc/stc): Add relaxing support.
1757 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1759 * h8300.h (BITOP): Pass MEMRELAX flag.
1761 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1763 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1766 For older changes see ChangeLog-9103
1768 Copyright (C) 2004-2012 Free Software Foundation, Inc.
1770 Copying and distribution of this file, with or without modification,
1771 are permitted in any medium without royalty provided the copyright
1772 notice and this notice are preserved.
1778 version-control: never