1 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
3 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
5 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
6 Andrew Jenner <andrew@codesourcery.com>
8 Based on patches from Altera Corporation.
12 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
14 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
16 2013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
19 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
21 2013-01-24 Nick Clifton <nickc@redhat.com>
23 * v850.h: Add e3v5 support.
25 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
27 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
29 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
31 * ppc.h (PPC_OPCODE_POWER8): New define.
32 (PPC_OPCODE_HTM): Likewise.
34 2013-01-10 Will Newton <will.newton@imgtec.com>
38 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
40 * cr16.h (make_instruction): Rename to cr16_make_instruction.
41 (match_opcode): Rename to cr16_match_opcode.
43 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
45 * mips.h: Add support for r5900 instructions including lq and sq.
47 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
49 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
50 (make_instruction,match_opcode): Added function prototypes.
51 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
53 2012-11-23 Alan Modra <amodra@gmail.com>
55 * ppc.h (ppc_parse_cpu): Update prototype.
57 2012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
59 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
60 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
62 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
64 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
66 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
68 * ia64.h (ia64_opnd): Add new operand types.
70 2012-08-21 David S. Miller <davem@davemloft.net>
72 * sparc.h (F3F4): New macro.
74 2012-08-13 Ian Bolton <ian.bolton@arm.com>
75 Laurent Desnogues <laurent.desnogues@arm.com>
76 Jim MacArthur <jim.macarthur@arm.com>
77 Marcus Shawcroft <marcus.shawcroft@arm.com>
78 Nigel Stephens <nigel.stephens@arm.com>
79 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
80 Richard Earnshaw <rearnsha@arm.com>
81 Sofiane Naci <sofiane.naci@arm.com>
82 Tejas Belagod <tejas.belagod@arm.com>
83 Yufeng Zhang <yufeng.zhang@arm.com>
85 * aarch64.h: New file.
87 2012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
88 Maciej W. Rozycki <macro@codesourcery.com>
90 * mips.h (mips_opcode): Add the exclusions field.
91 (OPCODE_IS_MEMBER): Remove macro.
92 (cpu_is_member): New inline function.
93 (opcode_is_member): Likewise.
95 2012-07-31 Chao-Ying Fu <fu@mips.com>
96 Catherine Moore <clm@codesourcery.com>
97 Maciej W. Rozycki <macro@codesourcery.com>
99 * mips.h: Document microMIPS DSP ASE usage.
100 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
101 microMIPS DSP ASE support.
102 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
103 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
104 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
105 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
106 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
107 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
108 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
110 2012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
112 * mips.h: Fix a typo in description.
114 2012-06-07 Georg-Johann Lay <avr@gjlay.de>
116 * avr.h: (AVR_ISA_XCH): New define.
117 (AVR_ISA_XMEGA): Use it.
118 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
120 2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
122 * m68hc11.h: Add XGate definitions.
123 (struct m68hc11_opcode): Add xg_mask field.
125 2012-05-14 Catherine Moore <clm@codesourcery.com>
126 Maciej W. Rozycki <macro@codesourcery.com>
127 Rhonda Wittels <rhonda@codesourcery.com>
129 * ppc.h (PPC_OPCODE_VLE): New definition.
130 (PPC_OP_SA): New macro.
131 (PPC_OP_SE_VLE): New macro.
132 (PPC_OP): Use a variable shift amount.
133 (powerpc_operand): Update comments.
134 (PPC_OPSHIFT_INV): New macro.
135 (PPC_OPERAND_CR): Replace with...
136 (PPC_OPERAND_CR_BIT): ...this and
137 (PPC_OPERAND_CR_REG): ...this.
140 2012-05-03 Sean Keys <skeys@ipdatasys.com>
142 * xgate.h: Header file for XGATE assembler.
144 2012-04-27 David S. Miller <davem@davemloft.net>
146 * sparc.h: Document new arg code' )' for crypto RS3
149 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
150 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
151 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
152 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
153 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
154 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
155 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
156 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
157 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
158 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
159 HWCAP_CBCOND, HWCAP_CRC32): New defines.
161 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
163 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
165 2012-02-27 Alan Modra <amodra@gmail.com>
167 * crx.h (cst4_map): Update declaration.
169 2012-02-25 Walter Lee <walt@tilera.com>
171 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
173 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
174 TILEPRO_OPC_LW_TLS_SN.
176 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
178 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
179 (XRELEASE_PREFIX_OPCODE): Likewise.
181 2011-12-08 Andrew Pinski <apinski@cavium.com>
182 Adam Nemet <anemet@caviumnetworks.com>
184 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
185 (INSN_OCTEON2): New macro.
186 (CPU_OCTEON2): New macro.
187 (OPCODE_IS_MEMBER): Add Octeon2.
189 2011-11-29 Andrew Pinski <apinski@cavium.com>
191 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
192 (INSN_OCTEONP): New macro.
193 (CPU_OCTEONP): New macro.
194 (OPCODE_IS_MEMBER): Add Octeon+.
195 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
197 2011-11-01 DJ Delorie <dj@redhat.com>
201 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
203 * mips.h: Fix a typo in description.
205 2011-09-21 David S. Miller <davem@davemloft.net>
207 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
208 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
209 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
210 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
212 2011-08-09 Chao-ying Fu <fu@mips.com>
213 Maciej W. Rozycki <macro@codesourcery.com>
215 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
216 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
217 (INSN_ASE_MASK): Add the MCU bit.
218 (INSN_MCU): New macro.
219 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
220 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
222 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
224 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
225 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
226 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
227 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
228 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
229 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
230 (INSN2_READ_GPR_MMN): Likewise.
231 (INSN2_READ_FPR_D): Change the bit used.
232 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
233 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
234 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
235 (INSN2_COND_BRANCH): Likewise.
236 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
237 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
238 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
239 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
240 (INSN2_MOD_GPR_MN): Likewise.
242 2011-08-05 David S. Miller <davem@davemloft.net>
244 * sparc.h: Document new format codes '4', '5', and '('.
245 (OPF_LOW4, RS3): New macros.
247 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
249 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
250 order of flags documented.
252 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
254 * mips.h: Clarify the description of microMIPS instruction
256 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
258 2011-07-24 Chao-ying Fu <fu@mips.com>
259 Maciej W. Rozycki <macro@codesourcery.com>
261 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
262 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
263 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
264 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
265 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
266 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
267 (OP_MASK_RS3, OP_SH_RS3): Likewise.
268 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
269 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
270 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
271 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
272 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
273 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
274 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
275 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
276 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
277 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
278 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
279 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
280 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
281 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
282 (INSN_WRITE_GPR_S): New macro.
283 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
284 (INSN2_READ_FPR_D): Likewise.
285 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
286 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
287 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
288 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
289 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
290 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
291 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
292 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
293 (CPU_MICROMIPS): New macro.
294 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
295 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
296 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
297 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
298 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
299 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
300 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
301 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
302 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
303 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
304 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
305 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
306 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
307 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
308 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
309 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
310 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
311 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
312 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
313 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
314 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
315 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
316 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
317 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
318 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
319 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
320 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
321 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
322 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
323 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
324 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
325 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
326 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
327 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
328 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
329 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
330 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
331 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
332 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
333 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
334 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
335 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
336 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
337 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
338 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
339 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
340 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
341 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
342 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
343 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
344 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
345 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
346 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
347 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
348 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
349 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
350 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
351 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
352 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
353 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
354 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
355 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
356 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
357 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
358 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
359 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
360 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
361 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
362 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
363 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
364 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
365 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
366 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
367 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
368 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
369 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
370 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
371 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
372 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
373 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
374 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
375 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
376 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
377 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
378 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
379 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
380 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
381 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
382 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
383 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
384 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
385 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
386 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
387 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
388 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
389 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
390 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
391 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
392 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
393 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
394 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
395 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
396 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
397 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
398 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
399 (micromips_opcodes): New declaration.
400 (bfd_micromips_num_opcodes): Likewise.
402 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
404 * mips.h (INSN_TRAP): Rename to...
405 (INSN_NO_DELAY_SLOT): ... this.
406 (INSN_SYNC): Remove macro.
408 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
410 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
411 a duplicate of AVR_ISA_SPM.
413 2011-07-01 Nick Clifton <nickc@redhat.com>
415 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
417 2011-06-18 Robin Getz <robin.getz@analog.com>
419 * bfin.h (is_macmod_signed): New func
421 2011-06-18 Mike Frysinger <vapier@gentoo.org>
423 * bfin.h (is_macmod_pmove): Add missing space before func args.
424 (is_macmod_hmove): Likewise.
426 2011-06-13 Walter Lee <walt@tilera.com>
428 * tilegx.h: New file.
429 * tilepro.h: New file.
431 2011-05-31 Paul Brook <paul@codesourcery.com>
433 * arm.h (ARM_ARCH_V7R_IDIV): Define.
435 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
437 * s390.h: Replace S390_OPERAND_REG_EVEN with
438 S390_OPERAND_REG_PAIR.
440 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
442 * s390.h: Add S390_OPCODE_REG_EVEN flag.
444 2011-04-18 Julian Brown <julian@codesourcery.com>
446 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
448 2011-04-11 Dan McDonald <dan@wellkeeper.com>
451 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
453 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
455 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
456 New instruction set flags.
457 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
459 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
461 * mips.h (M_PREF_AB): New enum value.
463 2011-02-12 Mike Frysinger <vapier@gentoo.org>
465 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
467 (is_macmod_pmove, is_macmod_hmove): New functions.
469 2011-02-11 Mike Frysinger <vapier@gentoo.org>
471 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
473 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
475 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
476 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
478 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
481 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
484 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
487 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
489 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
491 * mips.h: Update commentary after last commit.
493 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
495 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
496 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
497 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
499 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
501 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
503 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
505 * mips.h: Fix previous commit.
507 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
509 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
510 (INSN_LOONGSON_3A): Clear bit 31.
512 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
515 * arm.h (ARM_AEXT_V6M_ONLY): New define.
516 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
517 (ARM_ARCH_V6M_ONLY): New define.
519 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
521 * mips.h (INSN_LOONGSON_3A): Defined.
522 (CPU_LOONGSON_3A): Defined.
523 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
525 2010-10-09 Matt Rice <ratmice@gmail.com>
527 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
528 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
530 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
532 * arm.h (ARM_EXT_VIRT): New define.
533 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
534 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
537 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
539 * arm.h (ARM_AEXT_ADIV): New define.
540 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
542 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
544 * arm.h (ARM_EXT_OS): New define.
545 (ARM_AEXT_V6SM): Likewise.
546 (ARM_ARCH_V6SM): Likewise.
548 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
550 * arm.h (ARM_EXT_MP): Add.
551 (ARM_ARCH_V7A_MP): Likewise.
553 2010-09-22 Mike Frysinger <vapier@gentoo.org>
555 * bfin.h: Declare pseudoChr structs/defines.
557 2010-09-21 Mike Frysinger <vapier@gentoo.org>
559 * bfin.h: Strip trailing whitespace.
561 2010-07-29 DJ Delorie <dj@redhat.com>
563 * rx.h (RX_Operand_Type): Add TwoReg.
564 (RX_Opcode_ID): Remove ediv and ediv2.
566 2010-07-27 DJ Delorie <dj@redhat.com>
568 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
570 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
571 Ina Pandit <ina.pandit@kpitcummins.com>
573 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
574 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
575 PROCESSOR_V850E2_ALL.
576 Remove PROCESSOR_V850EA support.
577 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
578 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
579 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
580 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
581 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
582 V850_OPERAND_PERCENT.
583 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
585 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
588 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
590 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
591 (MIPS16_INSN_BRANCH): Rename to...
592 (MIPS16_INSN_COND_BRANCH): ... this.
594 2010-07-03 Alan Modra <amodra@gmail.com>
596 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
597 Renumber other PPC_OPCODE defines.
599 2010-07-03 Alan Modra <amodra@gmail.com>
601 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
603 2010-06-29 Alan Modra <amodra@gmail.com>
605 * maxq.h: Delete file.
607 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
609 * ppc.h (PPC_OPCODE_E500): Define.
611 2010-05-26 Catherine Moore <clm@codesourcery.com>
613 * opcode/mips.h (INSN_MIPS16): Remove.
615 2010-04-21 Joseph Myers <joseph@codesourcery.com>
617 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
619 2010-04-15 Nick Clifton <nickc@redhat.com>
621 * alpha.h: Update copyright notice to use GPLv3.
627 * convex.h: Likewise.
641 * m68hc11.h: Likewise.
647 * mn10200.h: Likewise.
648 * mn10300.h: Likewise.
649 * msp430.h: Likewise.
660 * score-datadep.h: Likewise.
661 * score-inst.h: Likewise.
663 * spu-insns.h: Likewise.
667 * tic54x.h: Likewise.
672 2010-03-25 Joseph Myers <joseph@codesourcery.com>
674 * tic6x-control-registers.h, tic6x-insn-formats.h,
675 tic6x-opcode-table.h, tic6x.h: New.
677 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
679 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
681 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
683 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
685 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
687 * ia64.h (ia64_find_opcode): Remove argument name.
688 (ia64_find_next_opcode): Likewise.
689 (ia64_dis_opcode): Likewise.
690 (ia64_free_opcode): Likewise.
691 (ia64_find_dependency): Likewise.
693 2009-11-22 Doug Evans <dje@sebabeach.org>
695 * cgen.h: Include bfd_stdint.h.
696 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
698 2009-11-18 Paul Brook <paul@codesourcery.com>
700 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
702 2009-11-17 Paul Brook <paul@codesourcery.com>
703 Daniel Jacobowitz <dan@codesourcery.com>
705 * arm.h (ARM_EXT_V6_DSP): Define.
706 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
707 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
709 2009-11-04 DJ Delorie <dj@redhat.com>
711 * rx.h (rx_decode_opcode) (mvtipl): Add.
712 (mvtcp, mvfcp, opecp): Remove.
714 2009-11-02 Paul Brook <paul@codesourcery.com>
716 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
717 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
718 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
719 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
720 FPU_ARCH_NEON_VFP_V4): Define.
722 2009-10-23 Doug Evans <dje@sebabeach.org>
724 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
725 * cgen.h: Update. Improve multi-inclusion macro name.
727 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
729 * ppc.h (PPC_OPCODE_476): Define.
731 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
733 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
735 2009-09-29 DJ Delorie <dj@redhat.com>
739 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
741 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
743 2009-09-21 Ben Elliston <bje@au.ibm.com>
745 * ppc.h (PPC_OPCODE_PPCA2): New.
747 2009-09-05 Martin Thuresson <martin@mtme.org>
749 * ia64.h (struct ia64_operand): Renamed member class to op_class.
751 2009-08-29 Martin Thuresson <martin@mtme.org>
753 * tic30.h (template): Rename type template to
754 insn_template. Updated code to use new name.
755 * tic54x.h (template): Rename type template to
758 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
760 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
762 2009-06-11 Anthony Green <green@moxielogic.com>
764 * moxie.h (MOXIE_F3_PCREL): Define.
765 (moxie_form3_opc_info): Grow.
767 2009-06-06 Anthony Green <green@moxielogic.com>
769 * moxie.h (MOXIE_F1_M): Define.
771 2009-04-15 Anthony Green <green@moxielogic.com>
775 2009-04-06 DJ Delorie <dj@redhat.com>
777 * h8300.h: Add relaxation attributes to MOVA opcodes.
779 2009-03-10 Alan Modra <amodra@bigpond.net.au>
781 * ppc.h (ppc_parse_cpu): Declare.
783 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
785 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
786 and _IMM11 for mbitclr and mbitset.
787 * score-datadep.h: Update dependency information.
789 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
791 * ppc.h (PPC_OPCODE_POWER7): New.
793 2009-02-06 Doug Evans <dje@google.com>
795 * i386.h: Add comment regarding sse* insns and prefixes.
797 2009-02-03 Sandip Matte <sandip@rmicorp.com>
799 * mips.h (INSN_XLR): Define.
800 (INSN_CHIP_MASK): Update.
802 (OPCODE_IS_MEMBER): Update.
803 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
805 2009-01-28 Doug Evans <dje@google.com>
807 * opcode/i386.h: Add multiple inclusion protection.
808 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
809 (EDI_REG_NUM): New macros.
810 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
811 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
812 (REX_PREFIX_P): New macro.
814 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
816 * ppc.h (struct powerpc_opcode): New field "deprecated".
817 (PPC_OPCODE_NOPOWER4): Delete.
819 2008-11-28 Joshua Kinard <kumba@gentoo.org>
821 * mips.h: Define CPU_R14000, CPU_R16000.
822 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
824 2008-11-18 Catherine Moore <clm@codesourcery.com>
826 * arm.h (FPU_NEON_FP16): New.
827 (FPU_ARCH_NEON_FP16): New.
829 2008-11-06 Chao-ying Fu <fu@mips.com>
831 * mips.h: Doucument '1' for 5-bit sync type.
833 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
835 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
838 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
840 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
842 2008-07-30 Michael J. Eager <eager@eagercon.com>
844 * ppc.h (PPC_OPCODE_405): Define.
845 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
847 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
849 * ppc.h (ppc_cpu_t): New typedef.
850 (struct powerpc_opcode <flags>): Use it.
851 (struct powerpc_operand <insert, extract>): Likewise.
852 (struct powerpc_macro <flags>): Likewise.
854 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
856 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
857 Update comment before MIPS16 field descriptors to mention MIPS16.
858 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
860 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
861 New bit masks and shift counts for cins and exts.
863 * mips.h: Document new field descriptors +Q.
864 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
866 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
868 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
869 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
871 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
873 * ppc.h: (PPC_OPCODE_E500MC): New.
875 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
877 * i386.h (MAX_OPERANDS): Set to 5.
878 (MAX_MNEM_SIZE): Changed to 20.
880 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
882 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
884 2008-03-09 Paul Brook <paul@codesourcery.com>
886 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
888 2008-03-04 Paul Brook <paul@codesourcery.com>
890 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
891 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
892 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
894 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
895 Nick Clifton <nickc@redhat.com>
898 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
899 with a 32-bit displacement but without the top bit of the 4th byte
902 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
904 * cr16.h (cr16_num_optab): Declared.
906 2008-02-14 Hakan Ardo <hakan@debian.org>
909 * avr.h (AVR_ISA_2xxe): Define.
911 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
913 * mips.h: Update copyright.
914 (INSN_CHIP_MASK): New macro.
915 (INSN_OCTEON): New macro.
916 (CPU_OCTEON): New macro.
917 (OPCODE_IS_MEMBER): Handle Octeon instructions.
919 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
921 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
923 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
925 * avr.h (AVR_ISA_USB162): Add new opcode set.
926 (AVR_ISA_AVR3): Likewise.
928 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
930 * mips.h (INSN_LOONGSON_2E): New.
931 (INSN_LOONGSON_2F): New.
932 (CPU_LOONGSON_2E): New.
933 (CPU_LOONGSON_2F): New.
934 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
936 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
938 * mips.h (INSN_ISA*): Redefine certain values as an
939 enumeration. Update comments.
940 (mips_isa_table): New.
941 (ISA_MIPS*): Redefine to match enumeration.
942 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
945 2007-08-08 Ben Elliston <bje@au.ibm.com>
947 * ppc.h (PPC_OPCODE_PPCPS): New.
949 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
951 * m68k.h: Document j K & E.
953 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
955 * cr16.h: New file for CR16 target.
957 2007-05-02 Alan Modra <amodra@bigpond.net.au>
959 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
961 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
963 * m68k.h (mcfisa_c): New.
964 (mcfusp, mcf_mask): Adjust.
966 2007-04-20 Alan Modra <amodra@bigpond.net.au>
968 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
969 (num_powerpc_operands): Declare.
970 (PPC_OPERAND_SIGNED et al): Redefine as hex.
971 (PPC_OPERAND_PLUS1): Define.
973 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
975 * i386.h (REX_MODE64): Renamed to ...
977 (REX_EXTX): Renamed to ...
979 (REX_EXTY): Renamed to ...
981 (REX_EXTZ): Renamed to ...
984 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
986 * i386.h: Add entries from config/tc-i386.h and move tables
987 to opcodes/i386-opc.h.
989 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
991 * i386.h (FloatDR): Removed.
992 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
994 2007-03-01 Alan Modra <amodra@bigpond.net.au>
996 * spu-insns.h: Add soma double-float insns.
998 2007-02-20 Thiemo Seufer <ths@mips.com>
999 Chao-Ying Fu <fu@mips.com>
1001 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1002 (INSN_DSPR2): Add flag for DSP R2 instructions.
1003 (M_BALIGN): New macro.
1005 2007-02-14 Alan Modra <amodra@bigpond.net.au>
1007 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1008 and Seg3ShortFrom with Shortform.
1010 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1013 * i386.h (i386_optab): Put the real "test" before the pseudo
1016 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
1018 * m68k.h (m68010up): OR fido_a.
1020 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
1022 * m68k.h (fido_a): New.
1024 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
1026 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1027 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1030 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1032 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1034 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1036 * score-inst.h (enum score_insn_type): Add Insn_internal.
1038 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1039 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1040 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1041 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1042 Alan Modra <amodra@bigpond.net.au>
1044 * spu-insns.h: New file.
1047 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1049 * ppc.h (PPC_OPCODE_CELL): Define.
1051 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1053 * i386.h : Modify opcode to support for the change in POPCNT opcode
1054 in amdfam10 architecture.
1056 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1058 * i386.h: Replace CpuMNI with CpuSSSE3.
1060 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
1061 Joseph Myers <joseph@codesourcery.com>
1062 Ian Lance Taylor <ian@wasabisystems.com>
1063 Ben Elliston <bje@wasabisystems.com>
1065 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1067 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1069 * score-datadep.h: New file.
1070 * score-inst.h: New file.
1072 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1074 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1075 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1076 movdq2q and movq2dq.
1078 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1079 Michael Meissner <michael.meissner@amd.com>
1081 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1083 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1085 * i386.h (i386_optab): Add "nop" with memory reference.
1087 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1089 * i386.h (i386_optab): Update comment for 64bit NOP.
1091 2006-06-06 Ben Elliston <bje@au.ibm.com>
1092 Anton Blanchard <anton@samba.org>
1094 * ppc.h (PPC_OPCODE_POWER6): Define.
1097 2006-06-05 Thiemo Seufer <ths@mips.com>
1099 * mips.h: Improve description of MT flags.
1101 2006-05-25 Richard Sandiford <richard@codesourcery.com>
1103 * m68k.h (mcf_mask): Define.
1105 2006-05-05 Thiemo Seufer <ths@mips.com>
1106 David Ung <davidu@mips.com>
1108 * mips.h (enum): Add macro M_CACHE_AB.
1110 2006-05-04 Thiemo Seufer <ths@mips.com>
1111 Nigel Stephens <nigel@mips.com>
1112 David Ung <davidu@mips.com>
1114 * mips.h: Add INSN_SMARTMIPS define.
1116 2006-04-30 Thiemo Seufer <ths@mips.com>
1117 David Ung <davidu@mips.com>
1119 * mips.h: Defines udi bits and masks. Add description of
1120 characters which may appear in the args field of udi
1123 2006-04-26 Thiemo Seufer <ths@networkno.de>
1125 * mips.h: Improve comments describing the bitfield instruction
1128 2006-04-26 Julian Brown <julian@codesourcery.com>
1130 * arm.h (FPU_VFP_EXT_V3): Define constant.
1131 (FPU_NEON_EXT_V1): Likewise.
1132 (FPU_VFP_HARD): Update.
1133 (FPU_VFP_V3): Define macro.
1134 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1136 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
1138 * avr.h (AVR_ISA_PWMx): New.
1140 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1142 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1143 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1144 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1145 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1146 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1148 2006-03-10 Paul Brook <paul@codesourcery.com>
1150 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1152 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1154 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1155 first. Correct mask of bb "B" opcode.
1157 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1159 * i386.h (i386_optab): Support Intel Merom New Instructions.
1161 2006-02-24 Paul Brook <paul@codesourcery.com>
1163 * arm.h: Add V7 feature bits.
1165 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1167 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1169 2006-01-31 Paul Brook <paul@codesourcery.com>
1170 Richard Earnshaw <rearnsha@arm.com>
1172 * arm.h: Use ARM_CPU_FEATURE.
1173 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1174 (arm_feature_set): Change to a structure.
1175 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1176 ARM_FEATURE): New macros.
1178 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
1180 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1181 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1182 (ADD_PC_INCR_OPCODE): Don't define.
1184 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1187 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1189 2005-11-14 David Ung <davidu@mips.com>
1191 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1192 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1193 save/restore encoding of the args field.
1195 2005-10-28 Dave Brolley <brolley@redhat.com>
1197 Contribute the following changes:
1198 2005-02-16 Dave Brolley <brolley@redhat.com>
1200 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1201 cgen_isa_mask_* to cgen_bitset_*.
1204 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1206 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1207 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1208 (CGEN_CPU_TABLE): Make isas a ponter.
1210 2003-09-29 Dave Brolley <brolley@redhat.com>
1212 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1213 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1214 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1216 2002-12-13 Dave Brolley <brolley@redhat.com>
1218 * cgen.h (symcat.h): #include it.
1219 (cgen-bitset.h): #include it.
1220 (CGEN_ATTR_VALUE_TYPE): Now a union.
1221 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1222 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1223 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1224 * cgen-bitset.h: New file.
1226 2005-09-30 Catherine Moore <clm@cm00re.com>
1230 2005-10-24 Jan Beulich <jbeulich@novell.com>
1232 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1235 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1237 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1238 Add FLAG_STRICT to pa10 ftest opcode.
1240 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1242 * hppa.h (pa_opcodes): Remove lha entries.
1244 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1246 * hppa.h (FLAG_STRICT): Revise comment.
1247 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1248 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1251 2005-09-30 Catherine Moore <clm@cm00re.com>
1255 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1257 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1259 2005-09-06 Chao-ying Fu <fu@mips.com>
1261 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1262 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1264 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1265 (INSN_ASE_MASK): Update to include INSN_MT.
1266 (INSN_MT): New define for MT ASE.
1268 2005-08-25 Chao-ying Fu <fu@mips.com>
1270 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1271 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1272 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1273 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1274 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1275 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1277 (INSN_DSP): New define for DSP ASE.
1279 2005-08-18 Alan Modra <amodra@bigpond.net.au>
1283 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1285 * ppc.h (PPC_OPCODE_E300): Define.
1287 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1289 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1291 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1294 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1297 2005-07-27 Jan Beulich <jbeulich@novell.com>
1299 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1300 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1301 Add movq-s as 64-bit variants of movd-s.
1303 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1305 * hppa.h: Fix punctuation in comment.
1307 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1308 implicit space-register addressing. Set space-register bits on opcodes
1309 using implicit space-register addressing. Add various missing pa20
1310 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1311 space-register addressing. Use "fE" instead of "fe" in various
1314 2005-07-18 Jan Beulich <jbeulich@novell.com>
1316 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1318 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1320 * i386.h (i386_optab): Support Intel VMX Instructions.
1322 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1324 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1326 2005-07-05 Jan Beulich <jbeulich@novell.com>
1328 * i386.h (i386_optab): Add new insns.
1330 2005-07-01 Nick Clifton <nickc@redhat.com>
1332 * sparc.h: Add typedefs to structure declarations.
1334 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1337 * i386.h (i386_optab): Update comments for 64bit addressing on
1338 mov. Allow 64bit addressing for mov and movq.
1340 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1342 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1343 respectively, in various floating-point load and store patterns.
1345 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1347 * hppa.h (FLAG_STRICT): Correct comment.
1348 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1349 PA 2.0 mneumonics when equivalent. Entries with cache control
1350 completers now require PA 1.1. Adjust whitespace.
1352 2005-05-19 Anton Blanchard <anton@samba.org>
1354 * ppc.h (PPC_OPCODE_POWER5): Define.
1356 2005-05-10 Nick Clifton <nickc@redhat.com>
1358 * Update the address and phone number of the FSF organization in
1359 the GPL notices in the following files:
1360 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1361 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1362 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1363 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1364 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1365 tic54x.h, tic80.h, v850.h, vax.h
1367 2005-05-09 Jan Beulich <jbeulich@novell.com>
1369 * i386.h (i386_optab): Add ht and hnt.
1371 2005-04-18 Mark Kettenis <kettenis@gnu.org>
1373 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1374 Add xcrypt-ctr. Provide aliases without hyphens.
1376 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1378 Moved from ../ChangeLog
1380 2005-04-12 Paul Brook <paul@codesourcery.com>
1381 * m88k.h: Rename psr macros to avoid conflicts.
1383 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1384 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1385 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1386 and ARM_ARCH_V6ZKT2.
1388 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1389 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1390 Remove redundant instruction types.
1391 (struct argument): X_op - new field.
1392 (struct cst4_entry): Remove.
1393 (no_op_insn): Declare.
1395 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1396 * crx.h (enum argtype): Rename types, remove unused types.
1398 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1399 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1400 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1401 (enum operand_type): Rearrange operands, edit comments.
1402 replace us<N> with ui<N> for unsigned immediate.
1403 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1404 displacements (respectively).
1405 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1406 (instruction type): Add NO_TYPE_INS.
1407 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1408 (operand_entry): New field - 'flags'.
1409 (operand flags): New.
1411 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1412 * crx.h (operand_type): Remove redundant types i3, i4,
1414 Add new unsigned immediate types us3, us4, us5, us16.
1416 2005-04-12 Mark Kettenis <kettenis@gnu.org>
1418 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1419 adjust them accordingly.
1421 2005-04-01 Jan Beulich <jbeulich@novell.com>
1423 * i386.h (i386_optab): Add rdtscp.
1425 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1427 * i386.h (i386_optab): Don't allow the `l' suffix for moving
1428 between memory and segment register. Allow movq for moving between
1429 general-purpose register and segment register.
1431 2005-02-09 Jan Beulich <jbeulich@novell.com>
1434 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1435 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1438 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1440 * m68k.h (m68008, m68ec030, m68882): Remove.
1442 (cpu_m68k, cpu_cf): New.
1443 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1444 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1446 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
1448 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1449 * cgen.h (enum cgen_parse_operand_type): Add
1450 CGEN_PARSE_OPERAND_SYMBOLIC.
1452 2005-01-21 Fred Fish <fnf@specifixinc.com>
1454 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1455 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1456 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1458 2005-01-19 Fred Fish <fnf@specifixinc.com>
1460 * mips.h (struct mips_opcode): Add new pinfo2 member.
1461 (INSN_ALIAS): New define for opcode table entries that are
1462 specific instances of another entry, such as 'move' for an 'or'
1463 with a zero operand.
1464 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1465 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1467 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1469 * mips.h (CPU_RM9000): Define.
1470 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1472 2004-11-25 Jan Beulich <jbeulich@novell.com>
1474 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1475 to/from test registers are illegal in 64-bit mode. Add missing
1476 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1477 (previously one had to explicitly encode a rex64 prefix). Re-enable
1478 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1479 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1481 2004-11-23 Jan Beulich <jbeulich@novell.com>
1483 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1484 available only with SSE2. Change the MMX additions introduced by SSE
1485 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1486 instructions by their now designated identifier (since combining i686
1487 and 3DNow! does not really imply 3DNow!A).
1489 2004-11-19 Alan Modra <amodra@bigpond.net.au>
1491 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1492 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1494 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1495 Vineet Sharma <vineets@noida.hcltech.com>
1497 * maxq.h: New file: Disassembly information for the maxq port.
1499 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1501 * i386.h (i386_optab): Put back "movzb".
1503 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
1505 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1506 comments. Remove member cris_ver_sim. Add members
1507 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1508 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1509 (struct cris_support_reg, struct cris_cond15): New types.
1510 (cris_conds15): Declare.
1511 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1512 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1513 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1514 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1515 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1516 SIZE_FIELD_UNSIGNED.
1518 2004-11-04 Jan Beulich <jbeulich@novell.com>
1520 * i386.h (sldx_Suf): Remove.
1521 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1522 (q_FP): Define, implying no REX64.
1523 (x_FP, sl_FP): Imply FloatMF.
1524 (i386_optab): Split reg and mem forms of moving from segment registers
1525 so that the memory forms can ignore the 16-/32-bit operand size
1526 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1527 all non-floating-point instructions. Unite 32- and 64-bit forms of
1528 movsx, movzx, and movd. Adjust floating point operations for the above
1529 changes to the *FP macros. Add DefaultSize to floating point control
1530 insns operating on larger memory ranges. Remove left over comments
1531 hinting at certain insns being Intel-syntax ones where the ones
1532 actually meant are already gone.
1534 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1536 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1539 2004-09-30 Paul Brook <paul@codesourcery.com>
1541 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1542 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1544 2004-09-11 Theodore A. Roth <troth@openavr.org>
1546 * avr.h: Add support for
1547 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1549 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1551 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1553 2004-08-24 Dmitry Diky <diwil@spec.ru>
1555 * msp430.h (msp430_opc): Add new instructions.
1556 (msp430_rcodes): Declare new instructions.
1557 (msp430_hcodes): Likewise..
1559 2004-08-13 Nick Clifton <nickc@redhat.com>
1562 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1565 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1567 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1569 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1571 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1573 2004-07-21 Jan Beulich <jbeulich@novell.com>
1575 * i386.h: Adjust instruction descriptions to better match the
1578 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
1580 * arm.h: Remove all old content. Replace with architecture defines
1581 from gas/config/tc-arm.c.
1583 2004-07-09 Andreas Schwab <schwab@suse.de>
1585 * m68k.h: Fix comment.
1587 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1591 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1593 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1595 2004-05-24 Peter Barada <peter@the-baradas.com>
1597 * m68k.h: Add 'size' to m68k_opcode.
1599 2004-05-05 Peter Barada <peter@the-baradas.com>
1601 * m68k.h: Switch from ColdFire chip name to core variant.
1603 2004-04-22 Peter Barada <peter@the-baradas.com>
1605 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1606 descriptions for new EMAC cases.
1607 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1608 handle Motorola MAC syntax.
1609 Allow disassembly of ColdFire V4e object files.
1611 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1613 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1615 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1617 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1619 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1621 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1623 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1625 * i386.h (i386_optab): Added xstore/xcrypt insns.
1627 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1629 * h8300.h (32bit ldc/stc): Add relaxing support.
1631 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1633 * h8300.h (BITOP): Pass MEMRELAX flag.
1635 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1637 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1640 For older changes see ChangeLog-9103
1642 Copyright (C) 2004-2012 Free Software Foundation, Inc.
1644 Copying and distribution of this file, with or without modification,
1645 are permitted in any medium without royalty provided the copyright
1646 notice and this notice are preserved.
1652 version-control: never