1 2011-02-11 Mike Frysinger <vapier@gentoo.org>
3 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
5 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
7 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
8 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
10 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
13 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
16 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
19 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
21 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
23 * mips.h: Update commentary after last commit.
25 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
27 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
28 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
29 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
31 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
33 * mips.h: Fix previous commit.
35 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
37 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
38 (INSN_LOONGSON_3A): Clear bit 31.
40 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
43 * arm.h (ARM_AEXT_V6M_ONLY): New define.
44 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
45 (ARM_ARCH_V6M_ONLY): New define.
47 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
49 * mips.h (INSN_LOONGSON_3A): Defined.
50 (CPU_LOONGSON_3A): Defined.
51 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
53 2010-10-09 Matt Rice <ratmice@gmail.com>
55 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
56 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
58 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
60 * arm.h (ARM_EXT_VIRT): New define.
61 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
62 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
65 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
67 * arm.h (ARM_AEXT_ADIV): New define.
68 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
70 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
72 * arm.h (ARM_EXT_OS): New define.
73 (ARM_AEXT_V6SM): Likewise.
74 (ARM_ARCH_V6SM): Likewise.
76 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
78 * arm.h (ARM_EXT_MP): Add.
79 (ARM_ARCH_V7A_MP): Likewise.
81 2010-09-22 Mike Frysinger <vapier@gentoo.org>
83 * bfin.h: Declare pseudoChr structs/defines.
85 2010-09-21 Mike Frysinger <vapier@gentoo.org>
87 * bfin.h: Strip trailing whitespace.
89 2010-07-29 DJ Delorie <dj@redhat.com>
91 * rx.h (RX_Operand_Type): Add TwoReg.
92 (RX_Opcode_ID): Remove ediv and ediv2.
94 2010-07-27 DJ Delorie <dj@redhat.com>
96 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
98 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
99 Ina Pandit <ina.pandit@kpitcummins.com>
101 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
102 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
103 PROCESSOR_V850E2_ALL.
104 Remove PROCESSOR_V850EA support.
105 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
106 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
107 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
108 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
109 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
110 V850_OPERAND_PERCENT.
111 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
113 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
116 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
118 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
119 (MIPS16_INSN_BRANCH): Rename to...
120 (MIPS16_INSN_COND_BRANCH): ... this.
122 2010-07-03 Alan Modra <amodra@gmail.com>
124 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
125 Renumber other PPC_OPCODE defines.
127 2010-07-03 Alan Modra <amodra@gmail.com>
129 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
131 2010-06-29 Alan Modra <amodra@gmail.com>
133 * maxq.h: Delete file.
135 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
137 * ppc.h (PPC_OPCODE_E500): Define.
139 2010-05-26 Catherine Moore <clm@codesourcery.com>
141 * opcode/mips.h (INSN_MIPS16): Remove.
143 2010-04-21 Joseph Myers <joseph@codesourcery.com>
145 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
147 2010-04-15 Nick Clifton <nickc@redhat.com>
149 * alpha.h: Update copyright notice to use GPLv3.
155 * convex.h: Likewise.
169 * m68hc11.h: Likewise.
175 * mn10200.h: Likewise.
176 * mn10300.h: Likewise.
177 * msp430.h: Likewise.
188 * score-datadep.h: Likewise.
189 * score-inst.h: Likewise.
191 * spu-insns.h: Likewise.
195 * tic54x.h: Likewise.
200 2010-03-25 Joseph Myers <joseph@codesourcery.com>
202 * tic6x-control-registers.h, tic6x-insn-formats.h,
203 tic6x-opcode-table.h, tic6x.h: New.
205 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
207 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
209 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
211 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
213 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
215 * ia64.h (ia64_find_opcode): Remove argument name.
216 (ia64_find_next_opcode): Likewise.
217 (ia64_dis_opcode): Likewise.
218 (ia64_free_opcode): Likewise.
219 (ia64_find_dependency): Likewise.
221 2009-11-22 Doug Evans <dje@sebabeach.org>
223 * cgen.h: Include bfd_stdint.h.
224 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
226 2009-11-18 Paul Brook <paul@codesourcery.com>
228 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
230 2009-11-17 Paul Brook <paul@codesourcery.com>
231 Daniel Jacobowitz <dan@codesourcery.com>
233 * arm.h (ARM_EXT_V6_DSP): Define.
234 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
235 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
237 2009-11-04 DJ Delorie <dj@redhat.com>
239 * rx.h (rx_decode_opcode) (mvtipl): Add.
240 (mvtcp, mvfcp, opecp): Remove.
242 2009-11-02 Paul Brook <paul@codesourcery.com>
244 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
245 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
246 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
247 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
248 FPU_ARCH_NEON_VFP_V4): Define.
250 2009-10-23 Doug Evans <dje@sebabeach.org>
252 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
253 * cgen.h: Update. Improve multi-inclusion macro name.
255 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
257 * ppc.h (PPC_OPCODE_476): Define.
259 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
261 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
263 2009-09-29 DJ Delorie <dj@redhat.com>
267 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
269 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
271 2009-09-21 Ben Elliston <bje@au.ibm.com>
273 * ppc.h (PPC_OPCODE_PPCA2): New.
275 2009-09-05 Martin Thuresson <martin@mtme.org>
277 * ia64.h (struct ia64_operand): Renamed member class to op_class.
279 2009-08-29 Martin Thuresson <martin@mtme.org>
281 * tic30.h (template): Rename type template to
282 insn_template. Updated code to use new name.
283 * tic54x.h (template): Rename type template to
286 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
288 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
290 2009-06-11 Anthony Green <green@moxielogic.com>
292 * moxie.h (MOXIE_F3_PCREL): Define.
293 (moxie_form3_opc_info): Grow.
295 2009-06-06 Anthony Green <green@moxielogic.com>
297 * moxie.h (MOXIE_F1_M): Define.
299 2009-04-15 Anthony Green <green@moxielogic.com>
303 2009-04-06 DJ Delorie <dj@redhat.com>
305 * h8300.h: Add relaxation attributes to MOVA opcodes.
307 2009-03-10 Alan Modra <amodra@bigpond.net.au>
309 * ppc.h (ppc_parse_cpu): Declare.
311 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
313 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
314 and _IMM11 for mbitclr and mbitset.
315 * score-datadep.h: Update dependency information.
317 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
319 * ppc.h (PPC_OPCODE_POWER7): New.
321 2009-02-06 Doug Evans <dje@google.com>
323 * i386.h: Add comment regarding sse* insns and prefixes.
325 2009-02-03 Sandip Matte <sandip@rmicorp.com>
327 * mips.h (INSN_XLR): Define.
328 (INSN_CHIP_MASK): Update.
330 (OPCODE_IS_MEMBER): Update.
331 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
333 2009-01-28 Doug Evans <dje@google.com>
335 * opcode/i386.h: Add multiple inclusion protection.
336 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
337 (EDI_REG_NUM): New macros.
338 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
339 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
340 (REX_PREFIX_P): New macro.
342 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
344 * ppc.h (struct powerpc_opcode): New field "deprecated".
345 (PPC_OPCODE_NOPOWER4): Delete.
347 2008-11-28 Joshua Kinard <kumba@gentoo.org>
349 * mips.h: Define CPU_R14000, CPU_R16000.
350 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
352 2008-11-18 Catherine Moore <clm@codesourcery.com>
354 * arm.h (FPU_NEON_FP16): New.
355 (FPU_ARCH_NEON_FP16): New.
357 2008-11-06 Chao-ying Fu <fu@mips.com>
359 * mips.h: Doucument '1' for 5-bit sync type.
361 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
363 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
366 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
368 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
370 2008-07-30 Michael J. Eager <eager@eagercon.com>
372 * ppc.h (PPC_OPCODE_405): Define.
373 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
375 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
377 * ppc.h (ppc_cpu_t): New typedef.
378 (struct powerpc_opcode <flags>): Use it.
379 (struct powerpc_operand <insert, extract>): Likewise.
380 (struct powerpc_macro <flags>): Likewise.
382 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
384 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
385 Update comment before MIPS16 field descriptors to mention MIPS16.
386 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
388 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
389 New bit masks and shift counts for cins and exts.
391 * mips.h: Document new field descriptors +Q.
392 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
394 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
396 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
397 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
399 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
401 * ppc.h: (PPC_OPCODE_E500MC): New.
403 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
405 * i386.h (MAX_OPERANDS): Set to 5.
406 (MAX_MNEM_SIZE): Changed to 20.
408 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
410 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
412 2008-03-09 Paul Brook <paul@codesourcery.com>
414 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
416 2008-03-04 Paul Brook <paul@codesourcery.com>
418 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
419 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
420 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
422 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
423 Nick Clifton <nickc@redhat.com>
426 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
427 with a 32-bit displacement but without the top bit of the 4th byte
430 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
432 * cr16.h (cr16_num_optab): Declared.
434 2008-02-14 Hakan Ardo <hakan@debian.org>
437 * avr.h (AVR_ISA_2xxe): Define.
439 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
441 * mips.h: Update copyright.
442 (INSN_CHIP_MASK): New macro.
443 (INSN_OCTEON): New macro.
444 (CPU_OCTEON): New macro.
445 (OPCODE_IS_MEMBER): Handle Octeon instructions.
447 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
449 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
451 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
453 * avr.h (AVR_ISA_USB162): Add new opcode set.
454 (AVR_ISA_AVR3): Likewise.
456 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
458 * mips.h (INSN_LOONGSON_2E): New.
459 (INSN_LOONGSON_2F): New.
460 (CPU_LOONGSON_2E): New.
461 (CPU_LOONGSON_2F): New.
462 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
464 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
466 * mips.h (INSN_ISA*): Redefine certain values as an
467 enumeration. Update comments.
468 (mips_isa_table): New.
469 (ISA_MIPS*): Redefine to match enumeration.
470 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
473 2007-08-08 Ben Elliston <bje@au.ibm.com>
475 * ppc.h (PPC_OPCODE_PPCPS): New.
477 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
479 * m68k.h: Document j K & E.
481 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
483 * cr16.h: New file for CR16 target.
485 2007-05-02 Alan Modra <amodra@bigpond.net.au>
487 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
489 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
491 * m68k.h (mcfisa_c): New.
492 (mcfusp, mcf_mask): Adjust.
494 2007-04-20 Alan Modra <amodra@bigpond.net.au>
496 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
497 (num_powerpc_operands): Declare.
498 (PPC_OPERAND_SIGNED et al): Redefine as hex.
499 (PPC_OPERAND_PLUS1): Define.
501 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
503 * i386.h (REX_MODE64): Renamed to ...
505 (REX_EXTX): Renamed to ...
507 (REX_EXTY): Renamed to ...
509 (REX_EXTZ): Renamed to ...
512 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
514 * i386.h: Add entries from config/tc-i386.h and move tables
515 to opcodes/i386-opc.h.
517 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
519 * i386.h (FloatDR): Removed.
520 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
522 2007-03-01 Alan Modra <amodra@bigpond.net.au>
524 * spu-insns.h: Add soma double-float insns.
526 2007-02-20 Thiemo Seufer <ths@mips.com>
527 Chao-Ying Fu <fu@mips.com>
529 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
530 (INSN_DSPR2): Add flag for DSP R2 instructions.
531 (M_BALIGN): New macro.
533 2007-02-14 Alan Modra <amodra@bigpond.net.au>
535 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
536 and Seg3ShortFrom with Shortform.
538 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
541 * i386.h (i386_optab): Put the real "test" before the pseudo
544 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
546 * m68k.h (m68010up): OR fido_a.
548 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
550 * m68k.h (fido_a): New.
552 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
554 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
555 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
558 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
560 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
562 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
564 * score-inst.h (enum score_insn_type): Add Insn_internal.
566 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
567 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
568 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
569 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
570 Alan Modra <amodra@bigpond.net.au>
572 * spu-insns.h: New file.
575 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
577 * ppc.h (PPC_OPCODE_CELL): Define.
579 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
581 * i386.h : Modify opcode to support for the change in POPCNT opcode
582 in amdfam10 architecture.
584 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
586 * i386.h: Replace CpuMNI with CpuSSSE3.
588 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
589 Joseph Myers <joseph@codesourcery.com>
590 Ian Lance Taylor <ian@wasabisystems.com>
591 Ben Elliston <bje@wasabisystems.com>
593 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
595 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
597 * score-datadep.h: New file.
598 * score-inst.h: New file.
600 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
602 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
603 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
606 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
607 Michael Meissner <michael.meissner@amd.com>
609 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
611 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
613 * i386.h (i386_optab): Add "nop" with memory reference.
615 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
617 * i386.h (i386_optab): Update comment for 64bit NOP.
619 2006-06-06 Ben Elliston <bje@au.ibm.com>
620 Anton Blanchard <anton@samba.org>
622 * ppc.h (PPC_OPCODE_POWER6): Define.
625 2006-06-05 Thiemo Seufer <ths@mips.com>
627 * mips.h: Improve description of MT flags.
629 2006-05-25 Richard Sandiford <richard@codesourcery.com>
631 * m68k.h (mcf_mask): Define.
633 2006-05-05 Thiemo Seufer <ths@mips.com>
634 David Ung <davidu@mips.com>
636 * mips.h (enum): Add macro M_CACHE_AB.
638 2006-05-04 Thiemo Seufer <ths@mips.com>
639 Nigel Stephens <nigel@mips.com>
640 David Ung <davidu@mips.com>
642 * mips.h: Add INSN_SMARTMIPS define.
644 2006-04-30 Thiemo Seufer <ths@mips.com>
645 David Ung <davidu@mips.com>
647 * mips.h: Defines udi bits and masks. Add description of
648 characters which may appear in the args field of udi
651 2006-04-26 Thiemo Seufer <ths@networkno.de>
653 * mips.h: Improve comments describing the bitfield instruction
656 2006-04-26 Julian Brown <julian@codesourcery.com>
658 * arm.h (FPU_VFP_EXT_V3): Define constant.
659 (FPU_NEON_EXT_V1): Likewise.
660 (FPU_VFP_HARD): Update.
661 (FPU_VFP_V3): Define macro.
662 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
664 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
666 * avr.h (AVR_ISA_PWMx): New.
668 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
670 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
671 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
672 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
673 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
674 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
676 2006-03-10 Paul Brook <paul@codesourcery.com>
678 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
680 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
682 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
683 first. Correct mask of bb "B" opcode.
685 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
687 * i386.h (i386_optab): Support Intel Merom New Instructions.
689 2006-02-24 Paul Brook <paul@codesourcery.com>
691 * arm.h: Add V7 feature bits.
693 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
695 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
697 2006-01-31 Paul Brook <paul@codesourcery.com>
698 Richard Earnshaw <rearnsha@arm.com>
700 * arm.h: Use ARM_CPU_FEATURE.
701 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
702 (arm_feature_set): Change to a structure.
703 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
704 ARM_FEATURE): New macros.
706 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
708 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
709 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
710 (ADD_PC_INCR_OPCODE): Don't define.
712 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
715 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
717 2005-11-14 David Ung <davidu@mips.com>
719 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
720 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
721 save/restore encoding of the args field.
723 2005-10-28 Dave Brolley <brolley@redhat.com>
725 Contribute the following changes:
726 2005-02-16 Dave Brolley <brolley@redhat.com>
728 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
729 cgen_isa_mask_* to cgen_bitset_*.
732 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
734 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
735 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
736 (CGEN_CPU_TABLE): Make isas a ponter.
738 2003-09-29 Dave Brolley <brolley@redhat.com>
740 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
741 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
742 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
744 2002-12-13 Dave Brolley <brolley@redhat.com>
746 * cgen.h (symcat.h): #include it.
747 (cgen-bitset.h): #include it.
748 (CGEN_ATTR_VALUE_TYPE): Now a union.
749 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
750 (CGEN_ATTR_ENTRY): 'value' now unsigned.
751 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
752 * cgen-bitset.h: New file.
754 2005-09-30 Catherine Moore <clm@cm00re.com>
758 2005-10-24 Jan Beulich <jbeulich@novell.com>
760 * ia64.h (enum ia64_opnd): Move memory operand out of set of
763 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
765 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
766 Add FLAG_STRICT to pa10 ftest opcode.
768 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
770 * hppa.h (pa_opcodes): Remove lha entries.
772 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
774 * hppa.h (FLAG_STRICT): Revise comment.
775 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
776 before corresponding pa11 opcodes. Add strict pa10 register-immediate
779 2005-09-30 Catherine Moore <clm@cm00re.com>
783 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
785 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
787 2005-09-06 Chao-ying Fu <fu@mips.com>
789 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
790 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
792 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
793 (INSN_ASE_MASK): Update to include INSN_MT.
794 (INSN_MT): New define for MT ASE.
796 2005-08-25 Chao-ying Fu <fu@mips.com>
798 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
799 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
800 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
801 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
802 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
803 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
805 (INSN_DSP): New define for DSP ASE.
807 2005-08-18 Alan Modra <amodra@bigpond.net.au>
811 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
813 * ppc.h (PPC_OPCODE_E300): Define.
815 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
817 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
819 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
822 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
825 2005-07-27 Jan Beulich <jbeulich@novell.com>
827 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
828 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
829 Add movq-s as 64-bit variants of movd-s.
831 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
833 * hppa.h: Fix punctuation in comment.
835 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
836 implicit space-register addressing. Set space-register bits on opcodes
837 using implicit space-register addressing. Add various missing pa20
838 long-immediate opcodes. Remove various opcodes using implicit 3-bit
839 space-register addressing. Use "fE" instead of "fe" in various
842 2005-07-18 Jan Beulich <jbeulich@novell.com>
844 * i386.h (i386_optab): Operands of aam and aad are unsigned.
846 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
848 * i386.h (i386_optab): Support Intel VMX Instructions.
850 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
852 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
854 2005-07-05 Jan Beulich <jbeulich@novell.com>
856 * i386.h (i386_optab): Add new insns.
858 2005-07-01 Nick Clifton <nickc@redhat.com>
860 * sparc.h: Add typedefs to structure declarations.
862 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
865 * i386.h (i386_optab): Update comments for 64bit addressing on
866 mov. Allow 64bit addressing for mov and movq.
868 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
870 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
871 respectively, in various floating-point load and store patterns.
873 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
875 * hppa.h (FLAG_STRICT): Correct comment.
876 (pa_opcodes): Update load and store entries to allow both PA 1.X and
877 PA 2.0 mneumonics when equivalent. Entries with cache control
878 completers now require PA 1.1. Adjust whitespace.
880 2005-05-19 Anton Blanchard <anton@samba.org>
882 * ppc.h (PPC_OPCODE_POWER5): Define.
884 2005-05-10 Nick Clifton <nickc@redhat.com>
886 * Update the address and phone number of the FSF organization in
887 the GPL notices in the following files:
888 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
889 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
890 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
891 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
892 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
893 tic54x.h, tic80.h, v850.h, vax.h
895 2005-05-09 Jan Beulich <jbeulich@novell.com>
897 * i386.h (i386_optab): Add ht and hnt.
899 2005-04-18 Mark Kettenis <kettenis@gnu.org>
901 * i386.h: Insert hyphens into selected VIA PadLock extensions.
902 Add xcrypt-ctr. Provide aliases without hyphens.
904 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
906 Moved from ../ChangeLog
908 2005-04-12 Paul Brook <paul@codesourcery.com>
909 * m88k.h: Rename psr macros to avoid conflicts.
911 2005-03-12 Zack Weinberg <zack@codesourcery.com>
912 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
913 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
916 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
917 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
918 Remove redundant instruction types.
919 (struct argument): X_op - new field.
920 (struct cst4_entry): Remove.
921 (no_op_insn): Declare.
923 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
924 * crx.h (enum argtype): Rename types, remove unused types.
926 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
927 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
928 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
929 (enum operand_type): Rearrange operands, edit comments.
930 replace us<N> with ui<N> for unsigned immediate.
931 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
932 displacements (respectively).
933 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
934 (instruction type): Add NO_TYPE_INS.
935 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
936 (operand_entry): New field - 'flags'.
937 (operand flags): New.
939 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
940 * crx.h (operand_type): Remove redundant types i3, i4,
942 Add new unsigned immediate types us3, us4, us5, us16.
944 2005-04-12 Mark Kettenis <kettenis@gnu.org>
946 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
947 adjust them accordingly.
949 2005-04-01 Jan Beulich <jbeulich@novell.com>
951 * i386.h (i386_optab): Add rdtscp.
953 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
955 * i386.h (i386_optab): Don't allow the `l' suffix for moving
956 between memory and segment register. Allow movq for moving between
957 general-purpose register and segment register.
959 2005-02-09 Jan Beulich <jbeulich@novell.com>
962 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
963 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
966 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
968 * m68k.h (m68008, m68ec030, m68882): Remove.
970 (cpu_m68k, cpu_cf): New.
971 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
972 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
974 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
976 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
977 * cgen.h (enum cgen_parse_operand_type): Add
978 CGEN_PARSE_OPERAND_SYMBOLIC.
980 2005-01-21 Fred Fish <fnf@specifixinc.com>
982 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
983 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
984 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
986 2005-01-19 Fred Fish <fnf@specifixinc.com>
988 * mips.h (struct mips_opcode): Add new pinfo2 member.
989 (INSN_ALIAS): New define for opcode table entries that are
990 specific instances of another entry, such as 'move' for an 'or'
992 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
993 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
995 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
997 * mips.h (CPU_RM9000): Define.
998 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1000 2004-11-25 Jan Beulich <jbeulich@novell.com>
1002 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1003 to/from test registers are illegal in 64-bit mode. Add missing
1004 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1005 (previously one had to explicitly encode a rex64 prefix). Re-enable
1006 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1007 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1009 2004-11-23 Jan Beulich <jbeulich@novell.com>
1011 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1012 available only with SSE2. Change the MMX additions introduced by SSE
1013 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1014 instructions by their now designated identifier (since combining i686
1015 and 3DNow! does not really imply 3DNow!A).
1017 2004-11-19 Alan Modra <amodra@bigpond.net.au>
1019 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1020 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1022 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1023 Vineet Sharma <vineets@noida.hcltech.com>
1025 * maxq.h: New file: Disassembly information for the maxq port.
1027 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1029 * i386.h (i386_optab): Put back "movzb".
1031 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
1033 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1034 comments. Remove member cris_ver_sim. Add members
1035 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1036 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1037 (struct cris_support_reg, struct cris_cond15): New types.
1038 (cris_conds15): Declare.
1039 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1040 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1041 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1042 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1043 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1044 SIZE_FIELD_UNSIGNED.
1046 2004-11-04 Jan Beulich <jbeulich@novell.com>
1048 * i386.h (sldx_Suf): Remove.
1049 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1050 (q_FP): Define, implying no REX64.
1051 (x_FP, sl_FP): Imply FloatMF.
1052 (i386_optab): Split reg and mem forms of moving from segment registers
1053 so that the memory forms can ignore the 16-/32-bit operand size
1054 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1055 all non-floating-point instructions. Unite 32- and 64-bit forms of
1056 movsx, movzx, and movd. Adjust floating point operations for the above
1057 changes to the *FP macros. Add DefaultSize to floating point control
1058 insns operating on larger memory ranges. Remove left over comments
1059 hinting at certain insns being Intel-syntax ones where the ones
1060 actually meant are already gone.
1062 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1064 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1067 2004-09-30 Paul Brook <paul@codesourcery.com>
1069 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1070 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1072 2004-09-11 Theodore A. Roth <troth@openavr.org>
1074 * avr.h: Add support for
1075 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1077 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1079 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1081 2004-08-24 Dmitry Diky <diwil@spec.ru>
1083 * msp430.h (msp430_opc): Add new instructions.
1084 (msp430_rcodes): Declare new instructions.
1085 (msp430_hcodes): Likewise..
1087 2004-08-13 Nick Clifton <nickc@redhat.com>
1090 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1093 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1095 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1097 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1099 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1101 2004-07-21 Jan Beulich <jbeulich@novell.com>
1103 * i386.h: Adjust instruction descriptions to better match the
1106 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
1108 * arm.h: Remove all old content. Replace with architecture defines
1109 from gas/config/tc-arm.c.
1111 2004-07-09 Andreas Schwab <schwab@suse.de>
1113 * m68k.h: Fix comment.
1115 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1119 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1121 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1123 2004-05-24 Peter Barada <peter@the-baradas.com>
1125 * m68k.h: Add 'size' to m68k_opcode.
1127 2004-05-05 Peter Barada <peter@the-baradas.com>
1129 * m68k.h: Switch from ColdFire chip name to core variant.
1131 2004-04-22 Peter Barada <peter@the-baradas.com>
1133 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1134 descriptions for new EMAC cases.
1135 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1136 handle Motorola MAC syntax.
1137 Allow disassembly of ColdFire V4e object files.
1139 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1141 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1143 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1145 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1147 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1149 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1151 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1153 * i386.h (i386_optab): Added xstore/xcrypt insns.
1155 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1157 * h8300.h (32bit ldc/stc): Add relaxing support.
1159 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1161 * h8300.h (BITOP): Pass MEMRELAX flag.
1163 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1165 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1168 For older changes see ChangeLog-9103
1174 version-control: never