1 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
3 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
5 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
7 * ia64.h (ia64_opnd): Add new operand types.
9 2012-08-21 David S. Miller <davem@davemloft.net>
11 * sparc.h (F3F4): New macro.
13 2012-08-13 Ian Bolton <ian.bolton@arm.com>
14 Laurent Desnogues <laurent.desnogues@arm.com>
15 Jim MacArthur <jim.macarthur@arm.com>
16 Marcus Shawcroft <marcus.shawcroft@arm.com>
17 Nigel Stephens <nigel.stephens@arm.com>
18 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
19 Richard Earnshaw <rearnsha@arm.com>
20 Sofiane Naci <sofiane.naci@arm.com>
21 Tejas Belagod <tejas.belagod@arm.com>
22 Yufeng Zhang <yufeng.zhang@arm.com>
24 * aarch64.h: New file.
26 2012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
27 Maciej W. Rozycki <macro@codesourcery.com>
29 * mips.h (mips_opcode): Add the exclusions field.
30 (OPCODE_IS_MEMBER): Remove macro.
31 (cpu_is_member): New inline function.
32 (opcode_is_member): Likewise.
34 2012-07-31 Chao-Ying Fu <fu@mips.com>
35 Catherine Moore <clm@codesourcery.com>
36 Maciej W. Rozycki <macro@codesourcery.com>
38 * mips.h: Document microMIPS DSP ASE usage.
39 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
40 microMIPS DSP ASE support.
41 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
42 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
43 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
44 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
45 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
46 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
47 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
49 2012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
51 * mips.h: Fix a typo in description.
53 2012-06-07 Georg-Johann Lay <avr@gjlay.de>
55 * avr.h: (AVR_ISA_XCH): New define.
56 (AVR_ISA_XMEGA): Use it.
57 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
59 2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
61 * m68hc11.h: Add XGate definitions.
62 (struct m68hc11_opcode): Add xg_mask field.
64 2012-05-14 Catherine Moore <clm@codesourcery.com>
65 Maciej W. Rozycki <macro@codesourcery.com>
66 Rhonda Wittels <rhonda@codesourcery.com>
68 * ppc.h (PPC_OPCODE_VLE): New definition.
69 (PPC_OP_SA): New macro.
70 (PPC_OP_SE_VLE): New macro.
71 (PPC_OP): Use a variable shift amount.
72 (powerpc_operand): Update comments.
73 (PPC_OPSHIFT_INV): New macro.
74 (PPC_OPERAND_CR): Replace with...
75 (PPC_OPERAND_CR_BIT): ...this and
76 (PPC_OPERAND_CR_REG): ...this.
79 2012-05-03 Sean Keys <skeys@ipdatasys.com>
81 * xgate.h: Header file for XGATE assembler.
83 2012-04-27 David S. Miller <davem@davemloft.net>
85 * sparc.h: Document new arg code' )' for crypto RS3
88 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
89 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
90 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
91 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
92 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
93 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
94 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
95 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
96 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
97 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
98 HWCAP_CBCOND, HWCAP_CRC32): New defines.
100 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
102 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
104 2012-02-27 Alan Modra <amodra@gmail.com>
106 * crx.h (cst4_map): Update declaration.
108 2012-02-25 Walter Lee <walt@tilera.com>
110 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
112 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
113 TILEPRO_OPC_LW_TLS_SN.
115 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
117 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
118 (XRELEASE_PREFIX_OPCODE): Likewise.
120 2011-12-08 Andrew Pinski <apinski@cavium.com>
121 Adam Nemet <anemet@caviumnetworks.com>
123 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
124 (INSN_OCTEON2): New macro.
125 (CPU_OCTEON2): New macro.
126 (OPCODE_IS_MEMBER): Add Octeon2.
128 2011-11-29 Andrew Pinski <apinski@cavium.com>
130 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
131 (INSN_OCTEONP): New macro.
132 (CPU_OCTEONP): New macro.
133 (OPCODE_IS_MEMBER): Add Octeon+.
134 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
136 2011-11-01 DJ Delorie <dj@redhat.com>
140 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
142 * mips.h: Fix a typo in description.
144 2011-09-21 David S. Miller <davem@davemloft.net>
146 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
147 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
148 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
149 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
151 2011-08-09 Chao-ying Fu <fu@mips.com>
152 Maciej W. Rozycki <macro@codesourcery.com>
154 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
155 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
156 (INSN_ASE_MASK): Add the MCU bit.
157 (INSN_MCU): New macro.
158 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
159 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
161 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
163 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
164 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
165 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
166 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
167 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
168 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
169 (INSN2_READ_GPR_MMN): Likewise.
170 (INSN2_READ_FPR_D): Change the bit used.
171 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
172 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
173 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
174 (INSN2_COND_BRANCH): Likewise.
175 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
176 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
177 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
178 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
179 (INSN2_MOD_GPR_MN): Likewise.
181 2011-08-05 David S. Miller <davem@davemloft.net>
183 * sparc.h: Document new format codes '4', '5', and '('.
184 (OPF_LOW4, RS3): New macros.
186 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
188 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
189 order of flags documented.
191 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
193 * mips.h: Clarify the description of microMIPS instruction
195 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
197 2011-07-24 Chao-ying Fu <fu@mips.com>
198 Maciej W. Rozycki <macro@codesourcery.com>
200 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
201 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
202 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
203 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
204 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
205 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
206 (OP_MASK_RS3, OP_SH_RS3): Likewise.
207 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
208 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
209 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
210 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
211 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
212 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
213 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
214 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
215 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
216 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
217 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
218 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
219 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
220 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
221 (INSN_WRITE_GPR_S): New macro.
222 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
223 (INSN2_READ_FPR_D): Likewise.
224 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
225 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
226 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
227 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
228 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
229 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
230 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
231 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
232 (CPU_MICROMIPS): New macro.
233 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
234 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
235 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
236 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
237 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
238 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
239 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
240 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
241 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
242 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
243 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
244 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
245 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
246 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
247 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
248 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
249 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
250 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
251 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
252 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
253 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
254 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
255 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
256 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
257 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
258 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
259 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
260 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
261 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
262 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
263 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
264 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
265 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
266 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
267 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
268 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
269 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
270 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
271 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
272 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
273 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
274 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
275 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
276 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
277 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
278 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
279 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
280 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
281 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
282 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
283 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
284 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
285 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
286 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
287 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
288 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
289 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
290 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
291 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
292 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
293 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
294 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
295 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
296 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
297 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
298 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
299 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
300 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
301 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
302 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
303 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
304 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
305 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
306 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
307 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
308 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
309 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
310 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
311 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
312 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
313 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
314 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
315 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
316 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
317 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
318 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
319 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
320 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
321 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
322 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
323 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
324 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
325 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
326 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
327 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
328 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
329 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
330 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
331 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
332 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
333 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
334 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
335 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
336 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
337 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
338 (micromips_opcodes): New declaration.
339 (bfd_micromips_num_opcodes): Likewise.
341 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
343 * mips.h (INSN_TRAP): Rename to...
344 (INSN_NO_DELAY_SLOT): ... this.
345 (INSN_SYNC): Remove macro.
347 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
349 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
350 a duplicate of AVR_ISA_SPM.
352 2011-07-01 Nick Clifton <nickc@redhat.com>
354 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
356 2011-06-18 Robin Getz <robin.getz@analog.com>
358 * bfin.h (is_macmod_signed): New func
360 2011-06-18 Mike Frysinger <vapier@gentoo.org>
362 * bfin.h (is_macmod_pmove): Add missing space before func args.
363 (is_macmod_hmove): Likewise.
365 2011-06-13 Walter Lee <walt@tilera.com>
367 * tilegx.h: New file.
368 * tilepro.h: New file.
370 2011-05-31 Paul Brook <paul@codesourcery.com>
372 * arm.h (ARM_ARCH_V7R_IDIV): Define.
374 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
376 * s390.h: Replace S390_OPERAND_REG_EVEN with
377 S390_OPERAND_REG_PAIR.
379 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
381 * s390.h: Add S390_OPCODE_REG_EVEN flag.
383 2011-04-18 Julian Brown <julian@codesourcery.com>
385 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
387 2011-04-11 Dan McDonald <dan@wellkeeper.com>
390 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
392 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
394 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
395 New instruction set flags.
396 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
398 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
400 * mips.h (M_PREF_AB): New enum value.
402 2011-02-12 Mike Frysinger <vapier@gentoo.org>
404 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
406 (is_macmod_pmove, is_macmod_hmove): New functions.
408 2011-02-11 Mike Frysinger <vapier@gentoo.org>
410 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
412 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
414 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
415 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
417 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
420 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
423 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
426 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
428 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
430 * mips.h: Update commentary after last commit.
432 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
434 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
435 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
436 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
438 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
440 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
442 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
444 * mips.h: Fix previous commit.
446 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
448 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
449 (INSN_LOONGSON_3A): Clear bit 31.
451 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
454 * arm.h (ARM_AEXT_V6M_ONLY): New define.
455 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
456 (ARM_ARCH_V6M_ONLY): New define.
458 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
460 * mips.h (INSN_LOONGSON_3A): Defined.
461 (CPU_LOONGSON_3A): Defined.
462 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
464 2010-10-09 Matt Rice <ratmice@gmail.com>
466 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
467 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
469 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
471 * arm.h (ARM_EXT_VIRT): New define.
472 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
473 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
476 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
478 * arm.h (ARM_AEXT_ADIV): New define.
479 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
481 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
483 * arm.h (ARM_EXT_OS): New define.
484 (ARM_AEXT_V6SM): Likewise.
485 (ARM_ARCH_V6SM): Likewise.
487 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
489 * arm.h (ARM_EXT_MP): Add.
490 (ARM_ARCH_V7A_MP): Likewise.
492 2010-09-22 Mike Frysinger <vapier@gentoo.org>
494 * bfin.h: Declare pseudoChr structs/defines.
496 2010-09-21 Mike Frysinger <vapier@gentoo.org>
498 * bfin.h: Strip trailing whitespace.
500 2010-07-29 DJ Delorie <dj@redhat.com>
502 * rx.h (RX_Operand_Type): Add TwoReg.
503 (RX_Opcode_ID): Remove ediv and ediv2.
505 2010-07-27 DJ Delorie <dj@redhat.com>
507 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
509 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
510 Ina Pandit <ina.pandit@kpitcummins.com>
512 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
513 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
514 PROCESSOR_V850E2_ALL.
515 Remove PROCESSOR_V850EA support.
516 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
517 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
518 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
519 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
520 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
521 V850_OPERAND_PERCENT.
522 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
524 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
527 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
529 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
530 (MIPS16_INSN_BRANCH): Rename to...
531 (MIPS16_INSN_COND_BRANCH): ... this.
533 2010-07-03 Alan Modra <amodra@gmail.com>
535 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
536 Renumber other PPC_OPCODE defines.
538 2010-07-03 Alan Modra <amodra@gmail.com>
540 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
542 2010-06-29 Alan Modra <amodra@gmail.com>
544 * maxq.h: Delete file.
546 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
548 * ppc.h (PPC_OPCODE_E500): Define.
550 2010-05-26 Catherine Moore <clm@codesourcery.com>
552 * opcode/mips.h (INSN_MIPS16): Remove.
554 2010-04-21 Joseph Myers <joseph@codesourcery.com>
556 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
558 2010-04-15 Nick Clifton <nickc@redhat.com>
560 * alpha.h: Update copyright notice to use GPLv3.
566 * convex.h: Likewise.
580 * m68hc11.h: Likewise.
586 * mn10200.h: Likewise.
587 * mn10300.h: Likewise.
588 * msp430.h: Likewise.
599 * score-datadep.h: Likewise.
600 * score-inst.h: Likewise.
602 * spu-insns.h: Likewise.
606 * tic54x.h: Likewise.
611 2010-03-25 Joseph Myers <joseph@codesourcery.com>
613 * tic6x-control-registers.h, tic6x-insn-formats.h,
614 tic6x-opcode-table.h, tic6x.h: New.
616 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
618 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
620 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
622 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
624 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
626 * ia64.h (ia64_find_opcode): Remove argument name.
627 (ia64_find_next_opcode): Likewise.
628 (ia64_dis_opcode): Likewise.
629 (ia64_free_opcode): Likewise.
630 (ia64_find_dependency): Likewise.
632 2009-11-22 Doug Evans <dje@sebabeach.org>
634 * cgen.h: Include bfd_stdint.h.
635 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
637 2009-11-18 Paul Brook <paul@codesourcery.com>
639 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
641 2009-11-17 Paul Brook <paul@codesourcery.com>
642 Daniel Jacobowitz <dan@codesourcery.com>
644 * arm.h (ARM_EXT_V6_DSP): Define.
645 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
646 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
648 2009-11-04 DJ Delorie <dj@redhat.com>
650 * rx.h (rx_decode_opcode) (mvtipl): Add.
651 (mvtcp, mvfcp, opecp): Remove.
653 2009-11-02 Paul Brook <paul@codesourcery.com>
655 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
656 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
657 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
658 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
659 FPU_ARCH_NEON_VFP_V4): Define.
661 2009-10-23 Doug Evans <dje@sebabeach.org>
663 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
664 * cgen.h: Update. Improve multi-inclusion macro name.
666 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
668 * ppc.h (PPC_OPCODE_476): Define.
670 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
672 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
674 2009-09-29 DJ Delorie <dj@redhat.com>
678 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
680 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
682 2009-09-21 Ben Elliston <bje@au.ibm.com>
684 * ppc.h (PPC_OPCODE_PPCA2): New.
686 2009-09-05 Martin Thuresson <martin@mtme.org>
688 * ia64.h (struct ia64_operand): Renamed member class to op_class.
690 2009-08-29 Martin Thuresson <martin@mtme.org>
692 * tic30.h (template): Rename type template to
693 insn_template. Updated code to use new name.
694 * tic54x.h (template): Rename type template to
697 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
699 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
701 2009-06-11 Anthony Green <green@moxielogic.com>
703 * moxie.h (MOXIE_F3_PCREL): Define.
704 (moxie_form3_opc_info): Grow.
706 2009-06-06 Anthony Green <green@moxielogic.com>
708 * moxie.h (MOXIE_F1_M): Define.
710 2009-04-15 Anthony Green <green@moxielogic.com>
714 2009-04-06 DJ Delorie <dj@redhat.com>
716 * h8300.h: Add relaxation attributes to MOVA opcodes.
718 2009-03-10 Alan Modra <amodra@bigpond.net.au>
720 * ppc.h (ppc_parse_cpu): Declare.
722 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
724 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
725 and _IMM11 for mbitclr and mbitset.
726 * score-datadep.h: Update dependency information.
728 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
730 * ppc.h (PPC_OPCODE_POWER7): New.
732 2009-02-06 Doug Evans <dje@google.com>
734 * i386.h: Add comment regarding sse* insns and prefixes.
736 2009-02-03 Sandip Matte <sandip@rmicorp.com>
738 * mips.h (INSN_XLR): Define.
739 (INSN_CHIP_MASK): Update.
741 (OPCODE_IS_MEMBER): Update.
742 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
744 2009-01-28 Doug Evans <dje@google.com>
746 * opcode/i386.h: Add multiple inclusion protection.
747 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
748 (EDI_REG_NUM): New macros.
749 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
750 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
751 (REX_PREFIX_P): New macro.
753 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
755 * ppc.h (struct powerpc_opcode): New field "deprecated".
756 (PPC_OPCODE_NOPOWER4): Delete.
758 2008-11-28 Joshua Kinard <kumba@gentoo.org>
760 * mips.h: Define CPU_R14000, CPU_R16000.
761 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
763 2008-11-18 Catherine Moore <clm@codesourcery.com>
765 * arm.h (FPU_NEON_FP16): New.
766 (FPU_ARCH_NEON_FP16): New.
768 2008-11-06 Chao-ying Fu <fu@mips.com>
770 * mips.h: Doucument '1' for 5-bit sync type.
772 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
774 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
777 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
779 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
781 2008-07-30 Michael J. Eager <eager@eagercon.com>
783 * ppc.h (PPC_OPCODE_405): Define.
784 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
786 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
788 * ppc.h (ppc_cpu_t): New typedef.
789 (struct powerpc_opcode <flags>): Use it.
790 (struct powerpc_operand <insert, extract>): Likewise.
791 (struct powerpc_macro <flags>): Likewise.
793 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
795 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
796 Update comment before MIPS16 field descriptors to mention MIPS16.
797 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
799 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
800 New bit masks and shift counts for cins and exts.
802 * mips.h: Document new field descriptors +Q.
803 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
805 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
807 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
808 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
810 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
812 * ppc.h: (PPC_OPCODE_E500MC): New.
814 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
816 * i386.h (MAX_OPERANDS): Set to 5.
817 (MAX_MNEM_SIZE): Changed to 20.
819 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
821 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
823 2008-03-09 Paul Brook <paul@codesourcery.com>
825 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
827 2008-03-04 Paul Brook <paul@codesourcery.com>
829 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
830 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
831 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
833 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
834 Nick Clifton <nickc@redhat.com>
837 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
838 with a 32-bit displacement but without the top bit of the 4th byte
841 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
843 * cr16.h (cr16_num_optab): Declared.
845 2008-02-14 Hakan Ardo <hakan@debian.org>
848 * avr.h (AVR_ISA_2xxe): Define.
850 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
852 * mips.h: Update copyright.
853 (INSN_CHIP_MASK): New macro.
854 (INSN_OCTEON): New macro.
855 (CPU_OCTEON): New macro.
856 (OPCODE_IS_MEMBER): Handle Octeon instructions.
858 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
860 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
862 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
864 * avr.h (AVR_ISA_USB162): Add new opcode set.
865 (AVR_ISA_AVR3): Likewise.
867 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
869 * mips.h (INSN_LOONGSON_2E): New.
870 (INSN_LOONGSON_2F): New.
871 (CPU_LOONGSON_2E): New.
872 (CPU_LOONGSON_2F): New.
873 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
875 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
877 * mips.h (INSN_ISA*): Redefine certain values as an
878 enumeration. Update comments.
879 (mips_isa_table): New.
880 (ISA_MIPS*): Redefine to match enumeration.
881 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
884 2007-08-08 Ben Elliston <bje@au.ibm.com>
886 * ppc.h (PPC_OPCODE_PPCPS): New.
888 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
890 * m68k.h: Document j K & E.
892 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
894 * cr16.h: New file for CR16 target.
896 2007-05-02 Alan Modra <amodra@bigpond.net.au>
898 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
900 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
902 * m68k.h (mcfisa_c): New.
903 (mcfusp, mcf_mask): Adjust.
905 2007-04-20 Alan Modra <amodra@bigpond.net.au>
907 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
908 (num_powerpc_operands): Declare.
909 (PPC_OPERAND_SIGNED et al): Redefine as hex.
910 (PPC_OPERAND_PLUS1): Define.
912 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
914 * i386.h (REX_MODE64): Renamed to ...
916 (REX_EXTX): Renamed to ...
918 (REX_EXTY): Renamed to ...
920 (REX_EXTZ): Renamed to ...
923 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
925 * i386.h: Add entries from config/tc-i386.h and move tables
926 to opcodes/i386-opc.h.
928 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
930 * i386.h (FloatDR): Removed.
931 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
933 2007-03-01 Alan Modra <amodra@bigpond.net.au>
935 * spu-insns.h: Add soma double-float insns.
937 2007-02-20 Thiemo Seufer <ths@mips.com>
938 Chao-Ying Fu <fu@mips.com>
940 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
941 (INSN_DSPR2): Add flag for DSP R2 instructions.
942 (M_BALIGN): New macro.
944 2007-02-14 Alan Modra <amodra@bigpond.net.au>
946 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
947 and Seg3ShortFrom with Shortform.
949 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
952 * i386.h (i386_optab): Put the real "test" before the pseudo
955 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
957 * m68k.h (m68010up): OR fido_a.
959 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
961 * m68k.h (fido_a): New.
963 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
965 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
966 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
969 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
971 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
973 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
975 * score-inst.h (enum score_insn_type): Add Insn_internal.
977 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
978 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
979 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
980 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
981 Alan Modra <amodra@bigpond.net.au>
983 * spu-insns.h: New file.
986 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
988 * ppc.h (PPC_OPCODE_CELL): Define.
990 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
992 * i386.h : Modify opcode to support for the change in POPCNT opcode
993 in amdfam10 architecture.
995 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
997 * i386.h: Replace CpuMNI with CpuSSSE3.
999 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
1000 Joseph Myers <joseph@codesourcery.com>
1001 Ian Lance Taylor <ian@wasabisystems.com>
1002 Ben Elliston <bje@wasabisystems.com>
1004 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1006 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1008 * score-datadep.h: New file.
1009 * score-inst.h: New file.
1011 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1013 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1014 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1015 movdq2q and movq2dq.
1017 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1018 Michael Meissner <michael.meissner@amd.com>
1020 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1022 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1024 * i386.h (i386_optab): Add "nop" with memory reference.
1026 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1028 * i386.h (i386_optab): Update comment for 64bit NOP.
1030 2006-06-06 Ben Elliston <bje@au.ibm.com>
1031 Anton Blanchard <anton@samba.org>
1033 * ppc.h (PPC_OPCODE_POWER6): Define.
1036 2006-06-05 Thiemo Seufer <ths@mips.com>
1038 * mips.h: Improve description of MT flags.
1040 2006-05-25 Richard Sandiford <richard@codesourcery.com>
1042 * m68k.h (mcf_mask): Define.
1044 2006-05-05 Thiemo Seufer <ths@mips.com>
1045 David Ung <davidu@mips.com>
1047 * mips.h (enum): Add macro M_CACHE_AB.
1049 2006-05-04 Thiemo Seufer <ths@mips.com>
1050 Nigel Stephens <nigel@mips.com>
1051 David Ung <davidu@mips.com>
1053 * mips.h: Add INSN_SMARTMIPS define.
1055 2006-04-30 Thiemo Seufer <ths@mips.com>
1056 David Ung <davidu@mips.com>
1058 * mips.h: Defines udi bits and masks. Add description of
1059 characters which may appear in the args field of udi
1062 2006-04-26 Thiemo Seufer <ths@networkno.de>
1064 * mips.h: Improve comments describing the bitfield instruction
1067 2006-04-26 Julian Brown <julian@codesourcery.com>
1069 * arm.h (FPU_VFP_EXT_V3): Define constant.
1070 (FPU_NEON_EXT_V1): Likewise.
1071 (FPU_VFP_HARD): Update.
1072 (FPU_VFP_V3): Define macro.
1073 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1075 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
1077 * avr.h (AVR_ISA_PWMx): New.
1079 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1081 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1082 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1083 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1084 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1085 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1087 2006-03-10 Paul Brook <paul@codesourcery.com>
1089 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1091 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1093 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1094 first. Correct mask of bb "B" opcode.
1096 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1098 * i386.h (i386_optab): Support Intel Merom New Instructions.
1100 2006-02-24 Paul Brook <paul@codesourcery.com>
1102 * arm.h: Add V7 feature bits.
1104 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1106 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1108 2006-01-31 Paul Brook <paul@codesourcery.com>
1109 Richard Earnshaw <rearnsha@arm.com>
1111 * arm.h: Use ARM_CPU_FEATURE.
1112 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1113 (arm_feature_set): Change to a structure.
1114 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1115 ARM_FEATURE): New macros.
1117 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
1119 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1120 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1121 (ADD_PC_INCR_OPCODE): Don't define.
1123 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1126 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1128 2005-11-14 David Ung <davidu@mips.com>
1130 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1131 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1132 save/restore encoding of the args field.
1134 2005-10-28 Dave Brolley <brolley@redhat.com>
1136 Contribute the following changes:
1137 2005-02-16 Dave Brolley <brolley@redhat.com>
1139 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1140 cgen_isa_mask_* to cgen_bitset_*.
1143 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1145 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1146 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1147 (CGEN_CPU_TABLE): Make isas a ponter.
1149 2003-09-29 Dave Brolley <brolley@redhat.com>
1151 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1152 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1153 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1155 2002-12-13 Dave Brolley <brolley@redhat.com>
1157 * cgen.h (symcat.h): #include it.
1158 (cgen-bitset.h): #include it.
1159 (CGEN_ATTR_VALUE_TYPE): Now a union.
1160 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1161 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1162 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1163 * cgen-bitset.h: New file.
1165 2005-09-30 Catherine Moore <clm@cm00re.com>
1169 2005-10-24 Jan Beulich <jbeulich@novell.com>
1171 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1174 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1176 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1177 Add FLAG_STRICT to pa10 ftest opcode.
1179 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1181 * hppa.h (pa_opcodes): Remove lha entries.
1183 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1185 * hppa.h (FLAG_STRICT): Revise comment.
1186 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1187 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1190 2005-09-30 Catherine Moore <clm@cm00re.com>
1194 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1196 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1198 2005-09-06 Chao-ying Fu <fu@mips.com>
1200 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1201 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1203 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1204 (INSN_ASE_MASK): Update to include INSN_MT.
1205 (INSN_MT): New define for MT ASE.
1207 2005-08-25 Chao-ying Fu <fu@mips.com>
1209 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1210 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1211 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1212 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1213 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1214 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1216 (INSN_DSP): New define for DSP ASE.
1218 2005-08-18 Alan Modra <amodra@bigpond.net.au>
1222 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1224 * ppc.h (PPC_OPCODE_E300): Define.
1226 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1228 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1230 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1233 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1236 2005-07-27 Jan Beulich <jbeulich@novell.com>
1238 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1239 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1240 Add movq-s as 64-bit variants of movd-s.
1242 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1244 * hppa.h: Fix punctuation in comment.
1246 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1247 implicit space-register addressing. Set space-register bits on opcodes
1248 using implicit space-register addressing. Add various missing pa20
1249 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1250 space-register addressing. Use "fE" instead of "fe" in various
1253 2005-07-18 Jan Beulich <jbeulich@novell.com>
1255 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1257 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1259 * i386.h (i386_optab): Support Intel VMX Instructions.
1261 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1263 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1265 2005-07-05 Jan Beulich <jbeulich@novell.com>
1267 * i386.h (i386_optab): Add new insns.
1269 2005-07-01 Nick Clifton <nickc@redhat.com>
1271 * sparc.h: Add typedefs to structure declarations.
1273 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1276 * i386.h (i386_optab): Update comments for 64bit addressing on
1277 mov. Allow 64bit addressing for mov and movq.
1279 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1281 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1282 respectively, in various floating-point load and store patterns.
1284 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1286 * hppa.h (FLAG_STRICT): Correct comment.
1287 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1288 PA 2.0 mneumonics when equivalent. Entries with cache control
1289 completers now require PA 1.1. Adjust whitespace.
1291 2005-05-19 Anton Blanchard <anton@samba.org>
1293 * ppc.h (PPC_OPCODE_POWER5): Define.
1295 2005-05-10 Nick Clifton <nickc@redhat.com>
1297 * Update the address and phone number of the FSF organization in
1298 the GPL notices in the following files:
1299 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1300 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1301 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1302 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1303 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1304 tic54x.h, tic80.h, v850.h, vax.h
1306 2005-05-09 Jan Beulich <jbeulich@novell.com>
1308 * i386.h (i386_optab): Add ht and hnt.
1310 2005-04-18 Mark Kettenis <kettenis@gnu.org>
1312 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1313 Add xcrypt-ctr. Provide aliases without hyphens.
1315 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1317 Moved from ../ChangeLog
1319 2005-04-12 Paul Brook <paul@codesourcery.com>
1320 * m88k.h: Rename psr macros to avoid conflicts.
1322 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1323 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1324 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1325 and ARM_ARCH_V6ZKT2.
1327 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1328 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1329 Remove redundant instruction types.
1330 (struct argument): X_op - new field.
1331 (struct cst4_entry): Remove.
1332 (no_op_insn): Declare.
1334 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1335 * crx.h (enum argtype): Rename types, remove unused types.
1337 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1338 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1339 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1340 (enum operand_type): Rearrange operands, edit comments.
1341 replace us<N> with ui<N> for unsigned immediate.
1342 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1343 displacements (respectively).
1344 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1345 (instruction type): Add NO_TYPE_INS.
1346 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1347 (operand_entry): New field - 'flags'.
1348 (operand flags): New.
1350 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1351 * crx.h (operand_type): Remove redundant types i3, i4,
1353 Add new unsigned immediate types us3, us4, us5, us16.
1355 2005-04-12 Mark Kettenis <kettenis@gnu.org>
1357 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1358 adjust them accordingly.
1360 2005-04-01 Jan Beulich <jbeulich@novell.com>
1362 * i386.h (i386_optab): Add rdtscp.
1364 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1366 * i386.h (i386_optab): Don't allow the `l' suffix for moving
1367 between memory and segment register. Allow movq for moving between
1368 general-purpose register and segment register.
1370 2005-02-09 Jan Beulich <jbeulich@novell.com>
1373 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1374 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1377 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1379 * m68k.h (m68008, m68ec030, m68882): Remove.
1381 (cpu_m68k, cpu_cf): New.
1382 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1383 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1385 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
1387 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1388 * cgen.h (enum cgen_parse_operand_type): Add
1389 CGEN_PARSE_OPERAND_SYMBOLIC.
1391 2005-01-21 Fred Fish <fnf@specifixinc.com>
1393 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1394 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1395 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1397 2005-01-19 Fred Fish <fnf@specifixinc.com>
1399 * mips.h (struct mips_opcode): Add new pinfo2 member.
1400 (INSN_ALIAS): New define for opcode table entries that are
1401 specific instances of another entry, such as 'move' for an 'or'
1402 with a zero operand.
1403 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1404 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1406 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1408 * mips.h (CPU_RM9000): Define.
1409 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1411 2004-11-25 Jan Beulich <jbeulich@novell.com>
1413 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1414 to/from test registers are illegal in 64-bit mode. Add missing
1415 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1416 (previously one had to explicitly encode a rex64 prefix). Re-enable
1417 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1418 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1420 2004-11-23 Jan Beulich <jbeulich@novell.com>
1422 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1423 available only with SSE2. Change the MMX additions introduced by SSE
1424 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1425 instructions by their now designated identifier (since combining i686
1426 and 3DNow! does not really imply 3DNow!A).
1428 2004-11-19 Alan Modra <amodra@bigpond.net.au>
1430 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1431 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1433 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1434 Vineet Sharma <vineets@noida.hcltech.com>
1436 * maxq.h: New file: Disassembly information for the maxq port.
1438 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1440 * i386.h (i386_optab): Put back "movzb".
1442 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
1444 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1445 comments. Remove member cris_ver_sim. Add members
1446 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1447 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1448 (struct cris_support_reg, struct cris_cond15): New types.
1449 (cris_conds15): Declare.
1450 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1451 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1452 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1453 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1454 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1455 SIZE_FIELD_UNSIGNED.
1457 2004-11-04 Jan Beulich <jbeulich@novell.com>
1459 * i386.h (sldx_Suf): Remove.
1460 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1461 (q_FP): Define, implying no REX64.
1462 (x_FP, sl_FP): Imply FloatMF.
1463 (i386_optab): Split reg and mem forms of moving from segment registers
1464 so that the memory forms can ignore the 16-/32-bit operand size
1465 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1466 all non-floating-point instructions. Unite 32- and 64-bit forms of
1467 movsx, movzx, and movd. Adjust floating point operations for the above
1468 changes to the *FP macros. Add DefaultSize to floating point control
1469 insns operating on larger memory ranges. Remove left over comments
1470 hinting at certain insns being Intel-syntax ones where the ones
1471 actually meant are already gone.
1473 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1475 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1478 2004-09-30 Paul Brook <paul@codesourcery.com>
1480 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1481 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1483 2004-09-11 Theodore A. Roth <troth@openavr.org>
1485 * avr.h: Add support for
1486 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1488 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1490 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1492 2004-08-24 Dmitry Diky <diwil@spec.ru>
1494 * msp430.h (msp430_opc): Add new instructions.
1495 (msp430_rcodes): Declare new instructions.
1496 (msp430_hcodes): Likewise..
1498 2004-08-13 Nick Clifton <nickc@redhat.com>
1501 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1504 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1506 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1508 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1510 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1512 2004-07-21 Jan Beulich <jbeulich@novell.com>
1514 * i386.h: Adjust instruction descriptions to better match the
1517 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
1519 * arm.h: Remove all old content. Replace with architecture defines
1520 from gas/config/tc-arm.c.
1522 2004-07-09 Andreas Schwab <schwab@suse.de>
1524 * m68k.h: Fix comment.
1526 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1530 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1532 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1534 2004-05-24 Peter Barada <peter@the-baradas.com>
1536 * m68k.h: Add 'size' to m68k_opcode.
1538 2004-05-05 Peter Barada <peter@the-baradas.com>
1540 * m68k.h: Switch from ColdFire chip name to core variant.
1542 2004-04-22 Peter Barada <peter@the-baradas.com>
1544 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1545 descriptions for new EMAC cases.
1546 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1547 handle Motorola MAC syntax.
1548 Allow disassembly of ColdFire V4e object files.
1550 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1552 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1554 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1556 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1558 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1560 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1562 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1564 * i386.h (i386_optab): Added xstore/xcrypt insns.
1566 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1568 * h8300.h (32bit ldc/stc): Add relaxing support.
1570 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1572 * h8300.h (BITOP): Pass MEMRELAX flag.
1574 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1576 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1579 For older changes see ChangeLog-9103
1585 version-control: never