1 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
3 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
5 (decode_mips16_operand): Declare.
7 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
9 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
10 (mips_operand, mips_int_operand, mips_mapped_int_operand)
11 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
12 (mips_pcrel_operand): New structures.
13 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
14 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
15 (decode_mips_operand, decode_micromips_operand): Declare.
17 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
19 * mips.h: Document MIPS16 "I" opcode.
21 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
23 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
24 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
25 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
26 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
27 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
28 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
29 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
30 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
31 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
32 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
33 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
34 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
35 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
37 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
40 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
42 * mips.h: Remove documentation of "[" and "]". Update documentation
43 of "k" and the MDMX formats.
45 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
47 * mips.h: Update documentation of "+s" and "+S".
49 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
51 * mips.h: Document "+i".
53 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
55 * mips.h: Remove "mi" documentation. Update "mh" documentation.
56 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
58 (INSN2_WRITE_GPR_MHI): Rename to...
59 (INSN2_WRITE_GPR_MH): ...this.
61 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
63 * mips.h: Remove documentation of "+D" and "+T".
65 2013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
67 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
68 Use "source" rather than "destination" for microMIPS "G".
70 2013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
72 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
75 2013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
77 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
79 2013-06-17 Catherine Moore <clm@codesourcery.com>
80 Maciej W. Rozycki <macro@codesourcery.com>
81 Chao-Ying Fu <fu@mips.com>
83 * mips.h (OP_SH_EVAOFFSET): Define.
84 (OP_MASK_EVAOFFSET): Define.
85 (INSN_ASE_MASK): Delete.
87 (M_CACHEE_AB, M_CACHEE_OB): New.
88 (M_LBE_OB, M_LBE_AB): New.
89 (M_LBUE_OB, M_LBUE_AB): New.
90 (M_LHE_OB, M_LHE_AB): New.
91 (M_LHUE_OB, M_LHUE_AB): New.
92 (M_LLE_AB, M_LLE_OB): New.
93 (M_LWE_OB, M_LWE_AB): New.
94 (M_LWLE_AB, M_LWLE_OB): New.
95 (M_LWRE_AB, M_LWRE_OB): New.
96 (M_PREFE_AB, M_PREFE_OB): New.
97 (M_SCE_AB, M_SCE_OB): New.
98 (M_SBE_OB, M_SBE_AB): New.
99 (M_SHE_OB, M_SHE_AB): New.
100 (M_SWE_OB, M_SWE_AB): New.
101 (M_SWLE_AB, M_SWLE_OB): New.
102 (M_SWRE_AB, M_SWRE_OB): New.
103 (MICROMIPSOP_SH_EVAOFFSET): Define.
104 (MICROMIPSOP_MASK_EVAOFFSET): Define.
106 2013-06-12 Sandra Loosemore <sandra@codesourcery.com>
108 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
110 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
112 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
114 2013-05-09 Andrew Pinski <apinski@cavium.com>
116 * mips.h (OP_MASK_CODE10): Correct definition.
117 (OP_SH_CODE10): Likewise.
118 Add a comment that "+J" is used now for OP_*CODE10.
119 (INSN_ASE_MASK): Update.
120 (INSN_VIRT): New macro.
121 (INSN_VIRT64): New macro
123 2013-05-02 Nick Clifton <nickc@redhat.com>
125 * msp430.h: Add patterns for MSP430X instructions.
127 2013-04-06 David S. Miller <davem@davemloft.net>
129 * sparc.h (F_PREFERRED): Define.
130 (F_PREF_ALIAS): Define.
132 2013-04-03 Nick Clifton <nickc@redhat.com>
134 * v850.h (V850_INVERSE_PCREL): Define.
136 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
139 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
141 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
144 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
146 * tic6xc-opcode-table.h: Add 16-bit insns.
147 * tic6x.h: Add support for 16-bit insns.
149 2013-03-21 Michael Schewe <michael.schewe@gmx.net>
151 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
152 and mov.b/w/l Rs,@(d:32,ERd).
154 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
157 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
158 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
159 tic6x_operand_xregpair operand coding type.
160 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
161 opcode field, usu ORXREGD1324 for the src2 operand and remove the
164 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
167 * tic6x.h (enum tic6x_coding_method): Add
168 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
169 separately the msb and lsb of a register pair. This is needed to
170 encode the opcodes in the same way as TI assembler does.
171 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
172 and rsqrdp opcodes to use the new field coding types.
174 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
176 * arm.h (CRC_EXT_ARMV8): New constant.
177 (ARCH_CRC_ARMV8): New macro.
179 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
181 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
183 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
184 Andrew Jenner <andrew@codesourcery.com>
186 Based on patches from Altera Corporation.
190 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
192 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
194 2013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
197 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
199 2013-01-24 Nick Clifton <nickc@redhat.com>
201 * v850.h: Add e3v5 support.
203 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
205 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
207 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
209 * ppc.h (PPC_OPCODE_POWER8): New define.
210 (PPC_OPCODE_HTM): Likewise.
212 2013-01-10 Will Newton <will.newton@imgtec.com>
216 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
218 * cr16.h (make_instruction): Rename to cr16_make_instruction.
219 (match_opcode): Rename to cr16_match_opcode.
221 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
223 * mips.h: Add support for r5900 instructions including lq and sq.
225 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
227 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
228 (make_instruction,match_opcode): Added function prototypes.
229 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
231 2012-11-23 Alan Modra <amodra@gmail.com>
233 * ppc.h (ppc_parse_cpu): Update prototype.
235 2012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
237 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
238 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
240 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
242 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
244 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
246 * ia64.h (ia64_opnd): Add new operand types.
248 2012-08-21 David S. Miller <davem@davemloft.net>
250 * sparc.h (F3F4): New macro.
252 2012-08-13 Ian Bolton <ian.bolton@arm.com>
253 Laurent Desnogues <laurent.desnogues@arm.com>
254 Jim MacArthur <jim.macarthur@arm.com>
255 Marcus Shawcroft <marcus.shawcroft@arm.com>
256 Nigel Stephens <nigel.stephens@arm.com>
257 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
258 Richard Earnshaw <rearnsha@arm.com>
259 Sofiane Naci <sofiane.naci@arm.com>
260 Tejas Belagod <tejas.belagod@arm.com>
261 Yufeng Zhang <yufeng.zhang@arm.com>
263 * aarch64.h: New file.
265 2012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
266 Maciej W. Rozycki <macro@codesourcery.com>
268 * mips.h (mips_opcode): Add the exclusions field.
269 (OPCODE_IS_MEMBER): Remove macro.
270 (cpu_is_member): New inline function.
271 (opcode_is_member): Likewise.
273 2012-07-31 Chao-Ying Fu <fu@mips.com>
274 Catherine Moore <clm@codesourcery.com>
275 Maciej W. Rozycki <macro@codesourcery.com>
277 * mips.h: Document microMIPS DSP ASE usage.
278 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
279 microMIPS DSP ASE support.
280 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
281 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
282 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
283 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
284 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
285 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
286 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
288 2012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
290 * mips.h: Fix a typo in description.
292 2012-06-07 Georg-Johann Lay <avr@gjlay.de>
294 * avr.h: (AVR_ISA_XCH): New define.
295 (AVR_ISA_XMEGA): Use it.
296 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
298 2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
300 * m68hc11.h: Add XGate definitions.
301 (struct m68hc11_opcode): Add xg_mask field.
303 2012-05-14 Catherine Moore <clm@codesourcery.com>
304 Maciej W. Rozycki <macro@codesourcery.com>
305 Rhonda Wittels <rhonda@codesourcery.com>
307 * ppc.h (PPC_OPCODE_VLE): New definition.
308 (PPC_OP_SA): New macro.
309 (PPC_OP_SE_VLE): New macro.
310 (PPC_OP): Use a variable shift amount.
311 (powerpc_operand): Update comments.
312 (PPC_OPSHIFT_INV): New macro.
313 (PPC_OPERAND_CR): Replace with...
314 (PPC_OPERAND_CR_BIT): ...this and
315 (PPC_OPERAND_CR_REG): ...this.
318 2012-05-03 Sean Keys <skeys@ipdatasys.com>
320 * xgate.h: Header file for XGATE assembler.
322 2012-04-27 David S. Miller <davem@davemloft.net>
324 * sparc.h: Document new arg code' )' for crypto RS3
327 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
328 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
329 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
330 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
331 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
332 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
333 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
334 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
335 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
336 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
337 HWCAP_CBCOND, HWCAP_CRC32): New defines.
339 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
341 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
343 2012-02-27 Alan Modra <amodra@gmail.com>
345 * crx.h (cst4_map): Update declaration.
347 2012-02-25 Walter Lee <walt@tilera.com>
349 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
351 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
352 TILEPRO_OPC_LW_TLS_SN.
354 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
356 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
357 (XRELEASE_PREFIX_OPCODE): Likewise.
359 2011-12-08 Andrew Pinski <apinski@cavium.com>
360 Adam Nemet <anemet@caviumnetworks.com>
362 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
363 (INSN_OCTEON2): New macro.
364 (CPU_OCTEON2): New macro.
365 (OPCODE_IS_MEMBER): Add Octeon2.
367 2011-11-29 Andrew Pinski <apinski@cavium.com>
369 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
370 (INSN_OCTEONP): New macro.
371 (CPU_OCTEONP): New macro.
372 (OPCODE_IS_MEMBER): Add Octeon+.
373 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
375 2011-11-01 DJ Delorie <dj@redhat.com>
379 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
381 * mips.h: Fix a typo in description.
383 2011-09-21 David S. Miller <davem@davemloft.net>
385 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
386 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
387 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
388 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
390 2011-08-09 Chao-ying Fu <fu@mips.com>
391 Maciej W. Rozycki <macro@codesourcery.com>
393 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
394 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
395 (INSN_ASE_MASK): Add the MCU bit.
396 (INSN_MCU): New macro.
397 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
398 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
400 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
402 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
403 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
404 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
405 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
406 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
407 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
408 (INSN2_READ_GPR_MMN): Likewise.
409 (INSN2_READ_FPR_D): Change the bit used.
410 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
411 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
412 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
413 (INSN2_COND_BRANCH): Likewise.
414 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
415 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
416 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
417 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
418 (INSN2_MOD_GPR_MN): Likewise.
420 2011-08-05 David S. Miller <davem@davemloft.net>
422 * sparc.h: Document new format codes '4', '5', and '('.
423 (OPF_LOW4, RS3): New macros.
425 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
427 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
428 order of flags documented.
430 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
432 * mips.h: Clarify the description of microMIPS instruction
434 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
436 2011-07-24 Chao-ying Fu <fu@mips.com>
437 Maciej W. Rozycki <macro@codesourcery.com>
439 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
440 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
441 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
442 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
443 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
444 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
445 (OP_MASK_RS3, OP_SH_RS3): Likewise.
446 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
447 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
448 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
449 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
450 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
451 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
452 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
453 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
454 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
455 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
456 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
457 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
458 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
459 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
460 (INSN_WRITE_GPR_S): New macro.
461 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
462 (INSN2_READ_FPR_D): Likewise.
463 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
464 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
465 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
466 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
467 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
468 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
469 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
470 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
471 (CPU_MICROMIPS): New macro.
472 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
473 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
474 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
475 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
476 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
477 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
478 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
479 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
480 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
481 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
482 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
483 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
484 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
485 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
486 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
487 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
488 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
489 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
490 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
491 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
492 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
493 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
494 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
495 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
496 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
497 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
498 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
499 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
500 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
501 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
502 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
503 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
504 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
505 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
506 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
507 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
508 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
509 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
510 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
511 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
512 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
513 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
514 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
515 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
516 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
517 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
518 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
519 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
520 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
521 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
522 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
523 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
524 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
525 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
526 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
527 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
528 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
529 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
530 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
531 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
532 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
533 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
534 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
535 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
536 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
537 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
538 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
539 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
540 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
541 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
542 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
543 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
544 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
545 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
546 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
547 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
548 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
549 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
550 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
551 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
552 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
553 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
554 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
555 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
556 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
557 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
558 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
559 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
560 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
561 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
562 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
563 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
564 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
565 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
566 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
567 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
568 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
569 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
570 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
571 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
572 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
573 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
574 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
575 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
576 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
577 (micromips_opcodes): New declaration.
578 (bfd_micromips_num_opcodes): Likewise.
580 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
582 * mips.h (INSN_TRAP): Rename to...
583 (INSN_NO_DELAY_SLOT): ... this.
584 (INSN_SYNC): Remove macro.
586 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
588 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
589 a duplicate of AVR_ISA_SPM.
591 2011-07-01 Nick Clifton <nickc@redhat.com>
593 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
595 2011-06-18 Robin Getz <robin.getz@analog.com>
597 * bfin.h (is_macmod_signed): New func
599 2011-06-18 Mike Frysinger <vapier@gentoo.org>
601 * bfin.h (is_macmod_pmove): Add missing space before func args.
602 (is_macmod_hmove): Likewise.
604 2011-06-13 Walter Lee <walt@tilera.com>
606 * tilegx.h: New file.
607 * tilepro.h: New file.
609 2011-05-31 Paul Brook <paul@codesourcery.com>
611 * arm.h (ARM_ARCH_V7R_IDIV): Define.
613 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
615 * s390.h: Replace S390_OPERAND_REG_EVEN with
616 S390_OPERAND_REG_PAIR.
618 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
620 * s390.h: Add S390_OPCODE_REG_EVEN flag.
622 2011-04-18 Julian Brown <julian@codesourcery.com>
624 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
626 2011-04-11 Dan McDonald <dan@wellkeeper.com>
629 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
631 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
633 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
634 New instruction set flags.
635 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
637 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
639 * mips.h (M_PREF_AB): New enum value.
641 2011-02-12 Mike Frysinger <vapier@gentoo.org>
643 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
645 (is_macmod_pmove, is_macmod_hmove): New functions.
647 2011-02-11 Mike Frysinger <vapier@gentoo.org>
649 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
651 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
653 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
654 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
656 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
659 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
662 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
665 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
667 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
669 * mips.h: Update commentary after last commit.
671 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
673 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
674 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
675 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
677 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
679 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
681 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
683 * mips.h: Fix previous commit.
685 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
687 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
688 (INSN_LOONGSON_3A): Clear bit 31.
690 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
693 * arm.h (ARM_AEXT_V6M_ONLY): New define.
694 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
695 (ARM_ARCH_V6M_ONLY): New define.
697 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
699 * mips.h (INSN_LOONGSON_3A): Defined.
700 (CPU_LOONGSON_3A): Defined.
701 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
703 2010-10-09 Matt Rice <ratmice@gmail.com>
705 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
706 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
708 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
710 * arm.h (ARM_EXT_VIRT): New define.
711 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
712 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
715 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
717 * arm.h (ARM_AEXT_ADIV): New define.
718 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
720 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
722 * arm.h (ARM_EXT_OS): New define.
723 (ARM_AEXT_V6SM): Likewise.
724 (ARM_ARCH_V6SM): Likewise.
726 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
728 * arm.h (ARM_EXT_MP): Add.
729 (ARM_ARCH_V7A_MP): Likewise.
731 2010-09-22 Mike Frysinger <vapier@gentoo.org>
733 * bfin.h: Declare pseudoChr structs/defines.
735 2010-09-21 Mike Frysinger <vapier@gentoo.org>
737 * bfin.h: Strip trailing whitespace.
739 2010-07-29 DJ Delorie <dj@redhat.com>
741 * rx.h (RX_Operand_Type): Add TwoReg.
742 (RX_Opcode_ID): Remove ediv and ediv2.
744 2010-07-27 DJ Delorie <dj@redhat.com>
746 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
748 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
749 Ina Pandit <ina.pandit@kpitcummins.com>
751 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
752 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
753 PROCESSOR_V850E2_ALL.
754 Remove PROCESSOR_V850EA support.
755 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
756 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
757 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
758 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
759 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
760 V850_OPERAND_PERCENT.
761 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
763 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
766 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
768 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
769 (MIPS16_INSN_BRANCH): Rename to...
770 (MIPS16_INSN_COND_BRANCH): ... this.
772 2010-07-03 Alan Modra <amodra@gmail.com>
774 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
775 Renumber other PPC_OPCODE defines.
777 2010-07-03 Alan Modra <amodra@gmail.com>
779 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
781 2010-06-29 Alan Modra <amodra@gmail.com>
783 * maxq.h: Delete file.
785 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
787 * ppc.h (PPC_OPCODE_E500): Define.
789 2010-05-26 Catherine Moore <clm@codesourcery.com>
791 * opcode/mips.h (INSN_MIPS16): Remove.
793 2010-04-21 Joseph Myers <joseph@codesourcery.com>
795 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
797 2010-04-15 Nick Clifton <nickc@redhat.com>
799 * alpha.h: Update copyright notice to use GPLv3.
805 * convex.h: Likewise.
819 * m68hc11.h: Likewise.
825 * mn10200.h: Likewise.
826 * mn10300.h: Likewise.
827 * msp430.h: Likewise.
838 * score-datadep.h: Likewise.
839 * score-inst.h: Likewise.
841 * spu-insns.h: Likewise.
845 * tic54x.h: Likewise.
850 2010-03-25 Joseph Myers <joseph@codesourcery.com>
852 * tic6x-control-registers.h, tic6x-insn-formats.h,
853 tic6x-opcode-table.h, tic6x.h: New.
855 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
857 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
859 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
861 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
863 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
865 * ia64.h (ia64_find_opcode): Remove argument name.
866 (ia64_find_next_opcode): Likewise.
867 (ia64_dis_opcode): Likewise.
868 (ia64_free_opcode): Likewise.
869 (ia64_find_dependency): Likewise.
871 2009-11-22 Doug Evans <dje@sebabeach.org>
873 * cgen.h: Include bfd_stdint.h.
874 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
876 2009-11-18 Paul Brook <paul@codesourcery.com>
878 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
880 2009-11-17 Paul Brook <paul@codesourcery.com>
881 Daniel Jacobowitz <dan@codesourcery.com>
883 * arm.h (ARM_EXT_V6_DSP): Define.
884 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
885 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
887 2009-11-04 DJ Delorie <dj@redhat.com>
889 * rx.h (rx_decode_opcode) (mvtipl): Add.
890 (mvtcp, mvfcp, opecp): Remove.
892 2009-11-02 Paul Brook <paul@codesourcery.com>
894 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
895 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
896 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
897 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
898 FPU_ARCH_NEON_VFP_V4): Define.
900 2009-10-23 Doug Evans <dje@sebabeach.org>
902 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
903 * cgen.h: Update. Improve multi-inclusion macro name.
905 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
907 * ppc.h (PPC_OPCODE_476): Define.
909 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
911 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
913 2009-09-29 DJ Delorie <dj@redhat.com>
917 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
919 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
921 2009-09-21 Ben Elliston <bje@au.ibm.com>
923 * ppc.h (PPC_OPCODE_PPCA2): New.
925 2009-09-05 Martin Thuresson <martin@mtme.org>
927 * ia64.h (struct ia64_operand): Renamed member class to op_class.
929 2009-08-29 Martin Thuresson <martin@mtme.org>
931 * tic30.h (template): Rename type template to
932 insn_template. Updated code to use new name.
933 * tic54x.h (template): Rename type template to
936 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
938 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
940 2009-06-11 Anthony Green <green@moxielogic.com>
942 * moxie.h (MOXIE_F3_PCREL): Define.
943 (moxie_form3_opc_info): Grow.
945 2009-06-06 Anthony Green <green@moxielogic.com>
947 * moxie.h (MOXIE_F1_M): Define.
949 2009-04-15 Anthony Green <green@moxielogic.com>
953 2009-04-06 DJ Delorie <dj@redhat.com>
955 * h8300.h: Add relaxation attributes to MOVA opcodes.
957 2009-03-10 Alan Modra <amodra@bigpond.net.au>
959 * ppc.h (ppc_parse_cpu): Declare.
961 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
963 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
964 and _IMM11 for mbitclr and mbitset.
965 * score-datadep.h: Update dependency information.
967 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
969 * ppc.h (PPC_OPCODE_POWER7): New.
971 2009-02-06 Doug Evans <dje@google.com>
973 * i386.h: Add comment regarding sse* insns and prefixes.
975 2009-02-03 Sandip Matte <sandip@rmicorp.com>
977 * mips.h (INSN_XLR): Define.
978 (INSN_CHIP_MASK): Update.
980 (OPCODE_IS_MEMBER): Update.
981 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
983 2009-01-28 Doug Evans <dje@google.com>
985 * opcode/i386.h: Add multiple inclusion protection.
986 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
987 (EDI_REG_NUM): New macros.
988 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
989 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
990 (REX_PREFIX_P): New macro.
992 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
994 * ppc.h (struct powerpc_opcode): New field "deprecated".
995 (PPC_OPCODE_NOPOWER4): Delete.
997 2008-11-28 Joshua Kinard <kumba@gentoo.org>
999 * mips.h: Define CPU_R14000, CPU_R16000.
1000 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
1002 2008-11-18 Catherine Moore <clm@codesourcery.com>
1004 * arm.h (FPU_NEON_FP16): New.
1005 (FPU_ARCH_NEON_FP16): New.
1007 2008-11-06 Chao-ying Fu <fu@mips.com>
1009 * mips.h: Doucument '1' for 5-bit sync type.
1011 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1013 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1016 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1018 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1020 2008-07-30 Michael J. Eager <eager@eagercon.com>
1022 * ppc.h (PPC_OPCODE_405): Define.
1023 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1025 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1027 * ppc.h (ppc_cpu_t): New typedef.
1028 (struct powerpc_opcode <flags>): Use it.
1029 (struct powerpc_operand <insert, extract>): Likewise.
1030 (struct powerpc_macro <flags>): Likewise.
1032 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1034 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1035 Update comment before MIPS16 field descriptors to mention MIPS16.
1036 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1038 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1039 New bit masks and shift counts for cins and exts.
1041 * mips.h: Document new field descriptors +Q.
1042 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1044 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1046 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
1047 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1049 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
1051 * ppc.h: (PPC_OPCODE_E500MC): New.
1053 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1055 * i386.h (MAX_OPERANDS): Set to 5.
1056 (MAX_MNEM_SIZE): Changed to 20.
1058 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1060 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1062 2008-03-09 Paul Brook <paul@codesourcery.com>
1064 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1066 2008-03-04 Paul Brook <paul@codesourcery.com>
1068 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1069 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1070 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1072 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
1073 Nick Clifton <nickc@redhat.com>
1076 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1077 with a 32-bit displacement but without the top bit of the 4th byte
1080 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1082 * cr16.h (cr16_num_optab): Declared.
1084 2008-02-14 Hakan Ardo <hakan@debian.org>
1087 * avr.h (AVR_ISA_2xxe): Define.
1089 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1091 * mips.h: Update copyright.
1092 (INSN_CHIP_MASK): New macro.
1093 (INSN_OCTEON): New macro.
1094 (CPU_OCTEON): New macro.
1095 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1097 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1099 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1101 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1103 * avr.h (AVR_ISA_USB162): Add new opcode set.
1104 (AVR_ISA_AVR3): Likewise.
1106 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1108 * mips.h (INSN_LOONGSON_2E): New.
1109 (INSN_LOONGSON_2F): New.
1110 (CPU_LOONGSON_2E): New.
1111 (CPU_LOONGSON_2F): New.
1112 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1114 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1116 * mips.h (INSN_ISA*): Redefine certain values as an
1117 enumeration. Update comments.
1118 (mips_isa_table): New.
1119 (ISA_MIPS*): Redefine to match enumeration.
1120 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1123 2007-08-08 Ben Elliston <bje@au.ibm.com>
1125 * ppc.h (PPC_OPCODE_PPCPS): New.
1127 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1129 * m68k.h: Document j K & E.
1131 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1133 * cr16.h: New file for CR16 target.
1135 2007-05-02 Alan Modra <amodra@bigpond.net.au>
1137 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1139 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1141 * m68k.h (mcfisa_c): New.
1142 (mcfusp, mcf_mask): Adjust.
1144 2007-04-20 Alan Modra <amodra@bigpond.net.au>
1146 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1147 (num_powerpc_operands): Declare.
1148 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1149 (PPC_OPERAND_PLUS1): Define.
1151 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
1153 * i386.h (REX_MODE64): Renamed to ...
1155 (REX_EXTX): Renamed to ...
1157 (REX_EXTY): Renamed to ...
1159 (REX_EXTZ): Renamed to ...
1162 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1164 * i386.h: Add entries from config/tc-i386.h and move tables
1165 to opcodes/i386-opc.h.
1167 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1169 * i386.h (FloatDR): Removed.
1170 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1172 2007-03-01 Alan Modra <amodra@bigpond.net.au>
1174 * spu-insns.h: Add soma double-float insns.
1176 2007-02-20 Thiemo Seufer <ths@mips.com>
1177 Chao-Ying Fu <fu@mips.com>
1179 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1180 (INSN_DSPR2): Add flag for DSP R2 instructions.
1181 (M_BALIGN): New macro.
1183 2007-02-14 Alan Modra <amodra@bigpond.net.au>
1185 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1186 and Seg3ShortFrom with Shortform.
1188 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1191 * i386.h (i386_optab): Put the real "test" before the pseudo
1194 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
1196 * m68k.h (m68010up): OR fido_a.
1198 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
1200 * m68k.h (fido_a): New.
1202 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
1204 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1205 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1208 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1210 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1212 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1214 * score-inst.h (enum score_insn_type): Add Insn_internal.
1216 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1217 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1218 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1219 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1220 Alan Modra <amodra@bigpond.net.au>
1222 * spu-insns.h: New file.
1225 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1227 * ppc.h (PPC_OPCODE_CELL): Define.
1229 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1231 * i386.h : Modify opcode to support for the change in POPCNT opcode
1232 in amdfam10 architecture.
1234 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1236 * i386.h: Replace CpuMNI with CpuSSSE3.
1238 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
1239 Joseph Myers <joseph@codesourcery.com>
1240 Ian Lance Taylor <ian@wasabisystems.com>
1241 Ben Elliston <bje@wasabisystems.com>
1243 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1245 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1247 * score-datadep.h: New file.
1248 * score-inst.h: New file.
1250 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1252 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1253 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1254 movdq2q and movq2dq.
1256 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1257 Michael Meissner <michael.meissner@amd.com>
1259 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1261 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1263 * i386.h (i386_optab): Add "nop" with memory reference.
1265 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1267 * i386.h (i386_optab): Update comment for 64bit NOP.
1269 2006-06-06 Ben Elliston <bje@au.ibm.com>
1270 Anton Blanchard <anton@samba.org>
1272 * ppc.h (PPC_OPCODE_POWER6): Define.
1275 2006-06-05 Thiemo Seufer <ths@mips.com>
1277 * mips.h: Improve description of MT flags.
1279 2006-05-25 Richard Sandiford <richard@codesourcery.com>
1281 * m68k.h (mcf_mask): Define.
1283 2006-05-05 Thiemo Seufer <ths@mips.com>
1284 David Ung <davidu@mips.com>
1286 * mips.h (enum): Add macro M_CACHE_AB.
1288 2006-05-04 Thiemo Seufer <ths@mips.com>
1289 Nigel Stephens <nigel@mips.com>
1290 David Ung <davidu@mips.com>
1292 * mips.h: Add INSN_SMARTMIPS define.
1294 2006-04-30 Thiemo Seufer <ths@mips.com>
1295 David Ung <davidu@mips.com>
1297 * mips.h: Defines udi bits and masks. Add description of
1298 characters which may appear in the args field of udi
1301 2006-04-26 Thiemo Seufer <ths@networkno.de>
1303 * mips.h: Improve comments describing the bitfield instruction
1306 2006-04-26 Julian Brown <julian@codesourcery.com>
1308 * arm.h (FPU_VFP_EXT_V3): Define constant.
1309 (FPU_NEON_EXT_V1): Likewise.
1310 (FPU_VFP_HARD): Update.
1311 (FPU_VFP_V3): Define macro.
1312 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1314 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
1316 * avr.h (AVR_ISA_PWMx): New.
1318 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1320 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1321 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1322 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1323 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1324 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1326 2006-03-10 Paul Brook <paul@codesourcery.com>
1328 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1330 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1332 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1333 first. Correct mask of bb "B" opcode.
1335 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1337 * i386.h (i386_optab): Support Intel Merom New Instructions.
1339 2006-02-24 Paul Brook <paul@codesourcery.com>
1341 * arm.h: Add V7 feature bits.
1343 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1345 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1347 2006-01-31 Paul Brook <paul@codesourcery.com>
1348 Richard Earnshaw <rearnsha@arm.com>
1350 * arm.h: Use ARM_CPU_FEATURE.
1351 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1352 (arm_feature_set): Change to a structure.
1353 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1354 ARM_FEATURE): New macros.
1356 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
1358 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1359 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1360 (ADD_PC_INCR_OPCODE): Don't define.
1362 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1365 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1367 2005-11-14 David Ung <davidu@mips.com>
1369 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1370 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1371 save/restore encoding of the args field.
1373 2005-10-28 Dave Brolley <brolley@redhat.com>
1375 Contribute the following changes:
1376 2005-02-16 Dave Brolley <brolley@redhat.com>
1378 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1379 cgen_isa_mask_* to cgen_bitset_*.
1382 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1384 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1385 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1386 (CGEN_CPU_TABLE): Make isas a ponter.
1388 2003-09-29 Dave Brolley <brolley@redhat.com>
1390 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1391 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1392 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1394 2002-12-13 Dave Brolley <brolley@redhat.com>
1396 * cgen.h (symcat.h): #include it.
1397 (cgen-bitset.h): #include it.
1398 (CGEN_ATTR_VALUE_TYPE): Now a union.
1399 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1400 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1401 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1402 * cgen-bitset.h: New file.
1404 2005-09-30 Catherine Moore <clm@cm00re.com>
1408 2005-10-24 Jan Beulich <jbeulich@novell.com>
1410 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1413 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1415 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1416 Add FLAG_STRICT to pa10 ftest opcode.
1418 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1420 * hppa.h (pa_opcodes): Remove lha entries.
1422 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1424 * hppa.h (FLAG_STRICT): Revise comment.
1425 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1426 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1429 2005-09-30 Catherine Moore <clm@cm00re.com>
1433 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1435 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1437 2005-09-06 Chao-ying Fu <fu@mips.com>
1439 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1440 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1442 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1443 (INSN_ASE_MASK): Update to include INSN_MT.
1444 (INSN_MT): New define for MT ASE.
1446 2005-08-25 Chao-ying Fu <fu@mips.com>
1448 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1449 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1450 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1451 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1452 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1453 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1455 (INSN_DSP): New define for DSP ASE.
1457 2005-08-18 Alan Modra <amodra@bigpond.net.au>
1461 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1463 * ppc.h (PPC_OPCODE_E300): Define.
1465 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1467 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1469 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1472 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1475 2005-07-27 Jan Beulich <jbeulich@novell.com>
1477 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1478 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1479 Add movq-s as 64-bit variants of movd-s.
1481 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1483 * hppa.h: Fix punctuation in comment.
1485 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1486 implicit space-register addressing. Set space-register bits on opcodes
1487 using implicit space-register addressing. Add various missing pa20
1488 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1489 space-register addressing. Use "fE" instead of "fe" in various
1492 2005-07-18 Jan Beulich <jbeulich@novell.com>
1494 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1496 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1498 * i386.h (i386_optab): Support Intel VMX Instructions.
1500 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1502 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1504 2005-07-05 Jan Beulich <jbeulich@novell.com>
1506 * i386.h (i386_optab): Add new insns.
1508 2005-07-01 Nick Clifton <nickc@redhat.com>
1510 * sparc.h: Add typedefs to structure declarations.
1512 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1515 * i386.h (i386_optab): Update comments for 64bit addressing on
1516 mov. Allow 64bit addressing for mov and movq.
1518 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1520 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1521 respectively, in various floating-point load and store patterns.
1523 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1525 * hppa.h (FLAG_STRICT): Correct comment.
1526 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1527 PA 2.0 mneumonics when equivalent. Entries with cache control
1528 completers now require PA 1.1. Adjust whitespace.
1530 2005-05-19 Anton Blanchard <anton@samba.org>
1532 * ppc.h (PPC_OPCODE_POWER5): Define.
1534 2005-05-10 Nick Clifton <nickc@redhat.com>
1536 * Update the address and phone number of the FSF organization in
1537 the GPL notices in the following files:
1538 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1539 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1540 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1541 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1542 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1543 tic54x.h, tic80.h, v850.h, vax.h
1545 2005-05-09 Jan Beulich <jbeulich@novell.com>
1547 * i386.h (i386_optab): Add ht and hnt.
1549 2005-04-18 Mark Kettenis <kettenis@gnu.org>
1551 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1552 Add xcrypt-ctr. Provide aliases without hyphens.
1554 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1556 Moved from ../ChangeLog
1558 2005-04-12 Paul Brook <paul@codesourcery.com>
1559 * m88k.h: Rename psr macros to avoid conflicts.
1561 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1562 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1563 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1564 and ARM_ARCH_V6ZKT2.
1566 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1567 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1568 Remove redundant instruction types.
1569 (struct argument): X_op - new field.
1570 (struct cst4_entry): Remove.
1571 (no_op_insn): Declare.
1573 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1574 * crx.h (enum argtype): Rename types, remove unused types.
1576 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1577 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1578 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1579 (enum operand_type): Rearrange operands, edit comments.
1580 replace us<N> with ui<N> for unsigned immediate.
1581 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1582 displacements (respectively).
1583 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1584 (instruction type): Add NO_TYPE_INS.
1585 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1586 (operand_entry): New field - 'flags'.
1587 (operand flags): New.
1589 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1590 * crx.h (operand_type): Remove redundant types i3, i4,
1592 Add new unsigned immediate types us3, us4, us5, us16.
1594 2005-04-12 Mark Kettenis <kettenis@gnu.org>
1596 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1597 adjust them accordingly.
1599 2005-04-01 Jan Beulich <jbeulich@novell.com>
1601 * i386.h (i386_optab): Add rdtscp.
1603 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1605 * i386.h (i386_optab): Don't allow the `l' suffix for moving
1606 between memory and segment register. Allow movq for moving between
1607 general-purpose register and segment register.
1609 2005-02-09 Jan Beulich <jbeulich@novell.com>
1612 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1613 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1616 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1618 * m68k.h (m68008, m68ec030, m68882): Remove.
1620 (cpu_m68k, cpu_cf): New.
1621 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1622 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1624 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
1626 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1627 * cgen.h (enum cgen_parse_operand_type): Add
1628 CGEN_PARSE_OPERAND_SYMBOLIC.
1630 2005-01-21 Fred Fish <fnf@specifixinc.com>
1632 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1633 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1634 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1636 2005-01-19 Fred Fish <fnf@specifixinc.com>
1638 * mips.h (struct mips_opcode): Add new pinfo2 member.
1639 (INSN_ALIAS): New define for opcode table entries that are
1640 specific instances of another entry, such as 'move' for an 'or'
1641 with a zero operand.
1642 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1643 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1645 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1647 * mips.h (CPU_RM9000): Define.
1648 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1650 2004-11-25 Jan Beulich <jbeulich@novell.com>
1652 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1653 to/from test registers are illegal in 64-bit mode. Add missing
1654 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1655 (previously one had to explicitly encode a rex64 prefix). Re-enable
1656 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1657 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1659 2004-11-23 Jan Beulich <jbeulich@novell.com>
1661 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1662 available only with SSE2. Change the MMX additions introduced by SSE
1663 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1664 instructions by their now designated identifier (since combining i686
1665 and 3DNow! does not really imply 3DNow!A).
1667 2004-11-19 Alan Modra <amodra@bigpond.net.au>
1669 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1670 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1672 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1673 Vineet Sharma <vineets@noida.hcltech.com>
1675 * maxq.h: New file: Disassembly information for the maxq port.
1677 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1679 * i386.h (i386_optab): Put back "movzb".
1681 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
1683 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1684 comments. Remove member cris_ver_sim. Add members
1685 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1686 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1687 (struct cris_support_reg, struct cris_cond15): New types.
1688 (cris_conds15): Declare.
1689 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1690 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1691 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1692 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1693 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1694 SIZE_FIELD_UNSIGNED.
1696 2004-11-04 Jan Beulich <jbeulich@novell.com>
1698 * i386.h (sldx_Suf): Remove.
1699 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1700 (q_FP): Define, implying no REX64.
1701 (x_FP, sl_FP): Imply FloatMF.
1702 (i386_optab): Split reg and mem forms of moving from segment registers
1703 so that the memory forms can ignore the 16-/32-bit operand size
1704 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1705 all non-floating-point instructions. Unite 32- and 64-bit forms of
1706 movsx, movzx, and movd. Adjust floating point operations for the above
1707 changes to the *FP macros. Add DefaultSize to floating point control
1708 insns operating on larger memory ranges. Remove left over comments
1709 hinting at certain insns being Intel-syntax ones where the ones
1710 actually meant are already gone.
1712 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1714 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1717 2004-09-30 Paul Brook <paul@codesourcery.com>
1719 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1720 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1722 2004-09-11 Theodore A. Roth <troth@openavr.org>
1724 * avr.h: Add support for
1725 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1727 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1729 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1731 2004-08-24 Dmitry Diky <diwil@spec.ru>
1733 * msp430.h (msp430_opc): Add new instructions.
1734 (msp430_rcodes): Declare new instructions.
1735 (msp430_hcodes): Likewise..
1737 2004-08-13 Nick Clifton <nickc@redhat.com>
1740 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1743 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1745 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1747 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1749 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1751 2004-07-21 Jan Beulich <jbeulich@novell.com>
1753 * i386.h: Adjust instruction descriptions to better match the
1756 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
1758 * arm.h: Remove all old content. Replace with architecture defines
1759 from gas/config/tc-arm.c.
1761 2004-07-09 Andreas Schwab <schwab@suse.de>
1763 * m68k.h: Fix comment.
1765 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1769 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1771 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1773 2004-05-24 Peter Barada <peter@the-baradas.com>
1775 * m68k.h: Add 'size' to m68k_opcode.
1777 2004-05-05 Peter Barada <peter@the-baradas.com>
1779 * m68k.h: Switch from ColdFire chip name to core variant.
1781 2004-04-22 Peter Barada <peter@the-baradas.com>
1783 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1784 descriptions for new EMAC cases.
1785 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1786 handle Motorola MAC syntax.
1787 Allow disassembly of ColdFire V4e object files.
1789 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1791 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1793 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1795 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1797 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1799 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1801 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1803 * i386.h (i386_optab): Added xstore/xcrypt insns.
1805 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1807 * h8300.h (32bit ldc/stc): Add relaxing support.
1809 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1811 * h8300.h (BITOP): Pass MEMRELAX flag.
1813 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1815 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1818 For older changes see ChangeLog-9103
1820 Copyright (C) 2004-2012 Free Software Foundation, Inc.
1822 Copying and distribution of this file, with or without modification,
1823 are permitted in any medium without royalty provided the copyright
1824 notice and this notice are preserved.
1830 version-control: never