1 2013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
3 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
5 2013-06-17 Catherine Moore <clm@codesourcery.com>
6 Maciej W. Rozycki <macro@codesourcery.com>
7 Chao-Ying Fu <fu@mips.com>
9 * mips.h (OP_SH_EVAOFFSET): Define.
10 (OP_MASK_EVAOFFSET): Define.
11 (INSN_ASE_MASK): Delete.
13 (M_CACHEE_AB, M_CACHEE_OB): New.
14 (M_LBE_OB, M_LBE_AB): New.
15 (M_LBUE_OB, M_LBUE_AB): New.
16 (M_LHE_OB, M_LHE_AB): New.
17 (M_LHUE_OB, M_LHUE_AB): New.
18 (M_LLE_AB, M_LLE_OB): New.
19 (M_LWE_OB, M_LWE_AB): New.
20 (M_LWLE_AB, M_LWLE_OB): New.
21 (M_LWRE_AB, M_LWRE_OB): New.
22 (M_PREFE_AB, M_PREFE_OB): New.
23 (M_SCE_AB, M_SCE_OB): New.
24 (M_SBE_OB, M_SBE_AB): New.
25 (M_SHE_OB, M_SHE_AB): New.
26 (M_SWE_OB, M_SWE_AB): New.
27 (M_SWLE_AB, M_SWLE_OB): New.
28 (M_SWRE_AB, M_SWRE_OB): New.
29 (MICROMIPSOP_SH_EVAOFFSET): Define.
30 (MICROMIPSOP_MASK_EVAOFFSET): Define.
32 2013-06-12 Sandra Loosemore <sandra@codesourcery.com>
34 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
36 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
38 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
40 2013-05-09 Andrew Pinski <apinski@cavium.com>
42 * mips.h (OP_MASK_CODE10): Correct definition.
43 (OP_SH_CODE10): Likewise.
44 Add a comment that "+J" is used now for OP_*CODE10.
45 (INSN_ASE_MASK): Update.
46 (INSN_VIRT): New macro.
47 (INSN_VIRT64): New macro
49 2013-05-02 Nick Clifton <nickc@redhat.com>
51 * msp430.h: Add patterns for MSP430X instructions.
53 2013-04-06 David S. Miller <davem@davemloft.net>
55 * sparc.h (F_PREFERRED): Define.
56 (F_PREF_ALIAS): Define.
58 2013-04-03 Nick Clifton <nickc@redhat.com>
60 * v850.h (V850_INVERSE_PCREL): Define.
62 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
65 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
67 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
70 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
72 * tic6xc-opcode-table.h: Add 16-bit insns.
73 * tic6x.h: Add support for 16-bit insns.
75 2013-03-21 Michael Schewe <michael.schewe@gmx.net>
77 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
78 and mov.b/w/l Rs,@(d:32,ERd).
80 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
83 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
84 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
85 tic6x_operand_xregpair operand coding type.
86 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
87 opcode field, usu ORXREGD1324 for the src2 operand and remove the
90 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
93 * tic6x.h (enum tic6x_coding_method): Add
94 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
95 separately the msb and lsb of a register pair. This is needed to
96 encode the opcodes in the same way as TI assembler does.
97 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
98 and rsqrdp opcodes to use the new field coding types.
100 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
102 * arm.h (CRC_EXT_ARMV8): New constant.
103 (ARCH_CRC_ARMV8): New macro.
105 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
107 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
109 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
110 Andrew Jenner <andrew@codesourcery.com>
112 Based on patches from Altera Corporation.
116 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
118 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
120 2013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
123 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
125 2013-01-24 Nick Clifton <nickc@redhat.com>
127 * v850.h: Add e3v5 support.
129 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
131 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
133 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
135 * ppc.h (PPC_OPCODE_POWER8): New define.
136 (PPC_OPCODE_HTM): Likewise.
138 2013-01-10 Will Newton <will.newton@imgtec.com>
142 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
144 * cr16.h (make_instruction): Rename to cr16_make_instruction.
145 (match_opcode): Rename to cr16_match_opcode.
147 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
149 * mips.h: Add support for r5900 instructions including lq and sq.
151 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
153 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
154 (make_instruction,match_opcode): Added function prototypes.
155 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
157 2012-11-23 Alan Modra <amodra@gmail.com>
159 * ppc.h (ppc_parse_cpu): Update prototype.
161 2012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
163 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
164 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
166 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
168 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
170 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
172 * ia64.h (ia64_opnd): Add new operand types.
174 2012-08-21 David S. Miller <davem@davemloft.net>
176 * sparc.h (F3F4): New macro.
178 2012-08-13 Ian Bolton <ian.bolton@arm.com>
179 Laurent Desnogues <laurent.desnogues@arm.com>
180 Jim MacArthur <jim.macarthur@arm.com>
181 Marcus Shawcroft <marcus.shawcroft@arm.com>
182 Nigel Stephens <nigel.stephens@arm.com>
183 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
184 Richard Earnshaw <rearnsha@arm.com>
185 Sofiane Naci <sofiane.naci@arm.com>
186 Tejas Belagod <tejas.belagod@arm.com>
187 Yufeng Zhang <yufeng.zhang@arm.com>
189 * aarch64.h: New file.
191 2012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
192 Maciej W. Rozycki <macro@codesourcery.com>
194 * mips.h (mips_opcode): Add the exclusions field.
195 (OPCODE_IS_MEMBER): Remove macro.
196 (cpu_is_member): New inline function.
197 (opcode_is_member): Likewise.
199 2012-07-31 Chao-Ying Fu <fu@mips.com>
200 Catherine Moore <clm@codesourcery.com>
201 Maciej W. Rozycki <macro@codesourcery.com>
203 * mips.h: Document microMIPS DSP ASE usage.
204 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
205 microMIPS DSP ASE support.
206 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
207 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
208 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
209 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
210 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
211 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
212 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
214 2012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
216 * mips.h: Fix a typo in description.
218 2012-06-07 Georg-Johann Lay <avr@gjlay.de>
220 * avr.h: (AVR_ISA_XCH): New define.
221 (AVR_ISA_XMEGA): Use it.
222 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
224 2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
226 * m68hc11.h: Add XGate definitions.
227 (struct m68hc11_opcode): Add xg_mask field.
229 2012-05-14 Catherine Moore <clm@codesourcery.com>
230 Maciej W. Rozycki <macro@codesourcery.com>
231 Rhonda Wittels <rhonda@codesourcery.com>
233 * ppc.h (PPC_OPCODE_VLE): New definition.
234 (PPC_OP_SA): New macro.
235 (PPC_OP_SE_VLE): New macro.
236 (PPC_OP): Use a variable shift amount.
237 (powerpc_operand): Update comments.
238 (PPC_OPSHIFT_INV): New macro.
239 (PPC_OPERAND_CR): Replace with...
240 (PPC_OPERAND_CR_BIT): ...this and
241 (PPC_OPERAND_CR_REG): ...this.
244 2012-05-03 Sean Keys <skeys@ipdatasys.com>
246 * xgate.h: Header file for XGATE assembler.
248 2012-04-27 David S. Miller <davem@davemloft.net>
250 * sparc.h: Document new arg code' )' for crypto RS3
253 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
254 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
255 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
256 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
257 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
258 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
259 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
260 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
261 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
262 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
263 HWCAP_CBCOND, HWCAP_CRC32): New defines.
265 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
267 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
269 2012-02-27 Alan Modra <amodra@gmail.com>
271 * crx.h (cst4_map): Update declaration.
273 2012-02-25 Walter Lee <walt@tilera.com>
275 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
277 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
278 TILEPRO_OPC_LW_TLS_SN.
280 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
282 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
283 (XRELEASE_PREFIX_OPCODE): Likewise.
285 2011-12-08 Andrew Pinski <apinski@cavium.com>
286 Adam Nemet <anemet@caviumnetworks.com>
288 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
289 (INSN_OCTEON2): New macro.
290 (CPU_OCTEON2): New macro.
291 (OPCODE_IS_MEMBER): Add Octeon2.
293 2011-11-29 Andrew Pinski <apinski@cavium.com>
295 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
296 (INSN_OCTEONP): New macro.
297 (CPU_OCTEONP): New macro.
298 (OPCODE_IS_MEMBER): Add Octeon+.
299 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
301 2011-11-01 DJ Delorie <dj@redhat.com>
305 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
307 * mips.h: Fix a typo in description.
309 2011-09-21 David S. Miller <davem@davemloft.net>
311 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
312 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
313 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
314 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
316 2011-08-09 Chao-ying Fu <fu@mips.com>
317 Maciej W. Rozycki <macro@codesourcery.com>
319 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
320 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
321 (INSN_ASE_MASK): Add the MCU bit.
322 (INSN_MCU): New macro.
323 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
324 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
326 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
328 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
329 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
330 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
331 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
332 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
333 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
334 (INSN2_READ_GPR_MMN): Likewise.
335 (INSN2_READ_FPR_D): Change the bit used.
336 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
337 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
338 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
339 (INSN2_COND_BRANCH): Likewise.
340 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
341 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
342 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
343 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
344 (INSN2_MOD_GPR_MN): Likewise.
346 2011-08-05 David S. Miller <davem@davemloft.net>
348 * sparc.h: Document new format codes '4', '5', and '('.
349 (OPF_LOW4, RS3): New macros.
351 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
353 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
354 order of flags documented.
356 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
358 * mips.h: Clarify the description of microMIPS instruction
360 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
362 2011-07-24 Chao-ying Fu <fu@mips.com>
363 Maciej W. Rozycki <macro@codesourcery.com>
365 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
366 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
367 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
368 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
369 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
370 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
371 (OP_MASK_RS3, OP_SH_RS3): Likewise.
372 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
373 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
374 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
375 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
376 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
377 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
378 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
379 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
380 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
381 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
382 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
383 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
384 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
385 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
386 (INSN_WRITE_GPR_S): New macro.
387 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
388 (INSN2_READ_FPR_D): Likewise.
389 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
390 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
391 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
392 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
393 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
394 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
395 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
396 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
397 (CPU_MICROMIPS): New macro.
398 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
399 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
400 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
401 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
402 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
403 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
404 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
405 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
406 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
407 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
408 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
409 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
410 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
411 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
412 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
413 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
414 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
415 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
416 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
417 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
418 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
419 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
420 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
421 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
422 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
423 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
424 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
425 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
426 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
427 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
428 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
429 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
430 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
431 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
432 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
433 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
434 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
435 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
436 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
437 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
438 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
439 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
440 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
441 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
442 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
443 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
444 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
445 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
446 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
447 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
448 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
449 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
450 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
451 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
452 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
453 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
454 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
455 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
456 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
457 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
458 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
459 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
460 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
461 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
462 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
463 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
464 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
465 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
466 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
467 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
468 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
469 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
470 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
471 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
472 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
473 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
474 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
475 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
476 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
477 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
478 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
479 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
480 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
481 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
482 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
483 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
484 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
485 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
486 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
487 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
488 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
489 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
490 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
491 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
492 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
493 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
494 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
495 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
496 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
497 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
498 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
499 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
500 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
501 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
502 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
503 (micromips_opcodes): New declaration.
504 (bfd_micromips_num_opcodes): Likewise.
506 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
508 * mips.h (INSN_TRAP): Rename to...
509 (INSN_NO_DELAY_SLOT): ... this.
510 (INSN_SYNC): Remove macro.
512 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
514 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
515 a duplicate of AVR_ISA_SPM.
517 2011-07-01 Nick Clifton <nickc@redhat.com>
519 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
521 2011-06-18 Robin Getz <robin.getz@analog.com>
523 * bfin.h (is_macmod_signed): New func
525 2011-06-18 Mike Frysinger <vapier@gentoo.org>
527 * bfin.h (is_macmod_pmove): Add missing space before func args.
528 (is_macmod_hmove): Likewise.
530 2011-06-13 Walter Lee <walt@tilera.com>
532 * tilegx.h: New file.
533 * tilepro.h: New file.
535 2011-05-31 Paul Brook <paul@codesourcery.com>
537 * arm.h (ARM_ARCH_V7R_IDIV): Define.
539 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
541 * s390.h: Replace S390_OPERAND_REG_EVEN with
542 S390_OPERAND_REG_PAIR.
544 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
546 * s390.h: Add S390_OPCODE_REG_EVEN flag.
548 2011-04-18 Julian Brown <julian@codesourcery.com>
550 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
552 2011-04-11 Dan McDonald <dan@wellkeeper.com>
555 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
557 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
559 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
560 New instruction set flags.
561 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
563 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
565 * mips.h (M_PREF_AB): New enum value.
567 2011-02-12 Mike Frysinger <vapier@gentoo.org>
569 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
571 (is_macmod_pmove, is_macmod_hmove): New functions.
573 2011-02-11 Mike Frysinger <vapier@gentoo.org>
575 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
577 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
579 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
580 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
582 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
585 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
588 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
591 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
593 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
595 * mips.h: Update commentary after last commit.
597 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
599 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
600 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
601 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
603 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
605 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
607 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
609 * mips.h: Fix previous commit.
611 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
613 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
614 (INSN_LOONGSON_3A): Clear bit 31.
616 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
619 * arm.h (ARM_AEXT_V6M_ONLY): New define.
620 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
621 (ARM_ARCH_V6M_ONLY): New define.
623 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
625 * mips.h (INSN_LOONGSON_3A): Defined.
626 (CPU_LOONGSON_3A): Defined.
627 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
629 2010-10-09 Matt Rice <ratmice@gmail.com>
631 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
632 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
634 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
636 * arm.h (ARM_EXT_VIRT): New define.
637 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
638 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
641 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
643 * arm.h (ARM_AEXT_ADIV): New define.
644 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
646 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
648 * arm.h (ARM_EXT_OS): New define.
649 (ARM_AEXT_V6SM): Likewise.
650 (ARM_ARCH_V6SM): Likewise.
652 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
654 * arm.h (ARM_EXT_MP): Add.
655 (ARM_ARCH_V7A_MP): Likewise.
657 2010-09-22 Mike Frysinger <vapier@gentoo.org>
659 * bfin.h: Declare pseudoChr structs/defines.
661 2010-09-21 Mike Frysinger <vapier@gentoo.org>
663 * bfin.h: Strip trailing whitespace.
665 2010-07-29 DJ Delorie <dj@redhat.com>
667 * rx.h (RX_Operand_Type): Add TwoReg.
668 (RX_Opcode_ID): Remove ediv and ediv2.
670 2010-07-27 DJ Delorie <dj@redhat.com>
672 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
674 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
675 Ina Pandit <ina.pandit@kpitcummins.com>
677 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
678 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
679 PROCESSOR_V850E2_ALL.
680 Remove PROCESSOR_V850EA support.
681 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
682 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
683 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
684 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
685 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
686 V850_OPERAND_PERCENT.
687 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
689 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
692 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
694 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
695 (MIPS16_INSN_BRANCH): Rename to...
696 (MIPS16_INSN_COND_BRANCH): ... this.
698 2010-07-03 Alan Modra <amodra@gmail.com>
700 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
701 Renumber other PPC_OPCODE defines.
703 2010-07-03 Alan Modra <amodra@gmail.com>
705 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
707 2010-06-29 Alan Modra <amodra@gmail.com>
709 * maxq.h: Delete file.
711 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
713 * ppc.h (PPC_OPCODE_E500): Define.
715 2010-05-26 Catherine Moore <clm@codesourcery.com>
717 * opcode/mips.h (INSN_MIPS16): Remove.
719 2010-04-21 Joseph Myers <joseph@codesourcery.com>
721 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
723 2010-04-15 Nick Clifton <nickc@redhat.com>
725 * alpha.h: Update copyright notice to use GPLv3.
731 * convex.h: Likewise.
745 * m68hc11.h: Likewise.
751 * mn10200.h: Likewise.
752 * mn10300.h: Likewise.
753 * msp430.h: Likewise.
764 * score-datadep.h: Likewise.
765 * score-inst.h: Likewise.
767 * spu-insns.h: Likewise.
771 * tic54x.h: Likewise.
776 2010-03-25 Joseph Myers <joseph@codesourcery.com>
778 * tic6x-control-registers.h, tic6x-insn-formats.h,
779 tic6x-opcode-table.h, tic6x.h: New.
781 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
783 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
785 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
787 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
789 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
791 * ia64.h (ia64_find_opcode): Remove argument name.
792 (ia64_find_next_opcode): Likewise.
793 (ia64_dis_opcode): Likewise.
794 (ia64_free_opcode): Likewise.
795 (ia64_find_dependency): Likewise.
797 2009-11-22 Doug Evans <dje@sebabeach.org>
799 * cgen.h: Include bfd_stdint.h.
800 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
802 2009-11-18 Paul Brook <paul@codesourcery.com>
804 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
806 2009-11-17 Paul Brook <paul@codesourcery.com>
807 Daniel Jacobowitz <dan@codesourcery.com>
809 * arm.h (ARM_EXT_V6_DSP): Define.
810 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
811 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
813 2009-11-04 DJ Delorie <dj@redhat.com>
815 * rx.h (rx_decode_opcode) (mvtipl): Add.
816 (mvtcp, mvfcp, opecp): Remove.
818 2009-11-02 Paul Brook <paul@codesourcery.com>
820 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
821 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
822 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
823 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
824 FPU_ARCH_NEON_VFP_V4): Define.
826 2009-10-23 Doug Evans <dje@sebabeach.org>
828 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
829 * cgen.h: Update. Improve multi-inclusion macro name.
831 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
833 * ppc.h (PPC_OPCODE_476): Define.
835 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
837 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
839 2009-09-29 DJ Delorie <dj@redhat.com>
843 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
845 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
847 2009-09-21 Ben Elliston <bje@au.ibm.com>
849 * ppc.h (PPC_OPCODE_PPCA2): New.
851 2009-09-05 Martin Thuresson <martin@mtme.org>
853 * ia64.h (struct ia64_operand): Renamed member class to op_class.
855 2009-08-29 Martin Thuresson <martin@mtme.org>
857 * tic30.h (template): Rename type template to
858 insn_template. Updated code to use new name.
859 * tic54x.h (template): Rename type template to
862 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
864 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
866 2009-06-11 Anthony Green <green@moxielogic.com>
868 * moxie.h (MOXIE_F3_PCREL): Define.
869 (moxie_form3_opc_info): Grow.
871 2009-06-06 Anthony Green <green@moxielogic.com>
873 * moxie.h (MOXIE_F1_M): Define.
875 2009-04-15 Anthony Green <green@moxielogic.com>
879 2009-04-06 DJ Delorie <dj@redhat.com>
881 * h8300.h: Add relaxation attributes to MOVA opcodes.
883 2009-03-10 Alan Modra <amodra@bigpond.net.au>
885 * ppc.h (ppc_parse_cpu): Declare.
887 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
889 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
890 and _IMM11 for mbitclr and mbitset.
891 * score-datadep.h: Update dependency information.
893 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
895 * ppc.h (PPC_OPCODE_POWER7): New.
897 2009-02-06 Doug Evans <dje@google.com>
899 * i386.h: Add comment regarding sse* insns and prefixes.
901 2009-02-03 Sandip Matte <sandip@rmicorp.com>
903 * mips.h (INSN_XLR): Define.
904 (INSN_CHIP_MASK): Update.
906 (OPCODE_IS_MEMBER): Update.
907 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
909 2009-01-28 Doug Evans <dje@google.com>
911 * opcode/i386.h: Add multiple inclusion protection.
912 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
913 (EDI_REG_NUM): New macros.
914 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
915 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
916 (REX_PREFIX_P): New macro.
918 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
920 * ppc.h (struct powerpc_opcode): New field "deprecated".
921 (PPC_OPCODE_NOPOWER4): Delete.
923 2008-11-28 Joshua Kinard <kumba@gentoo.org>
925 * mips.h: Define CPU_R14000, CPU_R16000.
926 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
928 2008-11-18 Catherine Moore <clm@codesourcery.com>
930 * arm.h (FPU_NEON_FP16): New.
931 (FPU_ARCH_NEON_FP16): New.
933 2008-11-06 Chao-ying Fu <fu@mips.com>
935 * mips.h: Doucument '1' for 5-bit sync type.
937 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
939 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
942 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
944 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
946 2008-07-30 Michael J. Eager <eager@eagercon.com>
948 * ppc.h (PPC_OPCODE_405): Define.
949 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
951 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
953 * ppc.h (ppc_cpu_t): New typedef.
954 (struct powerpc_opcode <flags>): Use it.
955 (struct powerpc_operand <insert, extract>): Likewise.
956 (struct powerpc_macro <flags>): Likewise.
958 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
960 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
961 Update comment before MIPS16 field descriptors to mention MIPS16.
962 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
964 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
965 New bit masks and shift counts for cins and exts.
967 * mips.h: Document new field descriptors +Q.
968 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
970 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
972 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
973 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
975 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
977 * ppc.h: (PPC_OPCODE_E500MC): New.
979 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
981 * i386.h (MAX_OPERANDS): Set to 5.
982 (MAX_MNEM_SIZE): Changed to 20.
984 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
986 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
988 2008-03-09 Paul Brook <paul@codesourcery.com>
990 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
992 2008-03-04 Paul Brook <paul@codesourcery.com>
994 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
995 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
996 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
998 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
999 Nick Clifton <nickc@redhat.com>
1002 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1003 with a 32-bit displacement but without the top bit of the 4th byte
1006 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1008 * cr16.h (cr16_num_optab): Declared.
1010 2008-02-14 Hakan Ardo <hakan@debian.org>
1013 * avr.h (AVR_ISA_2xxe): Define.
1015 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1017 * mips.h: Update copyright.
1018 (INSN_CHIP_MASK): New macro.
1019 (INSN_OCTEON): New macro.
1020 (CPU_OCTEON): New macro.
1021 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1023 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1025 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1027 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1029 * avr.h (AVR_ISA_USB162): Add new opcode set.
1030 (AVR_ISA_AVR3): Likewise.
1032 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1034 * mips.h (INSN_LOONGSON_2E): New.
1035 (INSN_LOONGSON_2F): New.
1036 (CPU_LOONGSON_2E): New.
1037 (CPU_LOONGSON_2F): New.
1038 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1040 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1042 * mips.h (INSN_ISA*): Redefine certain values as an
1043 enumeration. Update comments.
1044 (mips_isa_table): New.
1045 (ISA_MIPS*): Redefine to match enumeration.
1046 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1049 2007-08-08 Ben Elliston <bje@au.ibm.com>
1051 * ppc.h (PPC_OPCODE_PPCPS): New.
1053 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1055 * m68k.h: Document j K & E.
1057 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1059 * cr16.h: New file for CR16 target.
1061 2007-05-02 Alan Modra <amodra@bigpond.net.au>
1063 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1065 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1067 * m68k.h (mcfisa_c): New.
1068 (mcfusp, mcf_mask): Adjust.
1070 2007-04-20 Alan Modra <amodra@bigpond.net.au>
1072 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1073 (num_powerpc_operands): Declare.
1074 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1075 (PPC_OPERAND_PLUS1): Define.
1077 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
1079 * i386.h (REX_MODE64): Renamed to ...
1081 (REX_EXTX): Renamed to ...
1083 (REX_EXTY): Renamed to ...
1085 (REX_EXTZ): Renamed to ...
1088 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1090 * i386.h: Add entries from config/tc-i386.h and move tables
1091 to opcodes/i386-opc.h.
1093 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1095 * i386.h (FloatDR): Removed.
1096 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1098 2007-03-01 Alan Modra <amodra@bigpond.net.au>
1100 * spu-insns.h: Add soma double-float insns.
1102 2007-02-20 Thiemo Seufer <ths@mips.com>
1103 Chao-Ying Fu <fu@mips.com>
1105 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1106 (INSN_DSPR2): Add flag for DSP R2 instructions.
1107 (M_BALIGN): New macro.
1109 2007-02-14 Alan Modra <amodra@bigpond.net.au>
1111 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1112 and Seg3ShortFrom with Shortform.
1114 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1117 * i386.h (i386_optab): Put the real "test" before the pseudo
1120 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
1122 * m68k.h (m68010up): OR fido_a.
1124 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
1126 * m68k.h (fido_a): New.
1128 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
1130 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1131 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1134 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1136 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1138 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1140 * score-inst.h (enum score_insn_type): Add Insn_internal.
1142 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1143 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1144 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1145 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1146 Alan Modra <amodra@bigpond.net.au>
1148 * spu-insns.h: New file.
1151 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1153 * ppc.h (PPC_OPCODE_CELL): Define.
1155 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1157 * i386.h : Modify opcode to support for the change in POPCNT opcode
1158 in amdfam10 architecture.
1160 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1162 * i386.h: Replace CpuMNI with CpuSSSE3.
1164 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
1165 Joseph Myers <joseph@codesourcery.com>
1166 Ian Lance Taylor <ian@wasabisystems.com>
1167 Ben Elliston <bje@wasabisystems.com>
1169 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1171 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1173 * score-datadep.h: New file.
1174 * score-inst.h: New file.
1176 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1178 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1179 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1180 movdq2q and movq2dq.
1182 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1183 Michael Meissner <michael.meissner@amd.com>
1185 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1187 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1189 * i386.h (i386_optab): Add "nop" with memory reference.
1191 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1193 * i386.h (i386_optab): Update comment for 64bit NOP.
1195 2006-06-06 Ben Elliston <bje@au.ibm.com>
1196 Anton Blanchard <anton@samba.org>
1198 * ppc.h (PPC_OPCODE_POWER6): Define.
1201 2006-06-05 Thiemo Seufer <ths@mips.com>
1203 * mips.h: Improve description of MT flags.
1205 2006-05-25 Richard Sandiford <richard@codesourcery.com>
1207 * m68k.h (mcf_mask): Define.
1209 2006-05-05 Thiemo Seufer <ths@mips.com>
1210 David Ung <davidu@mips.com>
1212 * mips.h (enum): Add macro M_CACHE_AB.
1214 2006-05-04 Thiemo Seufer <ths@mips.com>
1215 Nigel Stephens <nigel@mips.com>
1216 David Ung <davidu@mips.com>
1218 * mips.h: Add INSN_SMARTMIPS define.
1220 2006-04-30 Thiemo Seufer <ths@mips.com>
1221 David Ung <davidu@mips.com>
1223 * mips.h: Defines udi bits and masks. Add description of
1224 characters which may appear in the args field of udi
1227 2006-04-26 Thiemo Seufer <ths@networkno.de>
1229 * mips.h: Improve comments describing the bitfield instruction
1232 2006-04-26 Julian Brown <julian@codesourcery.com>
1234 * arm.h (FPU_VFP_EXT_V3): Define constant.
1235 (FPU_NEON_EXT_V1): Likewise.
1236 (FPU_VFP_HARD): Update.
1237 (FPU_VFP_V3): Define macro.
1238 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1240 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
1242 * avr.h (AVR_ISA_PWMx): New.
1244 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1246 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1247 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1248 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1249 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1250 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1252 2006-03-10 Paul Brook <paul@codesourcery.com>
1254 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1256 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1258 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1259 first. Correct mask of bb "B" opcode.
1261 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1263 * i386.h (i386_optab): Support Intel Merom New Instructions.
1265 2006-02-24 Paul Brook <paul@codesourcery.com>
1267 * arm.h: Add V7 feature bits.
1269 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1271 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1273 2006-01-31 Paul Brook <paul@codesourcery.com>
1274 Richard Earnshaw <rearnsha@arm.com>
1276 * arm.h: Use ARM_CPU_FEATURE.
1277 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1278 (arm_feature_set): Change to a structure.
1279 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1280 ARM_FEATURE): New macros.
1282 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
1284 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1285 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1286 (ADD_PC_INCR_OPCODE): Don't define.
1288 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1291 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1293 2005-11-14 David Ung <davidu@mips.com>
1295 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1296 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1297 save/restore encoding of the args field.
1299 2005-10-28 Dave Brolley <brolley@redhat.com>
1301 Contribute the following changes:
1302 2005-02-16 Dave Brolley <brolley@redhat.com>
1304 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1305 cgen_isa_mask_* to cgen_bitset_*.
1308 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1310 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1311 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1312 (CGEN_CPU_TABLE): Make isas a ponter.
1314 2003-09-29 Dave Brolley <brolley@redhat.com>
1316 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1317 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1318 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1320 2002-12-13 Dave Brolley <brolley@redhat.com>
1322 * cgen.h (symcat.h): #include it.
1323 (cgen-bitset.h): #include it.
1324 (CGEN_ATTR_VALUE_TYPE): Now a union.
1325 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1326 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1327 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1328 * cgen-bitset.h: New file.
1330 2005-09-30 Catherine Moore <clm@cm00re.com>
1334 2005-10-24 Jan Beulich <jbeulich@novell.com>
1336 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1339 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1341 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1342 Add FLAG_STRICT to pa10 ftest opcode.
1344 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1346 * hppa.h (pa_opcodes): Remove lha entries.
1348 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1350 * hppa.h (FLAG_STRICT): Revise comment.
1351 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1352 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1355 2005-09-30 Catherine Moore <clm@cm00re.com>
1359 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1361 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1363 2005-09-06 Chao-ying Fu <fu@mips.com>
1365 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1366 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1368 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1369 (INSN_ASE_MASK): Update to include INSN_MT.
1370 (INSN_MT): New define for MT ASE.
1372 2005-08-25 Chao-ying Fu <fu@mips.com>
1374 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1375 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1376 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1377 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1378 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1379 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1381 (INSN_DSP): New define for DSP ASE.
1383 2005-08-18 Alan Modra <amodra@bigpond.net.au>
1387 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1389 * ppc.h (PPC_OPCODE_E300): Define.
1391 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1393 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1395 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1398 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1401 2005-07-27 Jan Beulich <jbeulich@novell.com>
1403 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1404 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1405 Add movq-s as 64-bit variants of movd-s.
1407 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1409 * hppa.h: Fix punctuation in comment.
1411 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1412 implicit space-register addressing. Set space-register bits on opcodes
1413 using implicit space-register addressing. Add various missing pa20
1414 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1415 space-register addressing. Use "fE" instead of "fe" in various
1418 2005-07-18 Jan Beulich <jbeulich@novell.com>
1420 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1422 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1424 * i386.h (i386_optab): Support Intel VMX Instructions.
1426 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1428 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1430 2005-07-05 Jan Beulich <jbeulich@novell.com>
1432 * i386.h (i386_optab): Add new insns.
1434 2005-07-01 Nick Clifton <nickc@redhat.com>
1436 * sparc.h: Add typedefs to structure declarations.
1438 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1441 * i386.h (i386_optab): Update comments for 64bit addressing on
1442 mov. Allow 64bit addressing for mov and movq.
1444 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1446 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1447 respectively, in various floating-point load and store patterns.
1449 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1451 * hppa.h (FLAG_STRICT): Correct comment.
1452 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1453 PA 2.0 mneumonics when equivalent. Entries with cache control
1454 completers now require PA 1.1. Adjust whitespace.
1456 2005-05-19 Anton Blanchard <anton@samba.org>
1458 * ppc.h (PPC_OPCODE_POWER5): Define.
1460 2005-05-10 Nick Clifton <nickc@redhat.com>
1462 * Update the address and phone number of the FSF organization in
1463 the GPL notices in the following files:
1464 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1465 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1466 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1467 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1468 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1469 tic54x.h, tic80.h, v850.h, vax.h
1471 2005-05-09 Jan Beulich <jbeulich@novell.com>
1473 * i386.h (i386_optab): Add ht and hnt.
1475 2005-04-18 Mark Kettenis <kettenis@gnu.org>
1477 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1478 Add xcrypt-ctr. Provide aliases without hyphens.
1480 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1482 Moved from ../ChangeLog
1484 2005-04-12 Paul Brook <paul@codesourcery.com>
1485 * m88k.h: Rename psr macros to avoid conflicts.
1487 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1488 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1489 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1490 and ARM_ARCH_V6ZKT2.
1492 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1493 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1494 Remove redundant instruction types.
1495 (struct argument): X_op - new field.
1496 (struct cst4_entry): Remove.
1497 (no_op_insn): Declare.
1499 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1500 * crx.h (enum argtype): Rename types, remove unused types.
1502 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1503 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1504 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1505 (enum operand_type): Rearrange operands, edit comments.
1506 replace us<N> with ui<N> for unsigned immediate.
1507 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1508 displacements (respectively).
1509 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1510 (instruction type): Add NO_TYPE_INS.
1511 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1512 (operand_entry): New field - 'flags'.
1513 (operand flags): New.
1515 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1516 * crx.h (operand_type): Remove redundant types i3, i4,
1518 Add new unsigned immediate types us3, us4, us5, us16.
1520 2005-04-12 Mark Kettenis <kettenis@gnu.org>
1522 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1523 adjust them accordingly.
1525 2005-04-01 Jan Beulich <jbeulich@novell.com>
1527 * i386.h (i386_optab): Add rdtscp.
1529 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1531 * i386.h (i386_optab): Don't allow the `l' suffix for moving
1532 between memory and segment register. Allow movq for moving between
1533 general-purpose register and segment register.
1535 2005-02-09 Jan Beulich <jbeulich@novell.com>
1538 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1539 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1542 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1544 * m68k.h (m68008, m68ec030, m68882): Remove.
1546 (cpu_m68k, cpu_cf): New.
1547 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1548 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1550 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
1552 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1553 * cgen.h (enum cgen_parse_operand_type): Add
1554 CGEN_PARSE_OPERAND_SYMBOLIC.
1556 2005-01-21 Fred Fish <fnf@specifixinc.com>
1558 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1559 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1560 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1562 2005-01-19 Fred Fish <fnf@specifixinc.com>
1564 * mips.h (struct mips_opcode): Add new pinfo2 member.
1565 (INSN_ALIAS): New define for opcode table entries that are
1566 specific instances of another entry, such as 'move' for an 'or'
1567 with a zero operand.
1568 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1569 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1571 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1573 * mips.h (CPU_RM9000): Define.
1574 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1576 2004-11-25 Jan Beulich <jbeulich@novell.com>
1578 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1579 to/from test registers are illegal in 64-bit mode. Add missing
1580 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1581 (previously one had to explicitly encode a rex64 prefix). Re-enable
1582 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1583 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1585 2004-11-23 Jan Beulich <jbeulich@novell.com>
1587 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1588 available only with SSE2. Change the MMX additions introduced by SSE
1589 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1590 instructions by their now designated identifier (since combining i686
1591 and 3DNow! does not really imply 3DNow!A).
1593 2004-11-19 Alan Modra <amodra@bigpond.net.au>
1595 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1596 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1598 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1599 Vineet Sharma <vineets@noida.hcltech.com>
1601 * maxq.h: New file: Disassembly information for the maxq port.
1603 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1605 * i386.h (i386_optab): Put back "movzb".
1607 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
1609 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1610 comments. Remove member cris_ver_sim. Add members
1611 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1612 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1613 (struct cris_support_reg, struct cris_cond15): New types.
1614 (cris_conds15): Declare.
1615 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1616 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1617 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1618 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1619 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1620 SIZE_FIELD_UNSIGNED.
1622 2004-11-04 Jan Beulich <jbeulich@novell.com>
1624 * i386.h (sldx_Suf): Remove.
1625 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1626 (q_FP): Define, implying no REX64.
1627 (x_FP, sl_FP): Imply FloatMF.
1628 (i386_optab): Split reg and mem forms of moving from segment registers
1629 so that the memory forms can ignore the 16-/32-bit operand size
1630 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1631 all non-floating-point instructions. Unite 32- and 64-bit forms of
1632 movsx, movzx, and movd. Adjust floating point operations for the above
1633 changes to the *FP macros. Add DefaultSize to floating point control
1634 insns operating on larger memory ranges. Remove left over comments
1635 hinting at certain insns being Intel-syntax ones where the ones
1636 actually meant are already gone.
1638 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1640 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1643 2004-09-30 Paul Brook <paul@codesourcery.com>
1645 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1646 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1648 2004-09-11 Theodore A. Roth <troth@openavr.org>
1650 * avr.h: Add support for
1651 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1653 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1655 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1657 2004-08-24 Dmitry Diky <diwil@spec.ru>
1659 * msp430.h (msp430_opc): Add new instructions.
1660 (msp430_rcodes): Declare new instructions.
1661 (msp430_hcodes): Likewise..
1663 2004-08-13 Nick Clifton <nickc@redhat.com>
1666 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1669 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1671 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1673 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1675 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1677 2004-07-21 Jan Beulich <jbeulich@novell.com>
1679 * i386.h: Adjust instruction descriptions to better match the
1682 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
1684 * arm.h: Remove all old content. Replace with architecture defines
1685 from gas/config/tc-arm.c.
1687 2004-07-09 Andreas Schwab <schwab@suse.de>
1689 * m68k.h: Fix comment.
1691 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1695 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1697 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1699 2004-05-24 Peter Barada <peter@the-baradas.com>
1701 * m68k.h: Add 'size' to m68k_opcode.
1703 2004-05-05 Peter Barada <peter@the-baradas.com>
1705 * m68k.h: Switch from ColdFire chip name to core variant.
1707 2004-04-22 Peter Barada <peter@the-baradas.com>
1709 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1710 descriptions for new EMAC cases.
1711 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1712 handle Motorola MAC syntax.
1713 Allow disassembly of ColdFire V4e object files.
1715 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1717 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1719 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1721 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1723 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1725 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1727 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1729 * i386.h (i386_optab): Added xstore/xcrypt insns.
1731 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1733 * h8300.h (32bit ldc/stc): Add relaxing support.
1735 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1737 * h8300.h (BITOP): Pass MEMRELAX flag.
1739 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1741 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1744 For older changes see ChangeLog-9103
1746 Copyright (C) 2004-2012 Free Software Foundation, Inc.
1748 Copying and distribution of this file, with or without modification,
1749 are permitted in any medium without royalty provided the copyright
1750 notice and this notice are preserved.
1756 version-control: never