1 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
3 * mips.h (INSN_TRAP): Rename to...
4 (INSN_NO_DELAY_SLOT): ... this.
5 (INSN_SYNC): Remove macro.
7 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
9 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
10 a duplicate of AVR_ISA_SPM.
12 2011-07-01 Nick Clifton <nickc@redhat.com>
14 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
16 2011-06-18 Robin Getz <robin.getz@analog.com>
18 * bfin.h (is_macmod_signed): New func
20 2011-06-18 Mike Frysinger <vapier@gentoo.org>
22 * bfin.h (is_macmod_pmove): Add missing space before func args.
23 (is_macmod_hmove): Likewise.
25 2011-06-13 Walter Lee <walt@tilera.com>
28 * tilepro.h: New file.
30 2011-05-31 Paul Brook <paul@codesourcery.com>
32 * arm.h (ARM_ARCH_V7R_IDIV): Define.
34 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
36 * s390.h: Replace S390_OPERAND_REG_EVEN with
37 S390_OPERAND_REG_PAIR.
39 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
41 * s390.h: Add S390_OPCODE_REG_EVEN flag.
43 2011-04-18 Julian Brown <julian@codesourcery.com>
45 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
47 2011-04-11 Dan McDonald <dan@wellkeeper.com>
50 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
52 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
54 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
55 New instruction set flags.
56 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
58 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
60 * mips.h (M_PREF_AB): New enum value.
62 2011-02-12 Mike Frysinger <vapier@gentoo.org>
64 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
66 (is_macmod_pmove, is_macmod_hmove): New functions.
68 2011-02-11 Mike Frysinger <vapier@gentoo.org>
70 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
72 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
74 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
75 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
77 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
80 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
83 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
86 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
88 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
90 * mips.h: Update commentary after last commit.
92 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
94 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
95 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
96 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
98 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
100 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
102 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
104 * mips.h: Fix previous commit.
106 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
108 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
109 (INSN_LOONGSON_3A): Clear bit 31.
111 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
114 * arm.h (ARM_AEXT_V6M_ONLY): New define.
115 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
116 (ARM_ARCH_V6M_ONLY): New define.
118 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
120 * mips.h (INSN_LOONGSON_3A): Defined.
121 (CPU_LOONGSON_3A): Defined.
122 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
124 2010-10-09 Matt Rice <ratmice@gmail.com>
126 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
127 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
129 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
131 * arm.h (ARM_EXT_VIRT): New define.
132 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
133 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
136 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
138 * arm.h (ARM_AEXT_ADIV): New define.
139 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
141 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
143 * arm.h (ARM_EXT_OS): New define.
144 (ARM_AEXT_V6SM): Likewise.
145 (ARM_ARCH_V6SM): Likewise.
147 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
149 * arm.h (ARM_EXT_MP): Add.
150 (ARM_ARCH_V7A_MP): Likewise.
152 2010-09-22 Mike Frysinger <vapier@gentoo.org>
154 * bfin.h: Declare pseudoChr structs/defines.
156 2010-09-21 Mike Frysinger <vapier@gentoo.org>
158 * bfin.h: Strip trailing whitespace.
160 2010-07-29 DJ Delorie <dj@redhat.com>
162 * rx.h (RX_Operand_Type): Add TwoReg.
163 (RX_Opcode_ID): Remove ediv and ediv2.
165 2010-07-27 DJ Delorie <dj@redhat.com>
167 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
169 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
170 Ina Pandit <ina.pandit@kpitcummins.com>
172 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
173 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
174 PROCESSOR_V850E2_ALL.
175 Remove PROCESSOR_V850EA support.
176 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
177 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
178 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
179 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
180 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
181 V850_OPERAND_PERCENT.
182 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
184 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
187 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
189 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
190 (MIPS16_INSN_BRANCH): Rename to...
191 (MIPS16_INSN_COND_BRANCH): ... this.
193 2010-07-03 Alan Modra <amodra@gmail.com>
195 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
196 Renumber other PPC_OPCODE defines.
198 2010-07-03 Alan Modra <amodra@gmail.com>
200 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
202 2010-06-29 Alan Modra <amodra@gmail.com>
204 * maxq.h: Delete file.
206 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
208 * ppc.h (PPC_OPCODE_E500): Define.
210 2010-05-26 Catherine Moore <clm@codesourcery.com>
212 * opcode/mips.h (INSN_MIPS16): Remove.
214 2010-04-21 Joseph Myers <joseph@codesourcery.com>
216 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
218 2010-04-15 Nick Clifton <nickc@redhat.com>
220 * alpha.h: Update copyright notice to use GPLv3.
226 * convex.h: Likewise.
240 * m68hc11.h: Likewise.
246 * mn10200.h: Likewise.
247 * mn10300.h: Likewise.
248 * msp430.h: Likewise.
259 * score-datadep.h: Likewise.
260 * score-inst.h: Likewise.
262 * spu-insns.h: Likewise.
266 * tic54x.h: Likewise.
271 2010-03-25 Joseph Myers <joseph@codesourcery.com>
273 * tic6x-control-registers.h, tic6x-insn-formats.h,
274 tic6x-opcode-table.h, tic6x.h: New.
276 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
278 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
280 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
282 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
284 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
286 * ia64.h (ia64_find_opcode): Remove argument name.
287 (ia64_find_next_opcode): Likewise.
288 (ia64_dis_opcode): Likewise.
289 (ia64_free_opcode): Likewise.
290 (ia64_find_dependency): Likewise.
292 2009-11-22 Doug Evans <dje@sebabeach.org>
294 * cgen.h: Include bfd_stdint.h.
295 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
297 2009-11-18 Paul Brook <paul@codesourcery.com>
299 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
301 2009-11-17 Paul Brook <paul@codesourcery.com>
302 Daniel Jacobowitz <dan@codesourcery.com>
304 * arm.h (ARM_EXT_V6_DSP): Define.
305 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
306 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
308 2009-11-04 DJ Delorie <dj@redhat.com>
310 * rx.h (rx_decode_opcode) (mvtipl): Add.
311 (mvtcp, mvfcp, opecp): Remove.
313 2009-11-02 Paul Brook <paul@codesourcery.com>
315 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
316 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
317 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
318 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
319 FPU_ARCH_NEON_VFP_V4): Define.
321 2009-10-23 Doug Evans <dje@sebabeach.org>
323 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
324 * cgen.h: Update. Improve multi-inclusion macro name.
326 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
328 * ppc.h (PPC_OPCODE_476): Define.
330 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
332 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
334 2009-09-29 DJ Delorie <dj@redhat.com>
338 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
340 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
342 2009-09-21 Ben Elliston <bje@au.ibm.com>
344 * ppc.h (PPC_OPCODE_PPCA2): New.
346 2009-09-05 Martin Thuresson <martin@mtme.org>
348 * ia64.h (struct ia64_operand): Renamed member class to op_class.
350 2009-08-29 Martin Thuresson <martin@mtme.org>
352 * tic30.h (template): Rename type template to
353 insn_template. Updated code to use new name.
354 * tic54x.h (template): Rename type template to
357 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
359 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
361 2009-06-11 Anthony Green <green@moxielogic.com>
363 * moxie.h (MOXIE_F3_PCREL): Define.
364 (moxie_form3_opc_info): Grow.
366 2009-06-06 Anthony Green <green@moxielogic.com>
368 * moxie.h (MOXIE_F1_M): Define.
370 2009-04-15 Anthony Green <green@moxielogic.com>
374 2009-04-06 DJ Delorie <dj@redhat.com>
376 * h8300.h: Add relaxation attributes to MOVA opcodes.
378 2009-03-10 Alan Modra <amodra@bigpond.net.au>
380 * ppc.h (ppc_parse_cpu): Declare.
382 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
384 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
385 and _IMM11 for mbitclr and mbitset.
386 * score-datadep.h: Update dependency information.
388 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
390 * ppc.h (PPC_OPCODE_POWER7): New.
392 2009-02-06 Doug Evans <dje@google.com>
394 * i386.h: Add comment regarding sse* insns and prefixes.
396 2009-02-03 Sandip Matte <sandip@rmicorp.com>
398 * mips.h (INSN_XLR): Define.
399 (INSN_CHIP_MASK): Update.
401 (OPCODE_IS_MEMBER): Update.
402 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
404 2009-01-28 Doug Evans <dje@google.com>
406 * opcode/i386.h: Add multiple inclusion protection.
407 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
408 (EDI_REG_NUM): New macros.
409 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
410 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
411 (REX_PREFIX_P): New macro.
413 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
415 * ppc.h (struct powerpc_opcode): New field "deprecated".
416 (PPC_OPCODE_NOPOWER4): Delete.
418 2008-11-28 Joshua Kinard <kumba@gentoo.org>
420 * mips.h: Define CPU_R14000, CPU_R16000.
421 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
423 2008-11-18 Catherine Moore <clm@codesourcery.com>
425 * arm.h (FPU_NEON_FP16): New.
426 (FPU_ARCH_NEON_FP16): New.
428 2008-11-06 Chao-ying Fu <fu@mips.com>
430 * mips.h: Doucument '1' for 5-bit sync type.
432 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
434 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
437 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
439 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
441 2008-07-30 Michael J. Eager <eager@eagercon.com>
443 * ppc.h (PPC_OPCODE_405): Define.
444 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
446 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
448 * ppc.h (ppc_cpu_t): New typedef.
449 (struct powerpc_opcode <flags>): Use it.
450 (struct powerpc_operand <insert, extract>): Likewise.
451 (struct powerpc_macro <flags>): Likewise.
453 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
455 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
456 Update comment before MIPS16 field descriptors to mention MIPS16.
457 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
459 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
460 New bit masks and shift counts for cins and exts.
462 * mips.h: Document new field descriptors +Q.
463 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
465 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
467 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
468 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
470 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
472 * ppc.h: (PPC_OPCODE_E500MC): New.
474 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
476 * i386.h (MAX_OPERANDS): Set to 5.
477 (MAX_MNEM_SIZE): Changed to 20.
479 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
481 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
483 2008-03-09 Paul Brook <paul@codesourcery.com>
485 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
487 2008-03-04 Paul Brook <paul@codesourcery.com>
489 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
490 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
491 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
493 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
494 Nick Clifton <nickc@redhat.com>
497 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
498 with a 32-bit displacement but without the top bit of the 4th byte
501 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
503 * cr16.h (cr16_num_optab): Declared.
505 2008-02-14 Hakan Ardo <hakan@debian.org>
508 * avr.h (AVR_ISA_2xxe): Define.
510 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
512 * mips.h: Update copyright.
513 (INSN_CHIP_MASK): New macro.
514 (INSN_OCTEON): New macro.
515 (CPU_OCTEON): New macro.
516 (OPCODE_IS_MEMBER): Handle Octeon instructions.
518 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
520 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
522 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
524 * avr.h (AVR_ISA_USB162): Add new opcode set.
525 (AVR_ISA_AVR3): Likewise.
527 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
529 * mips.h (INSN_LOONGSON_2E): New.
530 (INSN_LOONGSON_2F): New.
531 (CPU_LOONGSON_2E): New.
532 (CPU_LOONGSON_2F): New.
533 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
535 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
537 * mips.h (INSN_ISA*): Redefine certain values as an
538 enumeration. Update comments.
539 (mips_isa_table): New.
540 (ISA_MIPS*): Redefine to match enumeration.
541 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
544 2007-08-08 Ben Elliston <bje@au.ibm.com>
546 * ppc.h (PPC_OPCODE_PPCPS): New.
548 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
550 * m68k.h: Document j K & E.
552 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
554 * cr16.h: New file for CR16 target.
556 2007-05-02 Alan Modra <amodra@bigpond.net.au>
558 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
560 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
562 * m68k.h (mcfisa_c): New.
563 (mcfusp, mcf_mask): Adjust.
565 2007-04-20 Alan Modra <amodra@bigpond.net.au>
567 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
568 (num_powerpc_operands): Declare.
569 (PPC_OPERAND_SIGNED et al): Redefine as hex.
570 (PPC_OPERAND_PLUS1): Define.
572 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
574 * i386.h (REX_MODE64): Renamed to ...
576 (REX_EXTX): Renamed to ...
578 (REX_EXTY): Renamed to ...
580 (REX_EXTZ): Renamed to ...
583 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
585 * i386.h: Add entries from config/tc-i386.h and move tables
586 to opcodes/i386-opc.h.
588 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
590 * i386.h (FloatDR): Removed.
591 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
593 2007-03-01 Alan Modra <amodra@bigpond.net.au>
595 * spu-insns.h: Add soma double-float insns.
597 2007-02-20 Thiemo Seufer <ths@mips.com>
598 Chao-Ying Fu <fu@mips.com>
600 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
601 (INSN_DSPR2): Add flag for DSP R2 instructions.
602 (M_BALIGN): New macro.
604 2007-02-14 Alan Modra <amodra@bigpond.net.au>
606 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
607 and Seg3ShortFrom with Shortform.
609 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
612 * i386.h (i386_optab): Put the real "test" before the pseudo
615 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
617 * m68k.h (m68010up): OR fido_a.
619 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
621 * m68k.h (fido_a): New.
623 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
625 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
626 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
629 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
631 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
633 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
635 * score-inst.h (enum score_insn_type): Add Insn_internal.
637 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
638 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
639 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
640 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
641 Alan Modra <amodra@bigpond.net.au>
643 * spu-insns.h: New file.
646 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
648 * ppc.h (PPC_OPCODE_CELL): Define.
650 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
652 * i386.h : Modify opcode to support for the change in POPCNT opcode
653 in amdfam10 architecture.
655 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
657 * i386.h: Replace CpuMNI with CpuSSSE3.
659 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
660 Joseph Myers <joseph@codesourcery.com>
661 Ian Lance Taylor <ian@wasabisystems.com>
662 Ben Elliston <bje@wasabisystems.com>
664 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
666 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
668 * score-datadep.h: New file.
669 * score-inst.h: New file.
671 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
673 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
674 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
677 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
678 Michael Meissner <michael.meissner@amd.com>
680 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
682 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
684 * i386.h (i386_optab): Add "nop" with memory reference.
686 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
688 * i386.h (i386_optab): Update comment for 64bit NOP.
690 2006-06-06 Ben Elliston <bje@au.ibm.com>
691 Anton Blanchard <anton@samba.org>
693 * ppc.h (PPC_OPCODE_POWER6): Define.
696 2006-06-05 Thiemo Seufer <ths@mips.com>
698 * mips.h: Improve description of MT flags.
700 2006-05-25 Richard Sandiford <richard@codesourcery.com>
702 * m68k.h (mcf_mask): Define.
704 2006-05-05 Thiemo Seufer <ths@mips.com>
705 David Ung <davidu@mips.com>
707 * mips.h (enum): Add macro M_CACHE_AB.
709 2006-05-04 Thiemo Seufer <ths@mips.com>
710 Nigel Stephens <nigel@mips.com>
711 David Ung <davidu@mips.com>
713 * mips.h: Add INSN_SMARTMIPS define.
715 2006-04-30 Thiemo Seufer <ths@mips.com>
716 David Ung <davidu@mips.com>
718 * mips.h: Defines udi bits and masks. Add description of
719 characters which may appear in the args field of udi
722 2006-04-26 Thiemo Seufer <ths@networkno.de>
724 * mips.h: Improve comments describing the bitfield instruction
727 2006-04-26 Julian Brown <julian@codesourcery.com>
729 * arm.h (FPU_VFP_EXT_V3): Define constant.
730 (FPU_NEON_EXT_V1): Likewise.
731 (FPU_VFP_HARD): Update.
732 (FPU_VFP_V3): Define macro.
733 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
735 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
737 * avr.h (AVR_ISA_PWMx): New.
739 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
741 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
742 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
743 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
744 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
745 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
747 2006-03-10 Paul Brook <paul@codesourcery.com>
749 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
751 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
753 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
754 first. Correct mask of bb "B" opcode.
756 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
758 * i386.h (i386_optab): Support Intel Merom New Instructions.
760 2006-02-24 Paul Brook <paul@codesourcery.com>
762 * arm.h: Add V7 feature bits.
764 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
766 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
768 2006-01-31 Paul Brook <paul@codesourcery.com>
769 Richard Earnshaw <rearnsha@arm.com>
771 * arm.h: Use ARM_CPU_FEATURE.
772 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
773 (arm_feature_set): Change to a structure.
774 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
775 ARM_FEATURE): New macros.
777 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
779 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
780 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
781 (ADD_PC_INCR_OPCODE): Don't define.
783 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
786 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
788 2005-11-14 David Ung <davidu@mips.com>
790 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
791 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
792 save/restore encoding of the args field.
794 2005-10-28 Dave Brolley <brolley@redhat.com>
796 Contribute the following changes:
797 2005-02-16 Dave Brolley <brolley@redhat.com>
799 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
800 cgen_isa_mask_* to cgen_bitset_*.
803 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
805 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
806 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
807 (CGEN_CPU_TABLE): Make isas a ponter.
809 2003-09-29 Dave Brolley <brolley@redhat.com>
811 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
812 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
813 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
815 2002-12-13 Dave Brolley <brolley@redhat.com>
817 * cgen.h (symcat.h): #include it.
818 (cgen-bitset.h): #include it.
819 (CGEN_ATTR_VALUE_TYPE): Now a union.
820 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
821 (CGEN_ATTR_ENTRY): 'value' now unsigned.
822 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
823 * cgen-bitset.h: New file.
825 2005-09-30 Catherine Moore <clm@cm00re.com>
829 2005-10-24 Jan Beulich <jbeulich@novell.com>
831 * ia64.h (enum ia64_opnd): Move memory operand out of set of
834 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
836 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
837 Add FLAG_STRICT to pa10 ftest opcode.
839 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
841 * hppa.h (pa_opcodes): Remove lha entries.
843 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
845 * hppa.h (FLAG_STRICT): Revise comment.
846 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
847 before corresponding pa11 opcodes. Add strict pa10 register-immediate
850 2005-09-30 Catherine Moore <clm@cm00re.com>
854 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
856 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
858 2005-09-06 Chao-ying Fu <fu@mips.com>
860 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
861 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
863 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
864 (INSN_ASE_MASK): Update to include INSN_MT.
865 (INSN_MT): New define for MT ASE.
867 2005-08-25 Chao-ying Fu <fu@mips.com>
869 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
870 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
871 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
872 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
873 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
874 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
876 (INSN_DSP): New define for DSP ASE.
878 2005-08-18 Alan Modra <amodra@bigpond.net.au>
882 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
884 * ppc.h (PPC_OPCODE_E300): Define.
886 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
888 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
890 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
893 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
896 2005-07-27 Jan Beulich <jbeulich@novell.com>
898 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
899 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
900 Add movq-s as 64-bit variants of movd-s.
902 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
904 * hppa.h: Fix punctuation in comment.
906 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
907 implicit space-register addressing. Set space-register bits on opcodes
908 using implicit space-register addressing. Add various missing pa20
909 long-immediate opcodes. Remove various opcodes using implicit 3-bit
910 space-register addressing. Use "fE" instead of "fe" in various
913 2005-07-18 Jan Beulich <jbeulich@novell.com>
915 * i386.h (i386_optab): Operands of aam and aad are unsigned.
917 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
919 * i386.h (i386_optab): Support Intel VMX Instructions.
921 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
923 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
925 2005-07-05 Jan Beulich <jbeulich@novell.com>
927 * i386.h (i386_optab): Add new insns.
929 2005-07-01 Nick Clifton <nickc@redhat.com>
931 * sparc.h: Add typedefs to structure declarations.
933 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
936 * i386.h (i386_optab): Update comments for 64bit addressing on
937 mov. Allow 64bit addressing for mov and movq.
939 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
941 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
942 respectively, in various floating-point load and store patterns.
944 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
946 * hppa.h (FLAG_STRICT): Correct comment.
947 (pa_opcodes): Update load and store entries to allow both PA 1.X and
948 PA 2.0 mneumonics when equivalent. Entries with cache control
949 completers now require PA 1.1. Adjust whitespace.
951 2005-05-19 Anton Blanchard <anton@samba.org>
953 * ppc.h (PPC_OPCODE_POWER5): Define.
955 2005-05-10 Nick Clifton <nickc@redhat.com>
957 * Update the address and phone number of the FSF organization in
958 the GPL notices in the following files:
959 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
960 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
961 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
962 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
963 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
964 tic54x.h, tic80.h, v850.h, vax.h
966 2005-05-09 Jan Beulich <jbeulich@novell.com>
968 * i386.h (i386_optab): Add ht and hnt.
970 2005-04-18 Mark Kettenis <kettenis@gnu.org>
972 * i386.h: Insert hyphens into selected VIA PadLock extensions.
973 Add xcrypt-ctr. Provide aliases without hyphens.
975 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
977 Moved from ../ChangeLog
979 2005-04-12 Paul Brook <paul@codesourcery.com>
980 * m88k.h: Rename psr macros to avoid conflicts.
982 2005-03-12 Zack Weinberg <zack@codesourcery.com>
983 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
984 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
987 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
988 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
989 Remove redundant instruction types.
990 (struct argument): X_op - new field.
991 (struct cst4_entry): Remove.
992 (no_op_insn): Declare.
994 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
995 * crx.h (enum argtype): Rename types, remove unused types.
997 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
998 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
999 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1000 (enum operand_type): Rearrange operands, edit comments.
1001 replace us<N> with ui<N> for unsigned immediate.
1002 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1003 displacements (respectively).
1004 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1005 (instruction type): Add NO_TYPE_INS.
1006 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1007 (operand_entry): New field - 'flags'.
1008 (operand flags): New.
1010 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1011 * crx.h (operand_type): Remove redundant types i3, i4,
1013 Add new unsigned immediate types us3, us4, us5, us16.
1015 2005-04-12 Mark Kettenis <kettenis@gnu.org>
1017 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1018 adjust them accordingly.
1020 2005-04-01 Jan Beulich <jbeulich@novell.com>
1022 * i386.h (i386_optab): Add rdtscp.
1024 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1026 * i386.h (i386_optab): Don't allow the `l' suffix for moving
1027 between memory and segment register. Allow movq for moving between
1028 general-purpose register and segment register.
1030 2005-02-09 Jan Beulich <jbeulich@novell.com>
1033 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1034 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1037 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1039 * m68k.h (m68008, m68ec030, m68882): Remove.
1041 (cpu_m68k, cpu_cf): New.
1042 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1043 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1045 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
1047 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1048 * cgen.h (enum cgen_parse_operand_type): Add
1049 CGEN_PARSE_OPERAND_SYMBOLIC.
1051 2005-01-21 Fred Fish <fnf@specifixinc.com>
1053 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1054 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1055 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1057 2005-01-19 Fred Fish <fnf@specifixinc.com>
1059 * mips.h (struct mips_opcode): Add new pinfo2 member.
1060 (INSN_ALIAS): New define for opcode table entries that are
1061 specific instances of another entry, such as 'move' for an 'or'
1062 with a zero operand.
1063 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1064 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1066 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1068 * mips.h (CPU_RM9000): Define.
1069 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1071 2004-11-25 Jan Beulich <jbeulich@novell.com>
1073 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1074 to/from test registers are illegal in 64-bit mode. Add missing
1075 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1076 (previously one had to explicitly encode a rex64 prefix). Re-enable
1077 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1078 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1080 2004-11-23 Jan Beulich <jbeulich@novell.com>
1082 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1083 available only with SSE2. Change the MMX additions introduced by SSE
1084 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1085 instructions by their now designated identifier (since combining i686
1086 and 3DNow! does not really imply 3DNow!A).
1088 2004-11-19 Alan Modra <amodra@bigpond.net.au>
1090 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1091 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1093 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1094 Vineet Sharma <vineets@noida.hcltech.com>
1096 * maxq.h: New file: Disassembly information for the maxq port.
1098 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1100 * i386.h (i386_optab): Put back "movzb".
1102 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
1104 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1105 comments. Remove member cris_ver_sim. Add members
1106 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1107 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1108 (struct cris_support_reg, struct cris_cond15): New types.
1109 (cris_conds15): Declare.
1110 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1111 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1112 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1113 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1114 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1115 SIZE_FIELD_UNSIGNED.
1117 2004-11-04 Jan Beulich <jbeulich@novell.com>
1119 * i386.h (sldx_Suf): Remove.
1120 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1121 (q_FP): Define, implying no REX64.
1122 (x_FP, sl_FP): Imply FloatMF.
1123 (i386_optab): Split reg and mem forms of moving from segment registers
1124 so that the memory forms can ignore the 16-/32-bit operand size
1125 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1126 all non-floating-point instructions. Unite 32- and 64-bit forms of
1127 movsx, movzx, and movd. Adjust floating point operations for the above
1128 changes to the *FP macros. Add DefaultSize to floating point control
1129 insns operating on larger memory ranges. Remove left over comments
1130 hinting at certain insns being Intel-syntax ones where the ones
1131 actually meant are already gone.
1133 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1135 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1138 2004-09-30 Paul Brook <paul@codesourcery.com>
1140 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1141 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1143 2004-09-11 Theodore A. Roth <troth@openavr.org>
1145 * avr.h: Add support for
1146 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1148 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1150 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1152 2004-08-24 Dmitry Diky <diwil@spec.ru>
1154 * msp430.h (msp430_opc): Add new instructions.
1155 (msp430_rcodes): Declare new instructions.
1156 (msp430_hcodes): Likewise..
1158 2004-08-13 Nick Clifton <nickc@redhat.com>
1161 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1164 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1166 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1168 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1170 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1172 2004-07-21 Jan Beulich <jbeulich@novell.com>
1174 * i386.h: Adjust instruction descriptions to better match the
1177 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
1179 * arm.h: Remove all old content. Replace with architecture defines
1180 from gas/config/tc-arm.c.
1182 2004-07-09 Andreas Schwab <schwab@suse.de>
1184 * m68k.h: Fix comment.
1186 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1190 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1192 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1194 2004-05-24 Peter Barada <peter@the-baradas.com>
1196 * m68k.h: Add 'size' to m68k_opcode.
1198 2004-05-05 Peter Barada <peter@the-baradas.com>
1200 * m68k.h: Switch from ColdFire chip name to core variant.
1202 2004-04-22 Peter Barada <peter@the-baradas.com>
1204 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1205 descriptions for new EMAC cases.
1206 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1207 handle Motorola MAC syntax.
1208 Allow disassembly of ColdFire V4e object files.
1210 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1212 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1214 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1216 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1218 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1220 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1222 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1224 * i386.h (i386_optab): Added xstore/xcrypt insns.
1226 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1228 * h8300.h (32bit ldc/stc): Add relaxing support.
1230 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1232 * h8300.h (BITOP): Pass MEMRELAX flag.
1234 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1236 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1239 For older changes see ChangeLog-9103
1245 version-control: never