1 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
3 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
4 (make_instruction,match_opcode): Added function prototypes.
5 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
7 2012-11-23 Alan Modra <amodra@gmail.com>
9 * ppc.h (ppc_parse_cpu): Update prototype.
11 2012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
13 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
14 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
16 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
18 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
20 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
22 * ia64.h (ia64_opnd): Add new operand types.
24 2012-08-21 David S. Miller <davem@davemloft.net>
26 * sparc.h (F3F4): New macro.
28 2012-08-13 Ian Bolton <ian.bolton@arm.com>
29 Laurent Desnogues <laurent.desnogues@arm.com>
30 Jim MacArthur <jim.macarthur@arm.com>
31 Marcus Shawcroft <marcus.shawcroft@arm.com>
32 Nigel Stephens <nigel.stephens@arm.com>
33 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
34 Richard Earnshaw <rearnsha@arm.com>
35 Sofiane Naci <sofiane.naci@arm.com>
36 Tejas Belagod <tejas.belagod@arm.com>
37 Yufeng Zhang <yufeng.zhang@arm.com>
39 * aarch64.h: New file.
41 2012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
42 Maciej W. Rozycki <macro@codesourcery.com>
44 * mips.h (mips_opcode): Add the exclusions field.
45 (OPCODE_IS_MEMBER): Remove macro.
46 (cpu_is_member): New inline function.
47 (opcode_is_member): Likewise.
49 2012-07-31 Chao-Ying Fu <fu@mips.com>
50 Catherine Moore <clm@codesourcery.com>
51 Maciej W. Rozycki <macro@codesourcery.com>
53 * mips.h: Document microMIPS DSP ASE usage.
54 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
55 microMIPS DSP ASE support.
56 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
57 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
58 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
59 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
60 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
61 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
62 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
64 2012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
66 * mips.h: Fix a typo in description.
68 2012-06-07 Georg-Johann Lay <avr@gjlay.de>
70 * avr.h: (AVR_ISA_XCH): New define.
71 (AVR_ISA_XMEGA): Use it.
72 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
74 2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
76 * m68hc11.h: Add XGate definitions.
77 (struct m68hc11_opcode): Add xg_mask field.
79 2012-05-14 Catherine Moore <clm@codesourcery.com>
80 Maciej W. Rozycki <macro@codesourcery.com>
81 Rhonda Wittels <rhonda@codesourcery.com>
83 * ppc.h (PPC_OPCODE_VLE): New definition.
84 (PPC_OP_SA): New macro.
85 (PPC_OP_SE_VLE): New macro.
86 (PPC_OP): Use a variable shift amount.
87 (powerpc_operand): Update comments.
88 (PPC_OPSHIFT_INV): New macro.
89 (PPC_OPERAND_CR): Replace with...
90 (PPC_OPERAND_CR_BIT): ...this and
91 (PPC_OPERAND_CR_REG): ...this.
94 2012-05-03 Sean Keys <skeys@ipdatasys.com>
96 * xgate.h: Header file for XGATE assembler.
98 2012-04-27 David S. Miller <davem@davemloft.net>
100 * sparc.h: Document new arg code' )' for crypto RS3
103 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
104 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
105 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
106 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
107 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
108 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
109 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
110 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
111 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
112 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
113 HWCAP_CBCOND, HWCAP_CRC32): New defines.
115 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
117 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
119 2012-02-27 Alan Modra <amodra@gmail.com>
121 * crx.h (cst4_map): Update declaration.
123 2012-02-25 Walter Lee <walt@tilera.com>
125 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
127 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
128 TILEPRO_OPC_LW_TLS_SN.
130 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
132 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
133 (XRELEASE_PREFIX_OPCODE): Likewise.
135 2011-12-08 Andrew Pinski <apinski@cavium.com>
136 Adam Nemet <anemet@caviumnetworks.com>
138 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
139 (INSN_OCTEON2): New macro.
140 (CPU_OCTEON2): New macro.
141 (OPCODE_IS_MEMBER): Add Octeon2.
143 2011-11-29 Andrew Pinski <apinski@cavium.com>
145 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
146 (INSN_OCTEONP): New macro.
147 (CPU_OCTEONP): New macro.
148 (OPCODE_IS_MEMBER): Add Octeon+.
149 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
151 2011-11-01 DJ Delorie <dj@redhat.com>
155 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
157 * mips.h: Fix a typo in description.
159 2011-09-21 David S. Miller <davem@davemloft.net>
161 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
162 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
163 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
164 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
166 2011-08-09 Chao-ying Fu <fu@mips.com>
167 Maciej W. Rozycki <macro@codesourcery.com>
169 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
170 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
171 (INSN_ASE_MASK): Add the MCU bit.
172 (INSN_MCU): New macro.
173 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
174 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
176 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
178 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
179 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
180 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
181 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
182 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
183 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
184 (INSN2_READ_GPR_MMN): Likewise.
185 (INSN2_READ_FPR_D): Change the bit used.
186 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
187 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
188 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
189 (INSN2_COND_BRANCH): Likewise.
190 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
191 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
192 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
193 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
194 (INSN2_MOD_GPR_MN): Likewise.
196 2011-08-05 David S. Miller <davem@davemloft.net>
198 * sparc.h: Document new format codes '4', '5', and '('.
199 (OPF_LOW4, RS3): New macros.
201 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
203 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
204 order of flags documented.
206 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
208 * mips.h: Clarify the description of microMIPS instruction
210 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
212 2011-07-24 Chao-ying Fu <fu@mips.com>
213 Maciej W. Rozycki <macro@codesourcery.com>
215 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
216 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
217 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
218 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
219 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
220 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
221 (OP_MASK_RS3, OP_SH_RS3): Likewise.
222 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
223 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
224 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
225 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
226 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
227 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
228 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
229 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
230 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
231 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
232 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
233 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
234 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
235 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
236 (INSN_WRITE_GPR_S): New macro.
237 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
238 (INSN2_READ_FPR_D): Likewise.
239 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
240 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
241 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
242 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
243 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
244 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
245 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
246 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
247 (CPU_MICROMIPS): New macro.
248 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
249 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
250 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
251 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
252 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
253 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
254 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
255 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
256 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
257 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
258 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
259 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
260 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
261 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
262 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
263 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
264 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
265 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
266 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
267 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
268 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
269 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
270 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
271 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
272 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
273 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
274 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
275 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
276 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
277 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
278 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
279 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
280 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
281 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
282 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
283 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
284 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
285 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
286 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
287 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
288 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
289 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
290 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
291 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
292 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
293 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
294 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
295 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
296 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
297 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
298 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
299 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
300 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
301 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
302 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
303 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
304 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
305 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
306 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
307 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
308 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
309 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
310 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
311 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
312 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
313 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
314 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
315 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
316 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
317 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
318 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
319 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
320 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
321 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
322 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
323 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
324 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
325 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
326 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
327 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
328 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
329 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
330 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
331 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
332 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
333 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
334 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
335 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
336 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
337 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
338 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
339 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
340 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
341 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
342 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
343 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
344 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
345 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
346 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
347 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
348 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
349 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
350 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
351 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
352 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
353 (micromips_opcodes): New declaration.
354 (bfd_micromips_num_opcodes): Likewise.
356 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
358 * mips.h (INSN_TRAP): Rename to...
359 (INSN_NO_DELAY_SLOT): ... this.
360 (INSN_SYNC): Remove macro.
362 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
364 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
365 a duplicate of AVR_ISA_SPM.
367 2011-07-01 Nick Clifton <nickc@redhat.com>
369 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
371 2011-06-18 Robin Getz <robin.getz@analog.com>
373 * bfin.h (is_macmod_signed): New func
375 2011-06-18 Mike Frysinger <vapier@gentoo.org>
377 * bfin.h (is_macmod_pmove): Add missing space before func args.
378 (is_macmod_hmove): Likewise.
380 2011-06-13 Walter Lee <walt@tilera.com>
382 * tilegx.h: New file.
383 * tilepro.h: New file.
385 2011-05-31 Paul Brook <paul@codesourcery.com>
387 * arm.h (ARM_ARCH_V7R_IDIV): Define.
389 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
391 * s390.h: Replace S390_OPERAND_REG_EVEN with
392 S390_OPERAND_REG_PAIR.
394 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
396 * s390.h: Add S390_OPCODE_REG_EVEN flag.
398 2011-04-18 Julian Brown <julian@codesourcery.com>
400 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
402 2011-04-11 Dan McDonald <dan@wellkeeper.com>
405 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
407 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
409 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
410 New instruction set flags.
411 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
413 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
415 * mips.h (M_PREF_AB): New enum value.
417 2011-02-12 Mike Frysinger <vapier@gentoo.org>
419 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
421 (is_macmod_pmove, is_macmod_hmove): New functions.
423 2011-02-11 Mike Frysinger <vapier@gentoo.org>
425 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
427 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
429 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
430 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
432 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
435 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
438 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
441 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
443 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
445 * mips.h: Update commentary after last commit.
447 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
449 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
450 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
451 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
453 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
455 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
457 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
459 * mips.h: Fix previous commit.
461 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
463 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
464 (INSN_LOONGSON_3A): Clear bit 31.
466 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
469 * arm.h (ARM_AEXT_V6M_ONLY): New define.
470 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
471 (ARM_ARCH_V6M_ONLY): New define.
473 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
475 * mips.h (INSN_LOONGSON_3A): Defined.
476 (CPU_LOONGSON_3A): Defined.
477 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
479 2010-10-09 Matt Rice <ratmice@gmail.com>
481 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
482 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
484 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
486 * arm.h (ARM_EXT_VIRT): New define.
487 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
488 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
491 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
493 * arm.h (ARM_AEXT_ADIV): New define.
494 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
496 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
498 * arm.h (ARM_EXT_OS): New define.
499 (ARM_AEXT_V6SM): Likewise.
500 (ARM_ARCH_V6SM): Likewise.
502 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
504 * arm.h (ARM_EXT_MP): Add.
505 (ARM_ARCH_V7A_MP): Likewise.
507 2010-09-22 Mike Frysinger <vapier@gentoo.org>
509 * bfin.h: Declare pseudoChr structs/defines.
511 2010-09-21 Mike Frysinger <vapier@gentoo.org>
513 * bfin.h: Strip trailing whitespace.
515 2010-07-29 DJ Delorie <dj@redhat.com>
517 * rx.h (RX_Operand_Type): Add TwoReg.
518 (RX_Opcode_ID): Remove ediv and ediv2.
520 2010-07-27 DJ Delorie <dj@redhat.com>
522 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
524 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
525 Ina Pandit <ina.pandit@kpitcummins.com>
527 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
528 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
529 PROCESSOR_V850E2_ALL.
530 Remove PROCESSOR_V850EA support.
531 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
532 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
533 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
534 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
535 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
536 V850_OPERAND_PERCENT.
537 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
539 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
542 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
544 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
545 (MIPS16_INSN_BRANCH): Rename to...
546 (MIPS16_INSN_COND_BRANCH): ... this.
548 2010-07-03 Alan Modra <amodra@gmail.com>
550 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
551 Renumber other PPC_OPCODE defines.
553 2010-07-03 Alan Modra <amodra@gmail.com>
555 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
557 2010-06-29 Alan Modra <amodra@gmail.com>
559 * maxq.h: Delete file.
561 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
563 * ppc.h (PPC_OPCODE_E500): Define.
565 2010-05-26 Catherine Moore <clm@codesourcery.com>
567 * opcode/mips.h (INSN_MIPS16): Remove.
569 2010-04-21 Joseph Myers <joseph@codesourcery.com>
571 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
573 2010-04-15 Nick Clifton <nickc@redhat.com>
575 * alpha.h: Update copyright notice to use GPLv3.
581 * convex.h: Likewise.
595 * m68hc11.h: Likewise.
601 * mn10200.h: Likewise.
602 * mn10300.h: Likewise.
603 * msp430.h: Likewise.
614 * score-datadep.h: Likewise.
615 * score-inst.h: Likewise.
617 * spu-insns.h: Likewise.
621 * tic54x.h: Likewise.
626 2010-03-25 Joseph Myers <joseph@codesourcery.com>
628 * tic6x-control-registers.h, tic6x-insn-formats.h,
629 tic6x-opcode-table.h, tic6x.h: New.
631 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
633 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
635 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
637 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
639 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
641 * ia64.h (ia64_find_opcode): Remove argument name.
642 (ia64_find_next_opcode): Likewise.
643 (ia64_dis_opcode): Likewise.
644 (ia64_free_opcode): Likewise.
645 (ia64_find_dependency): Likewise.
647 2009-11-22 Doug Evans <dje@sebabeach.org>
649 * cgen.h: Include bfd_stdint.h.
650 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
652 2009-11-18 Paul Brook <paul@codesourcery.com>
654 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
656 2009-11-17 Paul Brook <paul@codesourcery.com>
657 Daniel Jacobowitz <dan@codesourcery.com>
659 * arm.h (ARM_EXT_V6_DSP): Define.
660 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
661 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
663 2009-11-04 DJ Delorie <dj@redhat.com>
665 * rx.h (rx_decode_opcode) (mvtipl): Add.
666 (mvtcp, mvfcp, opecp): Remove.
668 2009-11-02 Paul Brook <paul@codesourcery.com>
670 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
671 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
672 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
673 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
674 FPU_ARCH_NEON_VFP_V4): Define.
676 2009-10-23 Doug Evans <dje@sebabeach.org>
678 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
679 * cgen.h: Update. Improve multi-inclusion macro name.
681 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
683 * ppc.h (PPC_OPCODE_476): Define.
685 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
687 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
689 2009-09-29 DJ Delorie <dj@redhat.com>
693 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
695 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
697 2009-09-21 Ben Elliston <bje@au.ibm.com>
699 * ppc.h (PPC_OPCODE_PPCA2): New.
701 2009-09-05 Martin Thuresson <martin@mtme.org>
703 * ia64.h (struct ia64_operand): Renamed member class to op_class.
705 2009-08-29 Martin Thuresson <martin@mtme.org>
707 * tic30.h (template): Rename type template to
708 insn_template. Updated code to use new name.
709 * tic54x.h (template): Rename type template to
712 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
714 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
716 2009-06-11 Anthony Green <green@moxielogic.com>
718 * moxie.h (MOXIE_F3_PCREL): Define.
719 (moxie_form3_opc_info): Grow.
721 2009-06-06 Anthony Green <green@moxielogic.com>
723 * moxie.h (MOXIE_F1_M): Define.
725 2009-04-15 Anthony Green <green@moxielogic.com>
729 2009-04-06 DJ Delorie <dj@redhat.com>
731 * h8300.h: Add relaxation attributes to MOVA opcodes.
733 2009-03-10 Alan Modra <amodra@bigpond.net.au>
735 * ppc.h (ppc_parse_cpu): Declare.
737 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
739 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
740 and _IMM11 for mbitclr and mbitset.
741 * score-datadep.h: Update dependency information.
743 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
745 * ppc.h (PPC_OPCODE_POWER7): New.
747 2009-02-06 Doug Evans <dje@google.com>
749 * i386.h: Add comment regarding sse* insns and prefixes.
751 2009-02-03 Sandip Matte <sandip@rmicorp.com>
753 * mips.h (INSN_XLR): Define.
754 (INSN_CHIP_MASK): Update.
756 (OPCODE_IS_MEMBER): Update.
757 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
759 2009-01-28 Doug Evans <dje@google.com>
761 * opcode/i386.h: Add multiple inclusion protection.
762 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
763 (EDI_REG_NUM): New macros.
764 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
765 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
766 (REX_PREFIX_P): New macro.
768 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
770 * ppc.h (struct powerpc_opcode): New field "deprecated".
771 (PPC_OPCODE_NOPOWER4): Delete.
773 2008-11-28 Joshua Kinard <kumba@gentoo.org>
775 * mips.h: Define CPU_R14000, CPU_R16000.
776 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
778 2008-11-18 Catherine Moore <clm@codesourcery.com>
780 * arm.h (FPU_NEON_FP16): New.
781 (FPU_ARCH_NEON_FP16): New.
783 2008-11-06 Chao-ying Fu <fu@mips.com>
785 * mips.h: Doucument '1' for 5-bit sync type.
787 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
789 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
792 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
794 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
796 2008-07-30 Michael J. Eager <eager@eagercon.com>
798 * ppc.h (PPC_OPCODE_405): Define.
799 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
801 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
803 * ppc.h (ppc_cpu_t): New typedef.
804 (struct powerpc_opcode <flags>): Use it.
805 (struct powerpc_operand <insert, extract>): Likewise.
806 (struct powerpc_macro <flags>): Likewise.
808 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
810 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
811 Update comment before MIPS16 field descriptors to mention MIPS16.
812 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
814 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
815 New bit masks and shift counts for cins and exts.
817 * mips.h: Document new field descriptors +Q.
818 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
820 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
822 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
823 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
825 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
827 * ppc.h: (PPC_OPCODE_E500MC): New.
829 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
831 * i386.h (MAX_OPERANDS): Set to 5.
832 (MAX_MNEM_SIZE): Changed to 20.
834 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
836 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
838 2008-03-09 Paul Brook <paul@codesourcery.com>
840 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
842 2008-03-04 Paul Brook <paul@codesourcery.com>
844 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
845 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
846 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
848 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
849 Nick Clifton <nickc@redhat.com>
852 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
853 with a 32-bit displacement but without the top bit of the 4th byte
856 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
858 * cr16.h (cr16_num_optab): Declared.
860 2008-02-14 Hakan Ardo <hakan@debian.org>
863 * avr.h (AVR_ISA_2xxe): Define.
865 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
867 * mips.h: Update copyright.
868 (INSN_CHIP_MASK): New macro.
869 (INSN_OCTEON): New macro.
870 (CPU_OCTEON): New macro.
871 (OPCODE_IS_MEMBER): Handle Octeon instructions.
873 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
875 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
877 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
879 * avr.h (AVR_ISA_USB162): Add new opcode set.
880 (AVR_ISA_AVR3): Likewise.
882 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
884 * mips.h (INSN_LOONGSON_2E): New.
885 (INSN_LOONGSON_2F): New.
886 (CPU_LOONGSON_2E): New.
887 (CPU_LOONGSON_2F): New.
888 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
890 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
892 * mips.h (INSN_ISA*): Redefine certain values as an
893 enumeration. Update comments.
894 (mips_isa_table): New.
895 (ISA_MIPS*): Redefine to match enumeration.
896 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
899 2007-08-08 Ben Elliston <bje@au.ibm.com>
901 * ppc.h (PPC_OPCODE_PPCPS): New.
903 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
905 * m68k.h: Document j K & E.
907 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
909 * cr16.h: New file for CR16 target.
911 2007-05-02 Alan Modra <amodra@bigpond.net.au>
913 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
915 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
917 * m68k.h (mcfisa_c): New.
918 (mcfusp, mcf_mask): Adjust.
920 2007-04-20 Alan Modra <amodra@bigpond.net.au>
922 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
923 (num_powerpc_operands): Declare.
924 (PPC_OPERAND_SIGNED et al): Redefine as hex.
925 (PPC_OPERAND_PLUS1): Define.
927 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
929 * i386.h (REX_MODE64): Renamed to ...
931 (REX_EXTX): Renamed to ...
933 (REX_EXTY): Renamed to ...
935 (REX_EXTZ): Renamed to ...
938 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
940 * i386.h: Add entries from config/tc-i386.h and move tables
941 to opcodes/i386-opc.h.
943 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
945 * i386.h (FloatDR): Removed.
946 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
948 2007-03-01 Alan Modra <amodra@bigpond.net.au>
950 * spu-insns.h: Add soma double-float insns.
952 2007-02-20 Thiemo Seufer <ths@mips.com>
953 Chao-Ying Fu <fu@mips.com>
955 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
956 (INSN_DSPR2): Add flag for DSP R2 instructions.
957 (M_BALIGN): New macro.
959 2007-02-14 Alan Modra <amodra@bigpond.net.au>
961 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
962 and Seg3ShortFrom with Shortform.
964 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
967 * i386.h (i386_optab): Put the real "test" before the pseudo
970 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
972 * m68k.h (m68010up): OR fido_a.
974 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
976 * m68k.h (fido_a): New.
978 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
980 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
981 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
984 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
986 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
988 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
990 * score-inst.h (enum score_insn_type): Add Insn_internal.
992 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
993 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
994 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
995 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
996 Alan Modra <amodra@bigpond.net.au>
998 * spu-insns.h: New file.
1001 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1003 * ppc.h (PPC_OPCODE_CELL): Define.
1005 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1007 * i386.h : Modify opcode to support for the change in POPCNT opcode
1008 in amdfam10 architecture.
1010 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1012 * i386.h: Replace CpuMNI with CpuSSSE3.
1014 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
1015 Joseph Myers <joseph@codesourcery.com>
1016 Ian Lance Taylor <ian@wasabisystems.com>
1017 Ben Elliston <bje@wasabisystems.com>
1019 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1021 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1023 * score-datadep.h: New file.
1024 * score-inst.h: New file.
1026 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1028 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1029 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1030 movdq2q and movq2dq.
1032 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1033 Michael Meissner <michael.meissner@amd.com>
1035 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1037 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1039 * i386.h (i386_optab): Add "nop" with memory reference.
1041 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1043 * i386.h (i386_optab): Update comment for 64bit NOP.
1045 2006-06-06 Ben Elliston <bje@au.ibm.com>
1046 Anton Blanchard <anton@samba.org>
1048 * ppc.h (PPC_OPCODE_POWER6): Define.
1051 2006-06-05 Thiemo Seufer <ths@mips.com>
1053 * mips.h: Improve description of MT flags.
1055 2006-05-25 Richard Sandiford <richard@codesourcery.com>
1057 * m68k.h (mcf_mask): Define.
1059 2006-05-05 Thiemo Seufer <ths@mips.com>
1060 David Ung <davidu@mips.com>
1062 * mips.h (enum): Add macro M_CACHE_AB.
1064 2006-05-04 Thiemo Seufer <ths@mips.com>
1065 Nigel Stephens <nigel@mips.com>
1066 David Ung <davidu@mips.com>
1068 * mips.h: Add INSN_SMARTMIPS define.
1070 2006-04-30 Thiemo Seufer <ths@mips.com>
1071 David Ung <davidu@mips.com>
1073 * mips.h: Defines udi bits and masks. Add description of
1074 characters which may appear in the args field of udi
1077 2006-04-26 Thiemo Seufer <ths@networkno.de>
1079 * mips.h: Improve comments describing the bitfield instruction
1082 2006-04-26 Julian Brown <julian@codesourcery.com>
1084 * arm.h (FPU_VFP_EXT_V3): Define constant.
1085 (FPU_NEON_EXT_V1): Likewise.
1086 (FPU_VFP_HARD): Update.
1087 (FPU_VFP_V3): Define macro.
1088 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1090 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
1092 * avr.h (AVR_ISA_PWMx): New.
1094 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1096 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1097 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1098 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1099 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1100 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1102 2006-03-10 Paul Brook <paul@codesourcery.com>
1104 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1106 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1108 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1109 first. Correct mask of bb "B" opcode.
1111 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1113 * i386.h (i386_optab): Support Intel Merom New Instructions.
1115 2006-02-24 Paul Brook <paul@codesourcery.com>
1117 * arm.h: Add V7 feature bits.
1119 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1121 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1123 2006-01-31 Paul Brook <paul@codesourcery.com>
1124 Richard Earnshaw <rearnsha@arm.com>
1126 * arm.h: Use ARM_CPU_FEATURE.
1127 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1128 (arm_feature_set): Change to a structure.
1129 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1130 ARM_FEATURE): New macros.
1132 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
1134 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1135 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1136 (ADD_PC_INCR_OPCODE): Don't define.
1138 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1141 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1143 2005-11-14 David Ung <davidu@mips.com>
1145 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1146 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1147 save/restore encoding of the args field.
1149 2005-10-28 Dave Brolley <brolley@redhat.com>
1151 Contribute the following changes:
1152 2005-02-16 Dave Brolley <brolley@redhat.com>
1154 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1155 cgen_isa_mask_* to cgen_bitset_*.
1158 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1160 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1161 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1162 (CGEN_CPU_TABLE): Make isas a ponter.
1164 2003-09-29 Dave Brolley <brolley@redhat.com>
1166 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1167 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1168 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1170 2002-12-13 Dave Brolley <brolley@redhat.com>
1172 * cgen.h (symcat.h): #include it.
1173 (cgen-bitset.h): #include it.
1174 (CGEN_ATTR_VALUE_TYPE): Now a union.
1175 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1176 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1177 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1178 * cgen-bitset.h: New file.
1180 2005-09-30 Catherine Moore <clm@cm00re.com>
1184 2005-10-24 Jan Beulich <jbeulich@novell.com>
1186 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1189 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1191 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1192 Add FLAG_STRICT to pa10 ftest opcode.
1194 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1196 * hppa.h (pa_opcodes): Remove lha entries.
1198 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1200 * hppa.h (FLAG_STRICT): Revise comment.
1201 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1202 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1205 2005-09-30 Catherine Moore <clm@cm00re.com>
1209 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1211 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1213 2005-09-06 Chao-ying Fu <fu@mips.com>
1215 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1216 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1218 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1219 (INSN_ASE_MASK): Update to include INSN_MT.
1220 (INSN_MT): New define for MT ASE.
1222 2005-08-25 Chao-ying Fu <fu@mips.com>
1224 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1225 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1226 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1227 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1228 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1229 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1231 (INSN_DSP): New define for DSP ASE.
1233 2005-08-18 Alan Modra <amodra@bigpond.net.au>
1237 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1239 * ppc.h (PPC_OPCODE_E300): Define.
1241 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1243 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1245 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1248 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1251 2005-07-27 Jan Beulich <jbeulich@novell.com>
1253 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1254 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1255 Add movq-s as 64-bit variants of movd-s.
1257 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1259 * hppa.h: Fix punctuation in comment.
1261 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1262 implicit space-register addressing. Set space-register bits on opcodes
1263 using implicit space-register addressing. Add various missing pa20
1264 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1265 space-register addressing. Use "fE" instead of "fe" in various
1268 2005-07-18 Jan Beulich <jbeulich@novell.com>
1270 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1272 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1274 * i386.h (i386_optab): Support Intel VMX Instructions.
1276 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1278 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1280 2005-07-05 Jan Beulich <jbeulich@novell.com>
1282 * i386.h (i386_optab): Add new insns.
1284 2005-07-01 Nick Clifton <nickc@redhat.com>
1286 * sparc.h: Add typedefs to structure declarations.
1288 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1291 * i386.h (i386_optab): Update comments for 64bit addressing on
1292 mov. Allow 64bit addressing for mov and movq.
1294 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1296 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1297 respectively, in various floating-point load and store patterns.
1299 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1301 * hppa.h (FLAG_STRICT): Correct comment.
1302 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1303 PA 2.0 mneumonics when equivalent. Entries with cache control
1304 completers now require PA 1.1. Adjust whitespace.
1306 2005-05-19 Anton Blanchard <anton@samba.org>
1308 * ppc.h (PPC_OPCODE_POWER5): Define.
1310 2005-05-10 Nick Clifton <nickc@redhat.com>
1312 * Update the address and phone number of the FSF organization in
1313 the GPL notices in the following files:
1314 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1315 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1316 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1317 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1318 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1319 tic54x.h, tic80.h, v850.h, vax.h
1321 2005-05-09 Jan Beulich <jbeulich@novell.com>
1323 * i386.h (i386_optab): Add ht and hnt.
1325 2005-04-18 Mark Kettenis <kettenis@gnu.org>
1327 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1328 Add xcrypt-ctr. Provide aliases without hyphens.
1330 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1332 Moved from ../ChangeLog
1334 2005-04-12 Paul Brook <paul@codesourcery.com>
1335 * m88k.h: Rename psr macros to avoid conflicts.
1337 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1338 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1339 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1340 and ARM_ARCH_V6ZKT2.
1342 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1343 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1344 Remove redundant instruction types.
1345 (struct argument): X_op - new field.
1346 (struct cst4_entry): Remove.
1347 (no_op_insn): Declare.
1349 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1350 * crx.h (enum argtype): Rename types, remove unused types.
1352 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1353 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1354 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1355 (enum operand_type): Rearrange operands, edit comments.
1356 replace us<N> with ui<N> for unsigned immediate.
1357 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1358 displacements (respectively).
1359 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1360 (instruction type): Add NO_TYPE_INS.
1361 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1362 (operand_entry): New field - 'flags'.
1363 (operand flags): New.
1365 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1366 * crx.h (operand_type): Remove redundant types i3, i4,
1368 Add new unsigned immediate types us3, us4, us5, us16.
1370 2005-04-12 Mark Kettenis <kettenis@gnu.org>
1372 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1373 adjust them accordingly.
1375 2005-04-01 Jan Beulich <jbeulich@novell.com>
1377 * i386.h (i386_optab): Add rdtscp.
1379 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1381 * i386.h (i386_optab): Don't allow the `l' suffix for moving
1382 between memory and segment register. Allow movq for moving between
1383 general-purpose register and segment register.
1385 2005-02-09 Jan Beulich <jbeulich@novell.com>
1388 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1389 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1392 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1394 * m68k.h (m68008, m68ec030, m68882): Remove.
1396 (cpu_m68k, cpu_cf): New.
1397 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1398 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1400 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
1402 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1403 * cgen.h (enum cgen_parse_operand_type): Add
1404 CGEN_PARSE_OPERAND_SYMBOLIC.
1406 2005-01-21 Fred Fish <fnf@specifixinc.com>
1408 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1409 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1410 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1412 2005-01-19 Fred Fish <fnf@specifixinc.com>
1414 * mips.h (struct mips_opcode): Add new pinfo2 member.
1415 (INSN_ALIAS): New define for opcode table entries that are
1416 specific instances of another entry, such as 'move' for an 'or'
1417 with a zero operand.
1418 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1419 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1421 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1423 * mips.h (CPU_RM9000): Define.
1424 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1426 2004-11-25 Jan Beulich <jbeulich@novell.com>
1428 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1429 to/from test registers are illegal in 64-bit mode. Add missing
1430 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1431 (previously one had to explicitly encode a rex64 prefix). Re-enable
1432 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1433 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1435 2004-11-23 Jan Beulich <jbeulich@novell.com>
1437 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1438 available only with SSE2. Change the MMX additions introduced by SSE
1439 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1440 instructions by their now designated identifier (since combining i686
1441 and 3DNow! does not really imply 3DNow!A).
1443 2004-11-19 Alan Modra <amodra@bigpond.net.au>
1445 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1446 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1448 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1449 Vineet Sharma <vineets@noida.hcltech.com>
1451 * maxq.h: New file: Disassembly information for the maxq port.
1453 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1455 * i386.h (i386_optab): Put back "movzb".
1457 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
1459 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1460 comments. Remove member cris_ver_sim. Add members
1461 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1462 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1463 (struct cris_support_reg, struct cris_cond15): New types.
1464 (cris_conds15): Declare.
1465 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1466 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1467 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1468 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1469 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1470 SIZE_FIELD_UNSIGNED.
1472 2004-11-04 Jan Beulich <jbeulich@novell.com>
1474 * i386.h (sldx_Suf): Remove.
1475 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1476 (q_FP): Define, implying no REX64.
1477 (x_FP, sl_FP): Imply FloatMF.
1478 (i386_optab): Split reg and mem forms of moving from segment registers
1479 so that the memory forms can ignore the 16-/32-bit operand size
1480 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1481 all non-floating-point instructions. Unite 32- and 64-bit forms of
1482 movsx, movzx, and movd. Adjust floating point operations for the above
1483 changes to the *FP macros. Add DefaultSize to floating point control
1484 insns operating on larger memory ranges. Remove left over comments
1485 hinting at certain insns being Intel-syntax ones where the ones
1486 actually meant are already gone.
1488 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1490 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1493 2004-09-30 Paul Brook <paul@codesourcery.com>
1495 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1496 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1498 2004-09-11 Theodore A. Roth <troth@openavr.org>
1500 * avr.h: Add support for
1501 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1503 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1505 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1507 2004-08-24 Dmitry Diky <diwil@spec.ru>
1509 * msp430.h (msp430_opc): Add new instructions.
1510 (msp430_rcodes): Declare new instructions.
1511 (msp430_hcodes): Likewise..
1513 2004-08-13 Nick Clifton <nickc@redhat.com>
1516 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1519 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1521 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1523 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1525 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1527 2004-07-21 Jan Beulich <jbeulich@novell.com>
1529 * i386.h: Adjust instruction descriptions to better match the
1532 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
1534 * arm.h: Remove all old content. Replace with architecture defines
1535 from gas/config/tc-arm.c.
1537 2004-07-09 Andreas Schwab <schwab@suse.de>
1539 * m68k.h: Fix comment.
1541 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1545 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1547 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1549 2004-05-24 Peter Barada <peter@the-baradas.com>
1551 * m68k.h: Add 'size' to m68k_opcode.
1553 2004-05-05 Peter Barada <peter@the-baradas.com>
1555 * m68k.h: Switch from ColdFire chip name to core variant.
1557 2004-04-22 Peter Barada <peter@the-baradas.com>
1559 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1560 descriptions for new EMAC cases.
1561 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1562 handle Motorola MAC syntax.
1563 Allow disassembly of ColdFire V4e object files.
1565 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1567 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1569 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1571 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1573 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1575 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1577 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1579 * i386.h (i386_optab): Added xstore/xcrypt insns.
1581 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1583 * h8300.h (32bit ldc/stc): Add relaxing support.
1585 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1587 * h8300.h (BITOP): Pass MEMRELAX flag.
1589 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1591 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1594 For older changes see ChangeLog-9103
1596 Copyright (C) 2004-2012 Free Software Foundation, Inc.
1598 Copying and distribution of this file, with or without modification,
1599 are permitted in any medium without royalty provided the copyright
1600 notice and this notice are preserved.
1606 version-control: never