1 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
3 * arm.h (ARM_EXT_OS): New define.
4 (ARM_AEXT_V6SM): Likewise.
5 (ARM_ARCH_V6SM): Likewise.
7 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
9 * arm.h (ARM_EXT_MP): Add.
10 (ARM_ARCH_V7A_MP): Likewise.
12 2010-09-22 Mike Frysinger <vapier@gentoo.org>
14 * bfin.h: Declare pseudoChr structs/defines.
16 2010-09-21 Mike Frysinger <vapier@gentoo.org>
18 * bfin.h: Strip trailing whitespace.
20 2010-07-29 DJ Delorie <dj@redhat.com>
22 * rx.h (RX_Operand_Type): Add TwoReg.
23 (RX_Opcode_ID): Remove ediv and ediv2.
25 2010-07-27 DJ Delorie <dj@redhat.com>
27 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
29 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
30 Ina Pandit <ina.pandit@kpitcummins.com>
32 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
33 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
35 Remove PROCESSOR_V850EA support.
36 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
37 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
38 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
39 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
40 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
42 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
44 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
47 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
49 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
50 (MIPS16_INSN_BRANCH): Rename to...
51 (MIPS16_INSN_COND_BRANCH): ... this.
53 2010-07-03 Alan Modra <amodra@gmail.com>
55 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
56 Renumber other PPC_OPCODE defines.
58 2010-07-03 Alan Modra <amodra@gmail.com>
60 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
62 2010-06-29 Alan Modra <amodra@gmail.com>
64 * maxq.h: Delete file.
66 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
68 * ppc.h (PPC_OPCODE_E500): Define.
70 2010-05-26 Catherine Moore <clm@codesourcery.com>
72 * opcode/mips.h (INSN_MIPS16): Remove.
74 2010-04-21 Joseph Myers <joseph@codesourcery.com>
76 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
78 2010-04-15 Nick Clifton <nickc@redhat.com>
80 * alpha.h: Update copyright notice to use GPLv3.
100 * m68hc11.h: Likewise.
106 * mn10200.h: Likewise.
107 * mn10300.h: Likewise.
108 * msp430.h: Likewise.
119 * score-datadep.h: Likewise.
120 * score-inst.h: Likewise.
122 * spu-insns.h: Likewise.
126 * tic54x.h: Likewise.
131 2010-03-25 Joseph Myers <joseph@codesourcery.com>
133 * tic6x-control-registers.h, tic6x-insn-formats.h,
134 tic6x-opcode-table.h, tic6x.h: New.
136 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
138 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
140 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
142 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
144 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
146 * ia64.h (ia64_find_opcode): Remove argument name.
147 (ia64_find_next_opcode): Likewise.
148 (ia64_dis_opcode): Likewise.
149 (ia64_free_opcode): Likewise.
150 (ia64_find_dependency): Likewise.
152 2009-11-22 Doug Evans <dje@sebabeach.org>
154 * cgen.h: Include bfd_stdint.h.
155 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
157 2009-11-18 Paul Brook <paul@codesourcery.com>
159 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
161 2009-11-17 Paul Brook <paul@codesourcery.com>
162 Daniel Jacobowitz <dan@codesourcery.com>
164 * arm.h (ARM_EXT_V6_DSP): Define.
165 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
166 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
168 2009-11-04 DJ Delorie <dj@redhat.com>
170 * rx.h (rx_decode_opcode) (mvtipl): Add.
171 (mvtcp, mvfcp, opecp): Remove.
173 2009-11-02 Paul Brook <paul@codesourcery.com>
175 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
176 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
177 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
178 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
179 FPU_ARCH_NEON_VFP_V4): Define.
181 2009-10-23 Doug Evans <dje@sebabeach.org>
183 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
184 * cgen.h: Update. Improve multi-inclusion macro name.
186 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
188 * ppc.h (PPC_OPCODE_476): Define.
190 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
192 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
194 2009-09-29 DJ Delorie <dj@redhat.com>
198 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
200 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
202 2009-09-21 Ben Elliston <bje@au.ibm.com>
204 * ppc.h (PPC_OPCODE_PPCA2): New.
206 2009-09-05 Martin Thuresson <martin@mtme.org>
208 * ia64.h (struct ia64_operand): Renamed member class to op_class.
210 2009-08-29 Martin Thuresson <martin@mtme.org>
212 * tic30.h (template): Rename type template to
213 insn_template. Updated code to use new name.
214 * tic54x.h (template): Rename type template to
217 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
219 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
221 2009-06-11 Anthony Green <green@moxielogic.com>
223 * moxie.h (MOXIE_F3_PCREL): Define.
224 (moxie_form3_opc_info): Grow.
226 2009-06-06 Anthony Green <green@moxielogic.com>
228 * moxie.h (MOXIE_F1_M): Define.
230 2009-04-15 Anthony Green <green@moxielogic.com>
234 2009-04-06 DJ Delorie <dj@redhat.com>
236 * h8300.h: Add relaxation attributes to MOVA opcodes.
238 2009-03-10 Alan Modra <amodra@bigpond.net.au>
240 * ppc.h (ppc_parse_cpu): Declare.
242 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
244 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
245 and _IMM11 for mbitclr and mbitset.
246 * score-datadep.h: Update dependency information.
248 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
250 * ppc.h (PPC_OPCODE_POWER7): New.
252 2009-02-06 Doug Evans <dje@google.com>
254 * i386.h: Add comment regarding sse* insns and prefixes.
256 2009-02-03 Sandip Matte <sandip@rmicorp.com>
258 * mips.h (INSN_XLR): Define.
259 (INSN_CHIP_MASK): Update.
261 (OPCODE_IS_MEMBER): Update.
262 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
264 2009-01-28 Doug Evans <dje@google.com>
266 * opcode/i386.h: Add multiple inclusion protection.
267 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
268 (EDI_REG_NUM): New macros.
269 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
270 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
271 (REX_PREFIX_P): New macro.
273 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
275 * ppc.h (struct powerpc_opcode): New field "deprecated".
276 (PPC_OPCODE_NOPOWER4): Delete.
278 2008-11-28 Joshua Kinard <kumba@gentoo.org>
280 * mips.h: Define CPU_R14000, CPU_R16000.
281 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
283 2008-11-18 Catherine Moore <clm@codesourcery.com>
285 * arm.h (FPU_NEON_FP16): New.
286 (FPU_ARCH_NEON_FP16): New.
288 2008-11-06 Chao-ying Fu <fu@mips.com>
290 * mips.h: Doucument '1' for 5-bit sync type.
292 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
294 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
297 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
299 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
301 2008-07-30 Michael J. Eager <eager@eagercon.com>
303 * ppc.h (PPC_OPCODE_405): Define.
304 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
306 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
308 * ppc.h (ppc_cpu_t): New typedef.
309 (struct powerpc_opcode <flags>): Use it.
310 (struct powerpc_operand <insert, extract>): Likewise.
311 (struct powerpc_macro <flags>): Likewise.
313 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
315 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
316 Update comment before MIPS16 field descriptors to mention MIPS16.
317 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
319 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
320 New bit masks and shift counts for cins and exts.
322 * mips.h: Document new field descriptors +Q.
323 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
325 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
327 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
328 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
330 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
332 * ppc.h: (PPC_OPCODE_E500MC): New.
334 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
336 * i386.h (MAX_OPERANDS): Set to 5.
337 (MAX_MNEM_SIZE): Changed to 20.
339 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
341 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
343 2008-03-09 Paul Brook <paul@codesourcery.com>
345 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
347 2008-03-04 Paul Brook <paul@codesourcery.com>
349 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
350 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
351 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
353 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
354 Nick Clifton <nickc@redhat.com>
357 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
358 with a 32-bit displacement but without the top bit of the 4th byte
361 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
363 * cr16.h (cr16_num_optab): Declared.
365 2008-02-14 Hakan Ardo <hakan@debian.org>
368 * avr.h (AVR_ISA_2xxe): Define.
370 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
372 * mips.h: Update copyright.
373 (INSN_CHIP_MASK): New macro.
374 (INSN_OCTEON): New macro.
375 (CPU_OCTEON): New macro.
376 (OPCODE_IS_MEMBER): Handle Octeon instructions.
378 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
380 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
382 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
384 * avr.h (AVR_ISA_USB162): Add new opcode set.
385 (AVR_ISA_AVR3): Likewise.
387 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
389 * mips.h (INSN_LOONGSON_2E): New.
390 (INSN_LOONGSON_2F): New.
391 (CPU_LOONGSON_2E): New.
392 (CPU_LOONGSON_2F): New.
393 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
395 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
397 * mips.h (INSN_ISA*): Redefine certain values as an
398 enumeration. Update comments.
399 (mips_isa_table): New.
400 (ISA_MIPS*): Redefine to match enumeration.
401 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
404 2007-08-08 Ben Elliston <bje@au.ibm.com>
406 * ppc.h (PPC_OPCODE_PPCPS): New.
408 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
410 * m68k.h: Document j K & E.
412 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
414 * cr16.h: New file for CR16 target.
416 2007-05-02 Alan Modra <amodra@bigpond.net.au>
418 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
420 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
422 * m68k.h (mcfisa_c): New.
423 (mcfusp, mcf_mask): Adjust.
425 2007-04-20 Alan Modra <amodra@bigpond.net.au>
427 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
428 (num_powerpc_operands): Declare.
429 (PPC_OPERAND_SIGNED et al): Redefine as hex.
430 (PPC_OPERAND_PLUS1): Define.
432 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
434 * i386.h (REX_MODE64): Renamed to ...
436 (REX_EXTX): Renamed to ...
438 (REX_EXTY): Renamed to ...
440 (REX_EXTZ): Renamed to ...
443 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
445 * i386.h: Add entries from config/tc-i386.h and move tables
446 to opcodes/i386-opc.h.
448 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
450 * i386.h (FloatDR): Removed.
451 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
453 2007-03-01 Alan Modra <amodra@bigpond.net.au>
455 * spu-insns.h: Add soma double-float insns.
457 2007-02-20 Thiemo Seufer <ths@mips.com>
458 Chao-Ying Fu <fu@mips.com>
460 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
461 (INSN_DSPR2): Add flag for DSP R2 instructions.
462 (M_BALIGN): New macro.
464 2007-02-14 Alan Modra <amodra@bigpond.net.au>
466 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
467 and Seg3ShortFrom with Shortform.
469 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
472 * i386.h (i386_optab): Put the real "test" before the pseudo
475 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
477 * m68k.h (m68010up): OR fido_a.
479 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
481 * m68k.h (fido_a): New.
483 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
485 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
486 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
489 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
491 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
493 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
495 * score-inst.h (enum score_insn_type): Add Insn_internal.
497 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
498 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
499 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
500 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
501 Alan Modra <amodra@bigpond.net.au>
503 * spu-insns.h: New file.
506 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
508 * ppc.h (PPC_OPCODE_CELL): Define.
510 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
512 * i386.h : Modify opcode to support for the change in POPCNT opcode
513 in amdfam10 architecture.
515 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
517 * i386.h: Replace CpuMNI with CpuSSSE3.
519 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
520 Joseph Myers <joseph@codesourcery.com>
521 Ian Lance Taylor <ian@wasabisystems.com>
522 Ben Elliston <bje@wasabisystems.com>
524 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
526 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
528 * score-datadep.h: New file.
529 * score-inst.h: New file.
531 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
533 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
534 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
537 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
538 Michael Meissner <michael.meissner@amd.com>
540 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
542 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
544 * i386.h (i386_optab): Add "nop" with memory reference.
546 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
548 * i386.h (i386_optab): Update comment for 64bit NOP.
550 2006-06-06 Ben Elliston <bje@au.ibm.com>
551 Anton Blanchard <anton@samba.org>
553 * ppc.h (PPC_OPCODE_POWER6): Define.
556 2006-06-05 Thiemo Seufer <ths@mips.com>
558 * mips.h: Improve description of MT flags.
560 2006-05-25 Richard Sandiford <richard@codesourcery.com>
562 * m68k.h (mcf_mask): Define.
564 2006-05-05 Thiemo Seufer <ths@mips.com>
565 David Ung <davidu@mips.com>
567 * mips.h (enum): Add macro M_CACHE_AB.
569 2006-05-04 Thiemo Seufer <ths@mips.com>
570 Nigel Stephens <nigel@mips.com>
571 David Ung <davidu@mips.com>
573 * mips.h: Add INSN_SMARTMIPS define.
575 2006-04-30 Thiemo Seufer <ths@mips.com>
576 David Ung <davidu@mips.com>
578 * mips.h: Defines udi bits and masks. Add description of
579 characters which may appear in the args field of udi
582 2006-04-26 Thiemo Seufer <ths@networkno.de>
584 * mips.h: Improve comments describing the bitfield instruction
587 2006-04-26 Julian Brown <julian@codesourcery.com>
589 * arm.h (FPU_VFP_EXT_V3): Define constant.
590 (FPU_NEON_EXT_V1): Likewise.
591 (FPU_VFP_HARD): Update.
592 (FPU_VFP_V3): Define macro.
593 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
595 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
597 * avr.h (AVR_ISA_PWMx): New.
599 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
601 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
602 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
603 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
604 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
605 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
607 2006-03-10 Paul Brook <paul@codesourcery.com>
609 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
611 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
613 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
614 first. Correct mask of bb "B" opcode.
616 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
618 * i386.h (i386_optab): Support Intel Merom New Instructions.
620 2006-02-24 Paul Brook <paul@codesourcery.com>
622 * arm.h: Add V7 feature bits.
624 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
626 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
628 2006-01-31 Paul Brook <paul@codesourcery.com>
629 Richard Earnshaw <rearnsha@arm.com>
631 * arm.h: Use ARM_CPU_FEATURE.
632 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
633 (arm_feature_set): Change to a structure.
634 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
635 ARM_FEATURE): New macros.
637 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
639 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
640 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
641 (ADD_PC_INCR_OPCODE): Don't define.
643 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
646 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
648 2005-11-14 David Ung <davidu@mips.com>
650 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
651 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
652 save/restore encoding of the args field.
654 2005-10-28 Dave Brolley <brolley@redhat.com>
656 Contribute the following changes:
657 2005-02-16 Dave Brolley <brolley@redhat.com>
659 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
660 cgen_isa_mask_* to cgen_bitset_*.
663 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
665 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
666 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
667 (CGEN_CPU_TABLE): Make isas a ponter.
669 2003-09-29 Dave Brolley <brolley@redhat.com>
671 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
672 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
673 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
675 2002-12-13 Dave Brolley <brolley@redhat.com>
677 * cgen.h (symcat.h): #include it.
678 (cgen-bitset.h): #include it.
679 (CGEN_ATTR_VALUE_TYPE): Now a union.
680 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
681 (CGEN_ATTR_ENTRY): 'value' now unsigned.
682 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
683 * cgen-bitset.h: New file.
685 2005-09-30 Catherine Moore <clm@cm00re.com>
689 2005-10-24 Jan Beulich <jbeulich@novell.com>
691 * ia64.h (enum ia64_opnd): Move memory operand out of set of
694 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
696 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
697 Add FLAG_STRICT to pa10 ftest opcode.
699 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
701 * hppa.h (pa_opcodes): Remove lha entries.
703 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
705 * hppa.h (FLAG_STRICT): Revise comment.
706 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
707 before corresponding pa11 opcodes. Add strict pa10 register-immediate
710 2005-09-30 Catherine Moore <clm@cm00re.com>
714 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
716 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
718 2005-09-06 Chao-ying Fu <fu@mips.com>
720 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
721 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
723 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
724 (INSN_ASE_MASK): Update to include INSN_MT.
725 (INSN_MT): New define for MT ASE.
727 2005-08-25 Chao-ying Fu <fu@mips.com>
729 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
730 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
731 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
732 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
733 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
734 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
736 (INSN_DSP): New define for DSP ASE.
738 2005-08-18 Alan Modra <amodra@bigpond.net.au>
742 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
744 * ppc.h (PPC_OPCODE_E300): Define.
746 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
748 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
750 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
753 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
756 2005-07-27 Jan Beulich <jbeulich@novell.com>
758 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
759 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
760 Add movq-s as 64-bit variants of movd-s.
762 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
764 * hppa.h: Fix punctuation in comment.
766 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
767 implicit space-register addressing. Set space-register bits on opcodes
768 using implicit space-register addressing. Add various missing pa20
769 long-immediate opcodes. Remove various opcodes using implicit 3-bit
770 space-register addressing. Use "fE" instead of "fe" in various
773 2005-07-18 Jan Beulich <jbeulich@novell.com>
775 * i386.h (i386_optab): Operands of aam and aad are unsigned.
777 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
779 * i386.h (i386_optab): Support Intel VMX Instructions.
781 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
783 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
785 2005-07-05 Jan Beulich <jbeulich@novell.com>
787 * i386.h (i386_optab): Add new insns.
789 2005-07-01 Nick Clifton <nickc@redhat.com>
791 * sparc.h: Add typedefs to structure declarations.
793 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
796 * i386.h (i386_optab): Update comments for 64bit addressing on
797 mov. Allow 64bit addressing for mov and movq.
799 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
801 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
802 respectively, in various floating-point load and store patterns.
804 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
806 * hppa.h (FLAG_STRICT): Correct comment.
807 (pa_opcodes): Update load and store entries to allow both PA 1.X and
808 PA 2.0 mneumonics when equivalent. Entries with cache control
809 completers now require PA 1.1. Adjust whitespace.
811 2005-05-19 Anton Blanchard <anton@samba.org>
813 * ppc.h (PPC_OPCODE_POWER5): Define.
815 2005-05-10 Nick Clifton <nickc@redhat.com>
817 * Update the address and phone number of the FSF organization in
818 the GPL notices in the following files:
819 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
820 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
821 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
822 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
823 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
824 tic54x.h, tic80.h, v850.h, vax.h
826 2005-05-09 Jan Beulich <jbeulich@novell.com>
828 * i386.h (i386_optab): Add ht and hnt.
830 2005-04-18 Mark Kettenis <kettenis@gnu.org>
832 * i386.h: Insert hyphens into selected VIA PadLock extensions.
833 Add xcrypt-ctr. Provide aliases without hyphens.
835 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
837 Moved from ../ChangeLog
839 2005-04-12 Paul Brook <paul@codesourcery.com>
840 * m88k.h: Rename psr macros to avoid conflicts.
842 2005-03-12 Zack Weinberg <zack@codesourcery.com>
843 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
844 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
847 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
848 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
849 Remove redundant instruction types.
850 (struct argument): X_op - new field.
851 (struct cst4_entry): Remove.
852 (no_op_insn): Declare.
854 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
855 * crx.h (enum argtype): Rename types, remove unused types.
857 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
858 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
859 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
860 (enum operand_type): Rearrange operands, edit comments.
861 replace us<N> with ui<N> for unsigned immediate.
862 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
863 displacements (respectively).
864 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
865 (instruction type): Add NO_TYPE_INS.
866 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
867 (operand_entry): New field - 'flags'.
868 (operand flags): New.
870 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
871 * crx.h (operand_type): Remove redundant types i3, i4,
873 Add new unsigned immediate types us3, us4, us5, us16.
875 2005-04-12 Mark Kettenis <kettenis@gnu.org>
877 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
878 adjust them accordingly.
880 2005-04-01 Jan Beulich <jbeulich@novell.com>
882 * i386.h (i386_optab): Add rdtscp.
884 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
886 * i386.h (i386_optab): Don't allow the `l' suffix for moving
887 between memory and segment register. Allow movq for moving between
888 general-purpose register and segment register.
890 2005-02-09 Jan Beulich <jbeulich@novell.com>
893 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
894 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
897 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
899 * m68k.h (m68008, m68ec030, m68882): Remove.
901 (cpu_m68k, cpu_cf): New.
902 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
903 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
905 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
907 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
908 * cgen.h (enum cgen_parse_operand_type): Add
909 CGEN_PARSE_OPERAND_SYMBOLIC.
911 2005-01-21 Fred Fish <fnf@specifixinc.com>
913 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
914 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
915 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
917 2005-01-19 Fred Fish <fnf@specifixinc.com>
919 * mips.h (struct mips_opcode): Add new pinfo2 member.
920 (INSN_ALIAS): New define for opcode table entries that are
921 specific instances of another entry, such as 'move' for an 'or'
923 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
924 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
926 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
928 * mips.h (CPU_RM9000): Define.
929 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
931 2004-11-25 Jan Beulich <jbeulich@novell.com>
933 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
934 to/from test registers are illegal in 64-bit mode. Add missing
935 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
936 (previously one had to explicitly encode a rex64 prefix). Re-enable
937 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
938 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
940 2004-11-23 Jan Beulich <jbeulich@novell.com>
942 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
943 available only with SSE2. Change the MMX additions introduced by SSE
944 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
945 instructions by their now designated identifier (since combining i686
946 and 3DNow! does not really imply 3DNow!A).
948 2004-11-19 Alan Modra <amodra@bigpond.net.au>
950 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
951 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
953 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
954 Vineet Sharma <vineets@noida.hcltech.com>
956 * maxq.h: New file: Disassembly information for the maxq port.
958 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
960 * i386.h (i386_optab): Put back "movzb".
962 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
964 * cris.h (enum cris_insn_version_usage): Tweak formatting and
965 comments. Remove member cris_ver_sim. Add members
966 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
967 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
968 (struct cris_support_reg, struct cris_cond15): New types.
969 (cris_conds15): Declare.
970 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
971 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
972 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
973 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
974 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
977 2004-11-04 Jan Beulich <jbeulich@novell.com>
979 * i386.h (sldx_Suf): Remove.
980 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
981 (q_FP): Define, implying no REX64.
982 (x_FP, sl_FP): Imply FloatMF.
983 (i386_optab): Split reg and mem forms of moving from segment registers
984 so that the memory forms can ignore the 16-/32-bit operand size
985 distinction. Adjust a few others for Intel mode. Remove *FP uses from
986 all non-floating-point instructions. Unite 32- and 64-bit forms of
987 movsx, movzx, and movd. Adjust floating point operations for the above
988 changes to the *FP macros. Add DefaultSize to floating point control
989 insns operating on larger memory ranges. Remove left over comments
990 hinting at certain insns being Intel-syntax ones where the ones
991 actually meant are already gone.
993 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
995 * crx.h: Add COPS_REG_INS - Coprocessor Special register
998 2004-09-30 Paul Brook <paul@codesourcery.com>
1000 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1001 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1003 2004-09-11 Theodore A. Roth <troth@openavr.org>
1005 * avr.h: Add support for
1006 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1008 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1010 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1012 2004-08-24 Dmitry Diky <diwil@spec.ru>
1014 * msp430.h (msp430_opc): Add new instructions.
1015 (msp430_rcodes): Declare new instructions.
1016 (msp430_hcodes): Likewise..
1018 2004-08-13 Nick Clifton <nickc@redhat.com>
1021 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1024 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1026 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1028 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1030 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1032 2004-07-21 Jan Beulich <jbeulich@novell.com>
1034 * i386.h: Adjust instruction descriptions to better match the
1037 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
1039 * arm.h: Remove all old content. Replace with architecture defines
1040 from gas/config/tc-arm.c.
1042 2004-07-09 Andreas Schwab <schwab@suse.de>
1044 * m68k.h: Fix comment.
1046 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1050 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1052 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1054 2004-05-24 Peter Barada <peter@the-baradas.com>
1056 * m68k.h: Add 'size' to m68k_opcode.
1058 2004-05-05 Peter Barada <peter@the-baradas.com>
1060 * m68k.h: Switch from ColdFire chip name to core variant.
1062 2004-04-22 Peter Barada <peter@the-baradas.com>
1064 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1065 descriptions for new EMAC cases.
1066 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1067 handle Motorola MAC syntax.
1068 Allow disassembly of ColdFire V4e object files.
1070 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1072 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1074 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1076 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1078 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1080 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1082 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1084 * i386.h (i386_optab): Added xstore/xcrypt insns.
1086 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1088 * h8300.h (32bit ldc/stc): Add relaxing support.
1090 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1092 * h8300.h (BITOP): Pass MEMRELAX flag.
1094 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1096 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1099 For older changes see ChangeLog-9103
1105 version-control: never