1 2013-05-09 Andrew Pinski <apinski@cavium.com>
3 * mips.h (OP_MASK_CODE10): Correct definition.
4 (OP_SH_CODE10): Likewise.
5 Add a comment that "+J" is used now for OP_*CODE10.
6 (INSN_ASE_MASK): Update.
7 (INSN_VIRT): New macro.
8 (INSN_VIRT64): New macro
10 2013-05-02 Nick Clifton <nickc@redhat.com>
12 * msp430.h: Add patterns for MSP430X instructions.
14 2013-04-06 David S. Miller <davem@davemloft.net>
16 * sparc.h (F_PREFERRED): Define.
17 (F_PREF_ALIAS): Define.
19 2013-04-03 Nick Clifton <nickc@redhat.com>
21 * v850.h (V850_INVERSE_PCREL): Define.
23 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
26 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
28 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
31 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
33 * tic6xc-opcode-table.h: Add 16-bit insns.
34 * tic6x.h: Add support for 16-bit insns.
36 2013-03-21 Michael Schewe <michael.schewe@gmx.net>
38 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
39 and mov.b/w/l Rs,@(d:32,ERd).
41 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
44 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
45 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
46 tic6x_operand_xregpair operand coding type.
47 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
48 opcode field, usu ORXREGD1324 for the src2 operand and remove the
51 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
54 * tic6x.h (enum tic6x_coding_method): Add
55 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
56 separately the msb and lsb of a register pair. This is needed to
57 encode the opcodes in the same way as TI assembler does.
58 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
59 and rsqrdp opcodes to use the new field coding types.
61 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
63 * arm.h (CRC_EXT_ARMV8): New constant.
64 (ARCH_CRC_ARMV8): New macro.
66 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
68 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
70 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
71 Andrew Jenner <andrew@codesourcery.com>
73 Based on patches from Altera Corporation.
77 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
79 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
81 2013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
84 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
86 2013-01-24 Nick Clifton <nickc@redhat.com>
88 * v850.h: Add e3v5 support.
90 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
92 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
94 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
96 * ppc.h (PPC_OPCODE_POWER8): New define.
97 (PPC_OPCODE_HTM): Likewise.
99 2013-01-10 Will Newton <will.newton@imgtec.com>
103 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
105 * cr16.h (make_instruction): Rename to cr16_make_instruction.
106 (match_opcode): Rename to cr16_match_opcode.
108 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
110 * mips.h: Add support for r5900 instructions including lq and sq.
112 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
114 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
115 (make_instruction,match_opcode): Added function prototypes.
116 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
118 2012-11-23 Alan Modra <amodra@gmail.com>
120 * ppc.h (ppc_parse_cpu): Update prototype.
122 2012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
124 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
125 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
127 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
129 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
131 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
133 * ia64.h (ia64_opnd): Add new operand types.
135 2012-08-21 David S. Miller <davem@davemloft.net>
137 * sparc.h (F3F4): New macro.
139 2012-08-13 Ian Bolton <ian.bolton@arm.com>
140 Laurent Desnogues <laurent.desnogues@arm.com>
141 Jim MacArthur <jim.macarthur@arm.com>
142 Marcus Shawcroft <marcus.shawcroft@arm.com>
143 Nigel Stephens <nigel.stephens@arm.com>
144 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
145 Richard Earnshaw <rearnsha@arm.com>
146 Sofiane Naci <sofiane.naci@arm.com>
147 Tejas Belagod <tejas.belagod@arm.com>
148 Yufeng Zhang <yufeng.zhang@arm.com>
150 * aarch64.h: New file.
152 2012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
153 Maciej W. Rozycki <macro@codesourcery.com>
155 * mips.h (mips_opcode): Add the exclusions field.
156 (OPCODE_IS_MEMBER): Remove macro.
157 (cpu_is_member): New inline function.
158 (opcode_is_member): Likewise.
160 2012-07-31 Chao-Ying Fu <fu@mips.com>
161 Catherine Moore <clm@codesourcery.com>
162 Maciej W. Rozycki <macro@codesourcery.com>
164 * mips.h: Document microMIPS DSP ASE usage.
165 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
166 microMIPS DSP ASE support.
167 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
168 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
169 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
170 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
171 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
172 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
173 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
175 2012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
177 * mips.h: Fix a typo in description.
179 2012-06-07 Georg-Johann Lay <avr@gjlay.de>
181 * avr.h: (AVR_ISA_XCH): New define.
182 (AVR_ISA_XMEGA): Use it.
183 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
185 2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
187 * m68hc11.h: Add XGate definitions.
188 (struct m68hc11_opcode): Add xg_mask field.
190 2012-05-14 Catherine Moore <clm@codesourcery.com>
191 Maciej W. Rozycki <macro@codesourcery.com>
192 Rhonda Wittels <rhonda@codesourcery.com>
194 * ppc.h (PPC_OPCODE_VLE): New definition.
195 (PPC_OP_SA): New macro.
196 (PPC_OP_SE_VLE): New macro.
197 (PPC_OP): Use a variable shift amount.
198 (powerpc_operand): Update comments.
199 (PPC_OPSHIFT_INV): New macro.
200 (PPC_OPERAND_CR): Replace with...
201 (PPC_OPERAND_CR_BIT): ...this and
202 (PPC_OPERAND_CR_REG): ...this.
205 2012-05-03 Sean Keys <skeys@ipdatasys.com>
207 * xgate.h: Header file for XGATE assembler.
209 2012-04-27 David S. Miller <davem@davemloft.net>
211 * sparc.h: Document new arg code' )' for crypto RS3
214 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
215 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
216 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
217 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
218 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
219 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
220 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
221 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
222 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
223 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
224 HWCAP_CBCOND, HWCAP_CRC32): New defines.
226 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
228 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
230 2012-02-27 Alan Modra <amodra@gmail.com>
232 * crx.h (cst4_map): Update declaration.
234 2012-02-25 Walter Lee <walt@tilera.com>
236 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
238 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
239 TILEPRO_OPC_LW_TLS_SN.
241 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
243 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
244 (XRELEASE_PREFIX_OPCODE): Likewise.
246 2011-12-08 Andrew Pinski <apinski@cavium.com>
247 Adam Nemet <anemet@caviumnetworks.com>
249 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
250 (INSN_OCTEON2): New macro.
251 (CPU_OCTEON2): New macro.
252 (OPCODE_IS_MEMBER): Add Octeon2.
254 2011-11-29 Andrew Pinski <apinski@cavium.com>
256 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
257 (INSN_OCTEONP): New macro.
258 (CPU_OCTEONP): New macro.
259 (OPCODE_IS_MEMBER): Add Octeon+.
260 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
262 2011-11-01 DJ Delorie <dj@redhat.com>
266 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
268 * mips.h: Fix a typo in description.
270 2011-09-21 David S. Miller <davem@davemloft.net>
272 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
273 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
274 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
275 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
277 2011-08-09 Chao-ying Fu <fu@mips.com>
278 Maciej W. Rozycki <macro@codesourcery.com>
280 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
281 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
282 (INSN_ASE_MASK): Add the MCU bit.
283 (INSN_MCU): New macro.
284 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
285 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
287 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
289 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
290 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
291 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
292 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
293 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
294 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
295 (INSN2_READ_GPR_MMN): Likewise.
296 (INSN2_READ_FPR_D): Change the bit used.
297 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
298 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
299 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
300 (INSN2_COND_BRANCH): Likewise.
301 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
302 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
303 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
304 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
305 (INSN2_MOD_GPR_MN): Likewise.
307 2011-08-05 David S. Miller <davem@davemloft.net>
309 * sparc.h: Document new format codes '4', '5', and '('.
310 (OPF_LOW4, RS3): New macros.
312 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
314 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
315 order of flags documented.
317 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
319 * mips.h: Clarify the description of microMIPS instruction
321 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
323 2011-07-24 Chao-ying Fu <fu@mips.com>
324 Maciej W. Rozycki <macro@codesourcery.com>
326 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
327 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
328 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
329 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
330 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
331 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
332 (OP_MASK_RS3, OP_SH_RS3): Likewise.
333 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
334 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
335 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
336 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
337 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
338 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
339 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
340 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
341 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
342 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
343 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
344 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
345 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
346 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
347 (INSN_WRITE_GPR_S): New macro.
348 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
349 (INSN2_READ_FPR_D): Likewise.
350 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
351 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
352 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
353 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
354 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
355 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
356 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
357 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
358 (CPU_MICROMIPS): New macro.
359 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
360 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
361 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
362 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
363 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
364 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
365 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
366 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
367 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
368 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
369 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
370 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
371 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
372 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
373 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
374 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
375 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
376 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
377 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
378 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
379 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
380 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
381 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
382 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
383 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
384 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
385 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
386 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
387 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
388 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
389 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
390 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
391 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
392 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
393 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
394 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
395 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
396 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
397 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
398 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
399 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
400 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
401 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
402 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
403 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
404 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
405 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
406 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
407 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
408 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
409 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
410 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
411 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
412 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
413 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
414 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
415 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
416 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
417 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
418 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
419 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
420 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
421 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
422 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
423 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
424 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
425 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
426 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
427 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
428 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
429 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
430 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
431 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
432 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
433 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
434 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
435 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
436 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
437 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
438 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
439 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
440 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
441 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
442 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
443 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
444 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
445 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
446 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
447 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
448 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
449 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
450 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
451 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
452 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
453 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
454 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
455 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
456 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
457 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
458 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
459 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
460 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
461 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
462 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
463 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
464 (micromips_opcodes): New declaration.
465 (bfd_micromips_num_opcodes): Likewise.
467 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
469 * mips.h (INSN_TRAP): Rename to...
470 (INSN_NO_DELAY_SLOT): ... this.
471 (INSN_SYNC): Remove macro.
473 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
475 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
476 a duplicate of AVR_ISA_SPM.
478 2011-07-01 Nick Clifton <nickc@redhat.com>
480 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
482 2011-06-18 Robin Getz <robin.getz@analog.com>
484 * bfin.h (is_macmod_signed): New func
486 2011-06-18 Mike Frysinger <vapier@gentoo.org>
488 * bfin.h (is_macmod_pmove): Add missing space before func args.
489 (is_macmod_hmove): Likewise.
491 2011-06-13 Walter Lee <walt@tilera.com>
493 * tilegx.h: New file.
494 * tilepro.h: New file.
496 2011-05-31 Paul Brook <paul@codesourcery.com>
498 * arm.h (ARM_ARCH_V7R_IDIV): Define.
500 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
502 * s390.h: Replace S390_OPERAND_REG_EVEN with
503 S390_OPERAND_REG_PAIR.
505 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
507 * s390.h: Add S390_OPCODE_REG_EVEN flag.
509 2011-04-18 Julian Brown <julian@codesourcery.com>
511 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
513 2011-04-11 Dan McDonald <dan@wellkeeper.com>
516 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
518 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
520 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
521 New instruction set flags.
522 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
524 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
526 * mips.h (M_PREF_AB): New enum value.
528 2011-02-12 Mike Frysinger <vapier@gentoo.org>
530 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
532 (is_macmod_pmove, is_macmod_hmove): New functions.
534 2011-02-11 Mike Frysinger <vapier@gentoo.org>
536 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
538 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
540 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
541 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
543 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
546 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
549 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
552 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
554 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
556 * mips.h: Update commentary after last commit.
558 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
560 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
561 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
562 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
564 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
566 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
568 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
570 * mips.h: Fix previous commit.
572 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
574 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
575 (INSN_LOONGSON_3A): Clear bit 31.
577 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
580 * arm.h (ARM_AEXT_V6M_ONLY): New define.
581 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
582 (ARM_ARCH_V6M_ONLY): New define.
584 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
586 * mips.h (INSN_LOONGSON_3A): Defined.
587 (CPU_LOONGSON_3A): Defined.
588 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
590 2010-10-09 Matt Rice <ratmice@gmail.com>
592 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
593 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
595 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
597 * arm.h (ARM_EXT_VIRT): New define.
598 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
599 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
602 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
604 * arm.h (ARM_AEXT_ADIV): New define.
605 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
607 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
609 * arm.h (ARM_EXT_OS): New define.
610 (ARM_AEXT_V6SM): Likewise.
611 (ARM_ARCH_V6SM): Likewise.
613 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
615 * arm.h (ARM_EXT_MP): Add.
616 (ARM_ARCH_V7A_MP): Likewise.
618 2010-09-22 Mike Frysinger <vapier@gentoo.org>
620 * bfin.h: Declare pseudoChr structs/defines.
622 2010-09-21 Mike Frysinger <vapier@gentoo.org>
624 * bfin.h: Strip trailing whitespace.
626 2010-07-29 DJ Delorie <dj@redhat.com>
628 * rx.h (RX_Operand_Type): Add TwoReg.
629 (RX_Opcode_ID): Remove ediv and ediv2.
631 2010-07-27 DJ Delorie <dj@redhat.com>
633 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
635 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
636 Ina Pandit <ina.pandit@kpitcummins.com>
638 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
639 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
640 PROCESSOR_V850E2_ALL.
641 Remove PROCESSOR_V850EA support.
642 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
643 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
644 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
645 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
646 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
647 V850_OPERAND_PERCENT.
648 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
650 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
653 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
655 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
656 (MIPS16_INSN_BRANCH): Rename to...
657 (MIPS16_INSN_COND_BRANCH): ... this.
659 2010-07-03 Alan Modra <amodra@gmail.com>
661 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
662 Renumber other PPC_OPCODE defines.
664 2010-07-03 Alan Modra <amodra@gmail.com>
666 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
668 2010-06-29 Alan Modra <amodra@gmail.com>
670 * maxq.h: Delete file.
672 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
674 * ppc.h (PPC_OPCODE_E500): Define.
676 2010-05-26 Catherine Moore <clm@codesourcery.com>
678 * opcode/mips.h (INSN_MIPS16): Remove.
680 2010-04-21 Joseph Myers <joseph@codesourcery.com>
682 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
684 2010-04-15 Nick Clifton <nickc@redhat.com>
686 * alpha.h: Update copyright notice to use GPLv3.
692 * convex.h: Likewise.
706 * m68hc11.h: Likewise.
712 * mn10200.h: Likewise.
713 * mn10300.h: Likewise.
714 * msp430.h: Likewise.
725 * score-datadep.h: Likewise.
726 * score-inst.h: Likewise.
728 * spu-insns.h: Likewise.
732 * tic54x.h: Likewise.
737 2010-03-25 Joseph Myers <joseph@codesourcery.com>
739 * tic6x-control-registers.h, tic6x-insn-formats.h,
740 tic6x-opcode-table.h, tic6x.h: New.
742 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
744 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
746 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
748 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
750 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
752 * ia64.h (ia64_find_opcode): Remove argument name.
753 (ia64_find_next_opcode): Likewise.
754 (ia64_dis_opcode): Likewise.
755 (ia64_free_opcode): Likewise.
756 (ia64_find_dependency): Likewise.
758 2009-11-22 Doug Evans <dje@sebabeach.org>
760 * cgen.h: Include bfd_stdint.h.
761 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
763 2009-11-18 Paul Brook <paul@codesourcery.com>
765 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
767 2009-11-17 Paul Brook <paul@codesourcery.com>
768 Daniel Jacobowitz <dan@codesourcery.com>
770 * arm.h (ARM_EXT_V6_DSP): Define.
771 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
772 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
774 2009-11-04 DJ Delorie <dj@redhat.com>
776 * rx.h (rx_decode_opcode) (mvtipl): Add.
777 (mvtcp, mvfcp, opecp): Remove.
779 2009-11-02 Paul Brook <paul@codesourcery.com>
781 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
782 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
783 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
784 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
785 FPU_ARCH_NEON_VFP_V4): Define.
787 2009-10-23 Doug Evans <dje@sebabeach.org>
789 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
790 * cgen.h: Update. Improve multi-inclusion macro name.
792 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
794 * ppc.h (PPC_OPCODE_476): Define.
796 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
798 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
800 2009-09-29 DJ Delorie <dj@redhat.com>
804 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
806 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
808 2009-09-21 Ben Elliston <bje@au.ibm.com>
810 * ppc.h (PPC_OPCODE_PPCA2): New.
812 2009-09-05 Martin Thuresson <martin@mtme.org>
814 * ia64.h (struct ia64_operand): Renamed member class to op_class.
816 2009-08-29 Martin Thuresson <martin@mtme.org>
818 * tic30.h (template): Rename type template to
819 insn_template. Updated code to use new name.
820 * tic54x.h (template): Rename type template to
823 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
825 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
827 2009-06-11 Anthony Green <green@moxielogic.com>
829 * moxie.h (MOXIE_F3_PCREL): Define.
830 (moxie_form3_opc_info): Grow.
832 2009-06-06 Anthony Green <green@moxielogic.com>
834 * moxie.h (MOXIE_F1_M): Define.
836 2009-04-15 Anthony Green <green@moxielogic.com>
840 2009-04-06 DJ Delorie <dj@redhat.com>
842 * h8300.h: Add relaxation attributes to MOVA opcodes.
844 2009-03-10 Alan Modra <amodra@bigpond.net.au>
846 * ppc.h (ppc_parse_cpu): Declare.
848 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
850 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
851 and _IMM11 for mbitclr and mbitset.
852 * score-datadep.h: Update dependency information.
854 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
856 * ppc.h (PPC_OPCODE_POWER7): New.
858 2009-02-06 Doug Evans <dje@google.com>
860 * i386.h: Add comment regarding sse* insns and prefixes.
862 2009-02-03 Sandip Matte <sandip@rmicorp.com>
864 * mips.h (INSN_XLR): Define.
865 (INSN_CHIP_MASK): Update.
867 (OPCODE_IS_MEMBER): Update.
868 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
870 2009-01-28 Doug Evans <dje@google.com>
872 * opcode/i386.h: Add multiple inclusion protection.
873 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
874 (EDI_REG_NUM): New macros.
875 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
876 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
877 (REX_PREFIX_P): New macro.
879 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
881 * ppc.h (struct powerpc_opcode): New field "deprecated".
882 (PPC_OPCODE_NOPOWER4): Delete.
884 2008-11-28 Joshua Kinard <kumba@gentoo.org>
886 * mips.h: Define CPU_R14000, CPU_R16000.
887 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
889 2008-11-18 Catherine Moore <clm@codesourcery.com>
891 * arm.h (FPU_NEON_FP16): New.
892 (FPU_ARCH_NEON_FP16): New.
894 2008-11-06 Chao-ying Fu <fu@mips.com>
896 * mips.h: Doucument '1' for 5-bit sync type.
898 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
900 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
903 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
905 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
907 2008-07-30 Michael J. Eager <eager@eagercon.com>
909 * ppc.h (PPC_OPCODE_405): Define.
910 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
912 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
914 * ppc.h (ppc_cpu_t): New typedef.
915 (struct powerpc_opcode <flags>): Use it.
916 (struct powerpc_operand <insert, extract>): Likewise.
917 (struct powerpc_macro <flags>): Likewise.
919 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
921 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
922 Update comment before MIPS16 field descriptors to mention MIPS16.
923 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
925 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
926 New bit masks and shift counts for cins and exts.
928 * mips.h: Document new field descriptors +Q.
929 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
931 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
933 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
934 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
936 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
938 * ppc.h: (PPC_OPCODE_E500MC): New.
940 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
942 * i386.h (MAX_OPERANDS): Set to 5.
943 (MAX_MNEM_SIZE): Changed to 20.
945 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
947 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
949 2008-03-09 Paul Brook <paul@codesourcery.com>
951 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
953 2008-03-04 Paul Brook <paul@codesourcery.com>
955 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
956 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
957 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
959 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
960 Nick Clifton <nickc@redhat.com>
963 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
964 with a 32-bit displacement but without the top bit of the 4th byte
967 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
969 * cr16.h (cr16_num_optab): Declared.
971 2008-02-14 Hakan Ardo <hakan@debian.org>
974 * avr.h (AVR_ISA_2xxe): Define.
976 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
978 * mips.h: Update copyright.
979 (INSN_CHIP_MASK): New macro.
980 (INSN_OCTEON): New macro.
981 (CPU_OCTEON): New macro.
982 (OPCODE_IS_MEMBER): Handle Octeon instructions.
984 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
986 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
988 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
990 * avr.h (AVR_ISA_USB162): Add new opcode set.
991 (AVR_ISA_AVR3): Likewise.
993 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
995 * mips.h (INSN_LOONGSON_2E): New.
996 (INSN_LOONGSON_2F): New.
997 (CPU_LOONGSON_2E): New.
998 (CPU_LOONGSON_2F): New.
999 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1001 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1003 * mips.h (INSN_ISA*): Redefine certain values as an
1004 enumeration. Update comments.
1005 (mips_isa_table): New.
1006 (ISA_MIPS*): Redefine to match enumeration.
1007 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1010 2007-08-08 Ben Elliston <bje@au.ibm.com>
1012 * ppc.h (PPC_OPCODE_PPCPS): New.
1014 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1016 * m68k.h: Document j K & E.
1018 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1020 * cr16.h: New file for CR16 target.
1022 2007-05-02 Alan Modra <amodra@bigpond.net.au>
1024 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1026 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1028 * m68k.h (mcfisa_c): New.
1029 (mcfusp, mcf_mask): Adjust.
1031 2007-04-20 Alan Modra <amodra@bigpond.net.au>
1033 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1034 (num_powerpc_operands): Declare.
1035 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1036 (PPC_OPERAND_PLUS1): Define.
1038 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
1040 * i386.h (REX_MODE64): Renamed to ...
1042 (REX_EXTX): Renamed to ...
1044 (REX_EXTY): Renamed to ...
1046 (REX_EXTZ): Renamed to ...
1049 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1051 * i386.h: Add entries from config/tc-i386.h and move tables
1052 to opcodes/i386-opc.h.
1054 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1056 * i386.h (FloatDR): Removed.
1057 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1059 2007-03-01 Alan Modra <amodra@bigpond.net.au>
1061 * spu-insns.h: Add soma double-float insns.
1063 2007-02-20 Thiemo Seufer <ths@mips.com>
1064 Chao-Ying Fu <fu@mips.com>
1066 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1067 (INSN_DSPR2): Add flag for DSP R2 instructions.
1068 (M_BALIGN): New macro.
1070 2007-02-14 Alan Modra <amodra@bigpond.net.au>
1072 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1073 and Seg3ShortFrom with Shortform.
1075 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1078 * i386.h (i386_optab): Put the real "test" before the pseudo
1081 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
1083 * m68k.h (m68010up): OR fido_a.
1085 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
1087 * m68k.h (fido_a): New.
1089 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
1091 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1092 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1095 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1097 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1099 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1101 * score-inst.h (enum score_insn_type): Add Insn_internal.
1103 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1104 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1105 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1106 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1107 Alan Modra <amodra@bigpond.net.au>
1109 * spu-insns.h: New file.
1112 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1114 * ppc.h (PPC_OPCODE_CELL): Define.
1116 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1118 * i386.h : Modify opcode to support for the change in POPCNT opcode
1119 in amdfam10 architecture.
1121 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1123 * i386.h: Replace CpuMNI with CpuSSSE3.
1125 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
1126 Joseph Myers <joseph@codesourcery.com>
1127 Ian Lance Taylor <ian@wasabisystems.com>
1128 Ben Elliston <bje@wasabisystems.com>
1130 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1132 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1134 * score-datadep.h: New file.
1135 * score-inst.h: New file.
1137 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1139 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1140 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1141 movdq2q and movq2dq.
1143 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1144 Michael Meissner <michael.meissner@amd.com>
1146 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1148 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1150 * i386.h (i386_optab): Add "nop" with memory reference.
1152 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1154 * i386.h (i386_optab): Update comment for 64bit NOP.
1156 2006-06-06 Ben Elliston <bje@au.ibm.com>
1157 Anton Blanchard <anton@samba.org>
1159 * ppc.h (PPC_OPCODE_POWER6): Define.
1162 2006-06-05 Thiemo Seufer <ths@mips.com>
1164 * mips.h: Improve description of MT flags.
1166 2006-05-25 Richard Sandiford <richard@codesourcery.com>
1168 * m68k.h (mcf_mask): Define.
1170 2006-05-05 Thiemo Seufer <ths@mips.com>
1171 David Ung <davidu@mips.com>
1173 * mips.h (enum): Add macro M_CACHE_AB.
1175 2006-05-04 Thiemo Seufer <ths@mips.com>
1176 Nigel Stephens <nigel@mips.com>
1177 David Ung <davidu@mips.com>
1179 * mips.h: Add INSN_SMARTMIPS define.
1181 2006-04-30 Thiemo Seufer <ths@mips.com>
1182 David Ung <davidu@mips.com>
1184 * mips.h: Defines udi bits and masks. Add description of
1185 characters which may appear in the args field of udi
1188 2006-04-26 Thiemo Seufer <ths@networkno.de>
1190 * mips.h: Improve comments describing the bitfield instruction
1193 2006-04-26 Julian Brown <julian@codesourcery.com>
1195 * arm.h (FPU_VFP_EXT_V3): Define constant.
1196 (FPU_NEON_EXT_V1): Likewise.
1197 (FPU_VFP_HARD): Update.
1198 (FPU_VFP_V3): Define macro.
1199 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1201 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
1203 * avr.h (AVR_ISA_PWMx): New.
1205 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1207 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1208 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1209 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1210 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1211 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1213 2006-03-10 Paul Brook <paul@codesourcery.com>
1215 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1217 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1219 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1220 first. Correct mask of bb "B" opcode.
1222 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1224 * i386.h (i386_optab): Support Intel Merom New Instructions.
1226 2006-02-24 Paul Brook <paul@codesourcery.com>
1228 * arm.h: Add V7 feature bits.
1230 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1232 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1234 2006-01-31 Paul Brook <paul@codesourcery.com>
1235 Richard Earnshaw <rearnsha@arm.com>
1237 * arm.h: Use ARM_CPU_FEATURE.
1238 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1239 (arm_feature_set): Change to a structure.
1240 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1241 ARM_FEATURE): New macros.
1243 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
1245 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1246 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1247 (ADD_PC_INCR_OPCODE): Don't define.
1249 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1252 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1254 2005-11-14 David Ung <davidu@mips.com>
1256 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1257 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1258 save/restore encoding of the args field.
1260 2005-10-28 Dave Brolley <brolley@redhat.com>
1262 Contribute the following changes:
1263 2005-02-16 Dave Brolley <brolley@redhat.com>
1265 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1266 cgen_isa_mask_* to cgen_bitset_*.
1269 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1271 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1272 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1273 (CGEN_CPU_TABLE): Make isas a ponter.
1275 2003-09-29 Dave Brolley <brolley@redhat.com>
1277 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1278 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1279 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1281 2002-12-13 Dave Brolley <brolley@redhat.com>
1283 * cgen.h (symcat.h): #include it.
1284 (cgen-bitset.h): #include it.
1285 (CGEN_ATTR_VALUE_TYPE): Now a union.
1286 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1287 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1288 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1289 * cgen-bitset.h: New file.
1291 2005-09-30 Catherine Moore <clm@cm00re.com>
1295 2005-10-24 Jan Beulich <jbeulich@novell.com>
1297 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1300 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1302 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1303 Add FLAG_STRICT to pa10 ftest opcode.
1305 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1307 * hppa.h (pa_opcodes): Remove lha entries.
1309 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1311 * hppa.h (FLAG_STRICT): Revise comment.
1312 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1313 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1316 2005-09-30 Catherine Moore <clm@cm00re.com>
1320 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1322 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1324 2005-09-06 Chao-ying Fu <fu@mips.com>
1326 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1327 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1329 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1330 (INSN_ASE_MASK): Update to include INSN_MT.
1331 (INSN_MT): New define for MT ASE.
1333 2005-08-25 Chao-ying Fu <fu@mips.com>
1335 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1336 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1337 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1338 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1339 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1340 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1342 (INSN_DSP): New define for DSP ASE.
1344 2005-08-18 Alan Modra <amodra@bigpond.net.au>
1348 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1350 * ppc.h (PPC_OPCODE_E300): Define.
1352 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1354 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1356 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1359 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1362 2005-07-27 Jan Beulich <jbeulich@novell.com>
1364 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1365 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1366 Add movq-s as 64-bit variants of movd-s.
1368 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1370 * hppa.h: Fix punctuation in comment.
1372 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1373 implicit space-register addressing. Set space-register bits on opcodes
1374 using implicit space-register addressing. Add various missing pa20
1375 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1376 space-register addressing. Use "fE" instead of "fe" in various
1379 2005-07-18 Jan Beulich <jbeulich@novell.com>
1381 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1383 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1385 * i386.h (i386_optab): Support Intel VMX Instructions.
1387 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1389 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1391 2005-07-05 Jan Beulich <jbeulich@novell.com>
1393 * i386.h (i386_optab): Add new insns.
1395 2005-07-01 Nick Clifton <nickc@redhat.com>
1397 * sparc.h: Add typedefs to structure declarations.
1399 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1402 * i386.h (i386_optab): Update comments for 64bit addressing on
1403 mov. Allow 64bit addressing for mov and movq.
1405 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1407 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1408 respectively, in various floating-point load and store patterns.
1410 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1412 * hppa.h (FLAG_STRICT): Correct comment.
1413 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1414 PA 2.0 mneumonics when equivalent. Entries with cache control
1415 completers now require PA 1.1. Adjust whitespace.
1417 2005-05-19 Anton Blanchard <anton@samba.org>
1419 * ppc.h (PPC_OPCODE_POWER5): Define.
1421 2005-05-10 Nick Clifton <nickc@redhat.com>
1423 * Update the address and phone number of the FSF organization in
1424 the GPL notices in the following files:
1425 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1426 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1427 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1428 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1429 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1430 tic54x.h, tic80.h, v850.h, vax.h
1432 2005-05-09 Jan Beulich <jbeulich@novell.com>
1434 * i386.h (i386_optab): Add ht and hnt.
1436 2005-04-18 Mark Kettenis <kettenis@gnu.org>
1438 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1439 Add xcrypt-ctr. Provide aliases without hyphens.
1441 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1443 Moved from ../ChangeLog
1445 2005-04-12 Paul Brook <paul@codesourcery.com>
1446 * m88k.h: Rename psr macros to avoid conflicts.
1448 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1449 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1450 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1451 and ARM_ARCH_V6ZKT2.
1453 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1454 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1455 Remove redundant instruction types.
1456 (struct argument): X_op - new field.
1457 (struct cst4_entry): Remove.
1458 (no_op_insn): Declare.
1460 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1461 * crx.h (enum argtype): Rename types, remove unused types.
1463 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1464 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1465 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1466 (enum operand_type): Rearrange operands, edit comments.
1467 replace us<N> with ui<N> for unsigned immediate.
1468 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1469 displacements (respectively).
1470 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1471 (instruction type): Add NO_TYPE_INS.
1472 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1473 (operand_entry): New field - 'flags'.
1474 (operand flags): New.
1476 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1477 * crx.h (operand_type): Remove redundant types i3, i4,
1479 Add new unsigned immediate types us3, us4, us5, us16.
1481 2005-04-12 Mark Kettenis <kettenis@gnu.org>
1483 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1484 adjust them accordingly.
1486 2005-04-01 Jan Beulich <jbeulich@novell.com>
1488 * i386.h (i386_optab): Add rdtscp.
1490 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1492 * i386.h (i386_optab): Don't allow the `l' suffix for moving
1493 between memory and segment register. Allow movq for moving between
1494 general-purpose register and segment register.
1496 2005-02-09 Jan Beulich <jbeulich@novell.com>
1499 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1500 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1503 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1505 * m68k.h (m68008, m68ec030, m68882): Remove.
1507 (cpu_m68k, cpu_cf): New.
1508 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1509 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1511 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
1513 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1514 * cgen.h (enum cgen_parse_operand_type): Add
1515 CGEN_PARSE_OPERAND_SYMBOLIC.
1517 2005-01-21 Fred Fish <fnf@specifixinc.com>
1519 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1520 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1521 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1523 2005-01-19 Fred Fish <fnf@specifixinc.com>
1525 * mips.h (struct mips_opcode): Add new pinfo2 member.
1526 (INSN_ALIAS): New define for opcode table entries that are
1527 specific instances of another entry, such as 'move' for an 'or'
1528 with a zero operand.
1529 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1530 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1532 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1534 * mips.h (CPU_RM9000): Define.
1535 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1537 2004-11-25 Jan Beulich <jbeulich@novell.com>
1539 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1540 to/from test registers are illegal in 64-bit mode. Add missing
1541 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1542 (previously one had to explicitly encode a rex64 prefix). Re-enable
1543 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1544 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1546 2004-11-23 Jan Beulich <jbeulich@novell.com>
1548 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1549 available only with SSE2. Change the MMX additions introduced by SSE
1550 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1551 instructions by their now designated identifier (since combining i686
1552 and 3DNow! does not really imply 3DNow!A).
1554 2004-11-19 Alan Modra <amodra@bigpond.net.au>
1556 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1557 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1559 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1560 Vineet Sharma <vineets@noida.hcltech.com>
1562 * maxq.h: New file: Disassembly information for the maxq port.
1564 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1566 * i386.h (i386_optab): Put back "movzb".
1568 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
1570 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1571 comments. Remove member cris_ver_sim. Add members
1572 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1573 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1574 (struct cris_support_reg, struct cris_cond15): New types.
1575 (cris_conds15): Declare.
1576 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1577 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1578 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1579 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1580 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1581 SIZE_FIELD_UNSIGNED.
1583 2004-11-04 Jan Beulich <jbeulich@novell.com>
1585 * i386.h (sldx_Suf): Remove.
1586 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1587 (q_FP): Define, implying no REX64.
1588 (x_FP, sl_FP): Imply FloatMF.
1589 (i386_optab): Split reg and mem forms of moving from segment registers
1590 so that the memory forms can ignore the 16-/32-bit operand size
1591 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1592 all non-floating-point instructions. Unite 32- and 64-bit forms of
1593 movsx, movzx, and movd. Adjust floating point operations for the above
1594 changes to the *FP macros. Add DefaultSize to floating point control
1595 insns operating on larger memory ranges. Remove left over comments
1596 hinting at certain insns being Intel-syntax ones where the ones
1597 actually meant are already gone.
1599 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1601 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1604 2004-09-30 Paul Brook <paul@codesourcery.com>
1606 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1607 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1609 2004-09-11 Theodore A. Roth <troth@openavr.org>
1611 * avr.h: Add support for
1612 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1614 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1616 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1618 2004-08-24 Dmitry Diky <diwil@spec.ru>
1620 * msp430.h (msp430_opc): Add new instructions.
1621 (msp430_rcodes): Declare new instructions.
1622 (msp430_hcodes): Likewise..
1624 2004-08-13 Nick Clifton <nickc@redhat.com>
1627 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1630 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1632 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1634 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1636 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1638 2004-07-21 Jan Beulich <jbeulich@novell.com>
1640 * i386.h: Adjust instruction descriptions to better match the
1643 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
1645 * arm.h: Remove all old content. Replace with architecture defines
1646 from gas/config/tc-arm.c.
1648 2004-07-09 Andreas Schwab <schwab@suse.de>
1650 * m68k.h: Fix comment.
1652 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1656 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1658 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1660 2004-05-24 Peter Barada <peter@the-baradas.com>
1662 * m68k.h: Add 'size' to m68k_opcode.
1664 2004-05-05 Peter Barada <peter@the-baradas.com>
1666 * m68k.h: Switch from ColdFire chip name to core variant.
1668 2004-04-22 Peter Barada <peter@the-baradas.com>
1670 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1671 descriptions for new EMAC cases.
1672 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1673 handle Motorola MAC syntax.
1674 Allow disassembly of ColdFire V4e object files.
1676 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1678 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1680 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1682 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1684 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1686 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1688 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1690 * i386.h (i386_optab): Added xstore/xcrypt insns.
1692 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1694 * h8300.h (32bit ldc/stc): Add relaxing support.
1696 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1698 * h8300.h (BITOP): Pass MEMRELAX flag.
1700 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1702 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1705 For older changes see ChangeLog-9103
1707 Copyright (C) 2004-2012 Free Software Foundation, Inc.
1709 Copying and distribution of this file, with or without modification,
1710 are permitted in any medium without royalty provided the copyright
1711 notice and this notice are preserved.
1717 version-control: never