1 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
3 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
5 2012-02-27 Alan Modra <amodra@gmail.com>
7 * crx.h (cst4_map): Update declaration.
9 2012-02-25 Walter Lee <walt@tilera.com>
11 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
13 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
14 TILEPRO_OPC_LW_TLS_SN.
16 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
18 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
19 (XRELEASE_PREFIX_OPCODE): Likewise.
21 2011-12-08 Andrew Pinski <apinski@cavium.com>
22 Adam Nemet <anemet@caviumnetworks.com>
24 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
25 (INSN_OCTEON2): New macro.
26 (CPU_OCTEON2): New macro.
27 (OPCODE_IS_MEMBER): Add Octeon2.
29 2011-11-29 Andrew Pinski <apinski@cavium.com>
31 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
32 (INSN_OCTEONP): New macro.
33 (CPU_OCTEONP): New macro.
34 (OPCODE_IS_MEMBER): Add Octeon+.
35 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
37 2011-11-01 DJ Delorie <dj@redhat.com>
41 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
43 * mips.h: Fix a typo in description.
45 2011-09-21 David S. Miller <davem@davemloft.net>
47 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
48 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
49 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
50 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
52 2011-08-09 Chao-ying Fu <fu@mips.com>
53 Maciej W. Rozycki <macro@codesourcery.com>
55 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
56 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
57 (INSN_ASE_MASK): Add the MCU bit.
58 (INSN_MCU): New macro.
59 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
60 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
62 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
64 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
65 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
66 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
67 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
68 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
69 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
70 (INSN2_READ_GPR_MMN): Likewise.
71 (INSN2_READ_FPR_D): Change the bit used.
72 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
73 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
74 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
75 (INSN2_COND_BRANCH): Likewise.
76 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
77 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
78 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
79 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
80 (INSN2_MOD_GPR_MN): Likewise.
82 2011-08-05 David S. Miller <davem@davemloft.net>
84 * sparc.h: Document new format codes '4', '5', and '('.
85 (OPF_LOW4, RS3): New macros.
87 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
89 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
90 order of flags documented.
92 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
94 * mips.h: Clarify the description of microMIPS instruction
96 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
98 2011-07-24 Chao-ying Fu <fu@mips.com>
99 Maciej W. Rozycki <macro@codesourcery.com>
101 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
102 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
103 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
104 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
105 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
106 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
107 (OP_MASK_RS3, OP_SH_RS3): Likewise.
108 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
109 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
110 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
111 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
112 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
113 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
114 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
115 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
116 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
117 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
118 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
119 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
120 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
121 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
122 (INSN_WRITE_GPR_S): New macro.
123 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
124 (INSN2_READ_FPR_D): Likewise.
125 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
126 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
127 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
128 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
129 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
130 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
131 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
132 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
133 (CPU_MICROMIPS): New macro.
134 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
135 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
136 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
137 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
138 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
139 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
140 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
141 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
142 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
143 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
144 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
145 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
146 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
147 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
148 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
149 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
150 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
151 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
152 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
153 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
154 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
155 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
156 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
157 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
158 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
159 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
160 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
161 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
162 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
163 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
164 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
165 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
166 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
167 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
168 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
169 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
170 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
171 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
172 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
173 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
174 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
175 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
176 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
177 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
178 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
179 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
180 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
181 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
182 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
183 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
184 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
185 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
186 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
187 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
188 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
189 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
190 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
191 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
192 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
193 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
194 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
195 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
196 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
197 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
198 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
199 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
200 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
201 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
202 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
203 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
204 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
205 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
206 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
207 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
208 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
209 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
210 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
211 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
212 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
213 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
214 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
215 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
216 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
217 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
218 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
219 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
220 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
221 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
222 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
223 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
224 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
225 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
226 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
227 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
228 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
229 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
230 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
231 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
232 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
233 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
234 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
235 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
236 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
237 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
238 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
239 (micromips_opcodes): New declaration.
240 (bfd_micromips_num_opcodes): Likewise.
242 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
244 * mips.h (INSN_TRAP): Rename to...
245 (INSN_NO_DELAY_SLOT): ... this.
246 (INSN_SYNC): Remove macro.
248 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
250 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
251 a duplicate of AVR_ISA_SPM.
253 2011-07-01 Nick Clifton <nickc@redhat.com>
255 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
257 2011-06-18 Robin Getz <robin.getz@analog.com>
259 * bfin.h (is_macmod_signed): New func
261 2011-06-18 Mike Frysinger <vapier@gentoo.org>
263 * bfin.h (is_macmod_pmove): Add missing space before func args.
264 (is_macmod_hmove): Likewise.
266 2011-06-13 Walter Lee <walt@tilera.com>
268 * tilegx.h: New file.
269 * tilepro.h: New file.
271 2011-05-31 Paul Brook <paul@codesourcery.com>
273 * arm.h (ARM_ARCH_V7R_IDIV): Define.
275 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
277 * s390.h: Replace S390_OPERAND_REG_EVEN with
278 S390_OPERAND_REG_PAIR.
280 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
282 * s390.h: Add S390_OPCODE_REG_EVEN flag.
284 2011-04-18 Julian Brown <julian@codesourcery.com>
286 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
288 2011-04-11 Dan McDonald <dan@wellkeeper.com>
291 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
293 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
295 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
296 New instruction set flags.
297 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
299 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
301 * mips.h (M_PREF_AB): New enum value.
303 2011-02-12 Mike Frysinger <vapier@gentoo.org>
305 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
307 (is_macmod_pmove, is_macmod_hmove): New functions.
309 2011-02-11 Mike Frysinger <vapier@gentoo.org>
311 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
313 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
315 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
316 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
318 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
321 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
324 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
327 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
329 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
331 * mips.h: Update commentary after last commit.
333 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
335 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
336 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
337 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
339 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
341 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
343 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
345 * mips.h: Fix previous commit.
347 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
349 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
350 (INSN_LOONGSON_3A): Clear bit 31.
352 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
355 * arm.h (ARM_AEXT_V6M_ONLY): New define.
356 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
357 (ARM_ARCH_V6M_ONLY): New define.
359 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
361 * mips.h (INSN_LOONGSON_3A): Defined.
362 (CPU_LOONGSON_3A): Defined.
363 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
365 2010-10-09 Matt Rice <ratmice@gmail.com>
367 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
368 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
370 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
372 * arm.h (ARM_EXT_VIRT): New define.
373 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
374 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
377 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
379 * arm.h (ARM_AEXT_ADIV): New define.
380 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
382 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
384 * arm.h (ARM_EXT_OS): New define.
385 (ARM_AEXT_V6SM): Likewise.
386 (ARM_ARCH_V6SM): Likewise.
388 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
390 * arm.h (ARM_EXT_MP): Add.
391 (ARM_ARCH_V7A_MP): Likewise.
393 2010-09-22 Mike Frysinger <vapier@gentoo.org>
395 * bfin.h: Declare pseudoChr structs/defines.
397 2010-09-21 Mike Frysinger <vapier@gentoo.org>
399 * bfin.h: Strip trailing whitespace.
401 2010-07-29 DJ Delorie <dj@redhat.com>
403 * rx.h (RX_Operand_Type): Add TwoReg.
404 (RX_Opcode_ID): Remove ediv and ediv2.
406 2010-07-27 DJ Delorie <dj@redhat.com>
408 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
410 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
411 Ina Pandit <ina.pandit@kpitcummins.com>
413 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
414 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
415 PROCESSOR_V850E2_ALL.
416 Remove PROCESSOR_V850EA support.
417 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
418 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
419 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
420 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
421 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
422 V850_OPERAND_PERCENT.
423 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
425 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
428 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
430 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
431 (MIPS16_INSN_BRANCH): Rename to...
432 (MIPS16_INSN_COND_BRANCH): ... this.
434 2010-07-03 Alan Modra <amodra@gmail.com>
436 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
437 Renumber other PPC_OPCODE defines.
439 2010-07-03 Alan Modra <amodra@gmail.com>
441 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
443 2010-06-29 Alan Modra <amodra@gmail.com>
445 * maxq.h: Delete file.
447 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
449 * ppc.h (PPC_OPCODE_E500): Define.
451 2010-05-26 Catherine Moore <clm@codesourcery.com>
453 * opcode/mips.h (INSN_MIPS16): Remove.
455 2010-04-21 Joseph Myers <joseph@codesourcery.com>
457 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
459 2010-04-15 Nick Clifton <nickc@redhat.com>
461 * alpha.h: Update copyright notice to use GPLv3.
467 * convex.h: Likewise.
481 * m68hc11.h: Likewise.
487 * mn10200.h: Likewise.
488 * mn10300.h: Likewise.
489 * msp430.h: Likewise.
500 * score-datadep.h: Likewise.
501 * score-inst.h: Likewise.
503 * spu-insns.h: Likewise.
507 * tic54x.h: Likewise.
512 2010-03-25 Joseph Myers <joseph@codesourcery.com>
514 * tic6x-control-registers.h, tic6x-insn-formats.h,
515 tic6x-opcode-table.h, tic6x.h: New.
517 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
519 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
521 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
523 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
525 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
527 * ia64.h (ia64_find_opcode): Remove argument name.
528 (ia64_find_next_opcode): Likewise.
529 (ia64_dis_opcode): Likewise.
530 (ia64_free_opcode): Likewise.
531 (ia64_find_dependency): Likewise.
533 2009-11-22 Doug Evans <dje@sebabeach.org>
535 * cgen.h: Include bfd_stdint.h.
536 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
538 2009-11-18 Paul Brook <paul@codesourcery.com>
540 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
542 2009-11-17 Paul Brook <paul@codesourcery.com>
543 Daniel Jacobowitz <dan@codesourcery.com>
545 * arm.h (ARM_EXT_V6_DSP): Define.
546 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
547 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
549 2009-11-04 DJ Delorie <dj@redhat.com>
551 * rx.h (rx_decode_opcode) (mvtipl): Add.
552 (mvtcp, mvfcp, opecp): Remove.
554 2009-11-02 Paul Brook <paul@codesourcery.com>
556 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
557 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
558 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
559 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
560 FPU_ARCH_NEON_VFP_V4): Define.
562 2009-10-23 Doug Evans <dje@sebabeach.org>
564 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
565 * cgen.h: Update. Improve multi-inclusion macro name.
567 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
569 * ppc.h (PPC_OPCODE_476): Define.
571 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
573 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
575 2009-09-29 DJ Delorie <dj@redhat.com>
579 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
581 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
583 2009-09-21 Ben Elliston <bje@au.ibm.com>
585 * ppc.h (PPC_OPCODE_PPCA2): New.
587 2009-09-05 Martin Thuresson <martin@mtme.org>
589 * ia64.h (struct ia64_operand): Renamed member class to op_class.
591 2009-08-29 Martin Thuresson <martin@mtme.org>
593 * tic30.h (template): Rename type template to
594 insn_template. Updated code to use new name.
595 * tic54x.h (template): Rename type template to
598 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
600 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
602 2009-06-11 Anthony Green <green@moxielogic.com>
604 * moxie.h (MOXIE_F3_PCREL): Define.
605 (moxie_form3_opc_info): Grow.
607 2009-06-06 Anthony Green <green@moxielogic.com>
609 * moxie.h (MOXIE_F1_M): Define.
611 2009-04-15 Anthony Green <green@moxielogic.com>
615 2009-04-06 DJ Delorie <dj@redhat.com>
617 * h8300.h: Add relaxation attributes to MOVA opcodes.
619 2009-03-10 Alan Modra <amodra@bigpond.net.au>
621 * ppc.h (ppc_parse_cpu): Declare.
623 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
625 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
626 and _IMM11 for mbitclr and mbitset.
627 * score-datadep.h: Update dependency information.
629 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
631 * ppc.h (PPC_OPCODE_POWER7): New.
633 2009-02-06 Doug Evans <dje@google.com>
635 * i386.h: Add comment regarding sse* insns and prefixes.
637 2009-02-03 Sandip Matte <sandip@rmicorp.com>
639 * mips.h (INSN_XLR): Define.
640 (INSN_CHIP_MASK): Update.
642 (OPCODE_IS_MEMBER): Update.
643 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
645 2009-01-28 Doug Evans <dje@google.com>
647 * opcode/i386.h: Add multiple inclusion protection.
648 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
649 (EDI_REG_NUM): New macros.
650 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
651 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
652 (REX_PREFIX_P): New macro.
654 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
656 * ppc.h (struct powerpc_opcode): New field "deprecated".
657 (PPC_OPCODE_NOPOWER4): Delete.
659 2008-11-28 Joshua Kinard <kumba@gentoo.org>
661 * mips.h: Define CPU_R14000, CPU_R16000.
662 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
664 2008-11-18 Catherine Moore <clm@codesourcery.com>
666 * arm.h (FPU_NEON_FP16): New.
667 (FPU_ARCH_NEON_FP16): New.
669 2008-11-06 Chao-ying Fu <fu@mips.com>
671 * mips.h: Doucument '1' for 5-bit sync type.
673 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
675 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
678 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
680 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
682 2008-07-30 Michael J. Eager <eager@eagercon.com>
684 * ppc.h (PPC_OPCODE_405): Define.
685 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
687 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
689 * ppc.h (ppc_cpu_t): New typedef.
690 (struct powerpc_opcode <flags>): Use it.
691 (struct powerpc_operand <insert, extract>): Likewise.
692 (struct powerpc_macro <flags>): Likewise.
694 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
696 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
697 Update comment before MIPS16 field descriptors to mention MIPS16.
698 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
700 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
701 New bit masks and shift counts for cins and exts.
703 * mips.h: Document new field descriptors +Q.
704 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
706 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
708 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
709 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
711 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
713 * ppc.h: (PPC_OPCODE_E500MC): New.
715 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
717 * i386.h (MAX_OPERANDS): Set to 5.
718 (MAX_MNEM_SIZE): Changed to 20.
720 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
722 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
724 2008-03-09 Paul Brook <paul@codesourcery.com>
726 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
728 2008-03-04 Paul Brook <paul@codesourcery.com>
730 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
731 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
732 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
734 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
735 Nick Clifton <nickc@redhat.com>
738 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
739 with a 32-bit displacement but without the top bit of the 4th byte
742 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
744 * cr16.h (cr16_num_optab): Declared.
746 2008-02-14 Hakan Ardo <hakan@debian.org>
749 * avr.h (AVR_ISA_2xxe): Define.
751 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
753 * mips.h: Update copyright.
754 (INSN_CHIP_MASK): New macro.
755 (INSN_OCTEON): New macro.
756 (CPU_OCTEON): New macro.
757 (OPCODE_IS_MEMBER): Handle Octeon instructions.
759 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
761 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
763 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
765 * avr.h (AVR_ISA_USB162): Add new opcode set.
766 (AVR_ISA_AVR3): Likewise.
768 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
770 * mips.h (INSN_LOONGSON_2E): New.
771 (INSN_LOONGSON_2F): New.
772 (CPU_LOONGSON_2E): New.
773 (CPU_LOONGSON_2F): New.
774 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
776 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
778 * mips.h (INSN_ISA*): Redefine certain values as an
779 enumeration. Update comments.
780 (mips_isa_table): New.
781 (ISA_MIPS*): Redefine to match enumeration.
782 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
785 2007-08-08 Ben Elliston <bje@au.ibm.com>
787 * ppc.h (PPC_OPCODE_PPCPS): New.
789 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
791 * m68k.h: Document j K & E.
793 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
795 * cr16.h: New file for CR16 target.
797 2007-05-02 Alan Modra <amodra@bigpond.net.au>
799 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
801 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
803 * m68k.h (mcfisa_c): New.
804 (mcfusp, mcf_mask): Adjust.
806 2007-04-20 Alan Modra <amodra@bigpond.net.au>
808 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
809 (num_powerpc_operands): Declare.
810 (PPC_OPERAND_SIGNED et al): Redefine as hex.
811 (PPC_OPERAND_PLUS1): Define.
813 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
815 * i386.h (REX_MODE64): Renamed to ...
817 (REX_EXTX): Renamed to ...
819 (REX_EXTY): Renamed to ...
821 (REX_EXTZ): Renamed to ...
824 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
826 * i386.h: Add entries from config/tc-i386.h and move tables
827 to opcodes/i386-opc.h.
829 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
831 * i386.h (FloatDR): Removed.
832 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
834 2007-03-01 Alan Modra <amodra@bigpond.net.au>
836 * spu-insns.h: Add soma double-float insns.
838 2007-02-20 Thiemo Seufer <ths@mips.com>
839 Chao-Ying Fu <fu@mips.com>
841 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
842 (INSN_DSPR2): Add flag for DSP R2 instructions.
843 (M_BALIGN): New macro.
845 2007-02-14 Alan Modra <amodra@bigpond.net.au>
847 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
848 and Seg3ShortFrom with Shortform.
850 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
853 * i386.h (i386_optab): Put the real "test" before the pseudo
856 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
858 * m68k.h (m68010up): OR fido_a.
860 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
862 * m68k.h (fido_a): New.
864 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
866 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
867 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
870 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
872 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
874 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
876 * score-inst.h (enum score_insn_type): Add Insn_internal.
878 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
879 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
880 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
881 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
882 Alan Modra <amodra@bigpond.net.au>
884 * spu-insns.h: New file.
887 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
889 * ppc.h (PPC_OPCODE_CELL): Define.
891 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
893 * i386.h : Modify opcode to support for the change in POPCNT opcode
894 in amdfam10 architecture.
896 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
898 * i386.h: Replace CpuMNI with CpuSSSE3.
900 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
901 Joseph Myers <joseph@codesourcery.com>
902 Ian Lance Taylor <ian@wasabisystems.com>
903 Ben Elliston <bje@wasabisystems.com>
905 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
907 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
909 * score-datadep.h: New file.
910 * score-inst.h: New file.
912 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
914 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
915 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
918 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
919 Michael Meissner <michael.meissner@amd.com>
921 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
923 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
925 * i386.h (i386_optab): Add "nop" with memory reference.
927 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
929 * i386.h (i386_optab): Update comment for 64bit NOP.
931 2006-06-06 Ben Elliston <bje@au.ibm.com>
932 Anton Blanchard <anton@samba.org>
934 * ppc.h (PPC_OPCODE_POWER6): Define.
937 2006-06-05 Thiemo Seufer <ths@mips.com>
939 * mips.h: Improve description of MT flags.
941 2006-05-25 Richard Sandiford <richard@codesourcery.com>
943 * m68k.h (mcf_mask): Define.
945 2006-05-05 Thiemo Seufer <ths@mips.com>
946 David Ung <davidu@mips.com>
948 * mips.h (enum): Add macro M_CACHE_AB.
950 2006-05-04 Thiemo Seufer <ths@mips.com>
951 Nigel Stephens <nigel@mips.com>
952 David Ung <davidu@mips.com>
954 * mips.h: Add INSN_SMARTMIPS define.
956 2006-04-30 Thiemo Seufer <ths@mips.com>
957 David Ung <davidu@mips.com>
959 * mips.h: Defines udi bits and masks. Add description of
960 characters which may appear in the args field of udi
963 2006-04-26 Thiemo Seufer <ths@networkno.de>
965 * mips.h: Improve comments describing the bitfield instruction
968 2006-04-26 Julian Brown <julian@codesourcery.com>
970 * arm.h (FPU_VFP_EXT_V3): Define constant.
971 (FPU_NEON_EXT_V1): Likewise.
972 (FPU_VFP_HARD): Update.
973 (FPU_VFP_V3): Define macro.
974 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
976 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
978 * avr.h (AVR_ISA_PWMx): New.
980 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
982 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
983 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
984 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
985 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
986 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
988 2006-03-10 Paul Brook <paul@codesourcery.com>
990 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
992 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
994 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
995 first. Correct mask of bb "B" opcode.
997 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
999 * i386.h (i386_optab): Support Intel Merom New Instructions.
1001 2006-02-24 Paul Brook <paul@codesourcery.com>
1003 * arm.h: Add V7 feature bits.
1005 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1007 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1009 2006-01-31 Paul Brook <paul@codesourcery.com>
1010 Richard Earnshaw <rearnsha@arm.com>
1012 * arm.h: Use ARM_CPU_FEATURE.
1013 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1014 (arm_feature_set): Change to a structure.
1015 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1016 ARM_FEATURE): New macros.
1018 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
1020 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1021 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1022 (ADD_PC_INCR_OPCODE): Don't define.
1024 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1027 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1029 2005-11-14 David Ung <davidu@mips.com>
1031 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1032 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1033 save/restore encoding of the args field.
1035 2005-10-28 Dave Brolley <brolley@redhat.com>
1037 Contribute the following changes:
1038 2005-02-16 Dave Brolley <brolley@redhat.com>
1040 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1041 cgen_isa_mask_* to cgen_bitset_*.
1044 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1046 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1047 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1048 (CGEN_CPU_TABLE): Make isas a ponter.
1050 2003-09-29 Dave Brolley <brolley@redhat.com>
1052 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1053 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1054 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1056 2002-12-13 Dave Brolley <brolley@redhat.com>
1058 * cgen.h (symcat.h): #include it.
1059 (cgen-bitset.h): #include it.
1060 (CGEN_ATTR_VALUE_TYPE): Now a union.
1061 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1062 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1063 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1064 * cgen-bitset.h: New file.
1066 2005-09-30 Catherine Moore <clm@cm00re.com>
1070 2005-10-24 Jan Beulich <jbeulich@novell.com>
1072 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1075 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1077 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1078 Add FLAG_STRICT to pa10 ftest opcode.
1080 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1082 * hppa.h (pa_opcodes): Remove lha entries.
1084 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1086 * hppa.h (FLAG_STRICT): Revise comment.
1087 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1088 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1091 2005-09-30 Catherine Moore <clm@cm00re.com>
1095 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1097 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1099 2005-09-06 Chao-ying Fu <fu@mips.com>
1101 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1102 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1104 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1105 (INSN_ASE_MASK): Update to include INSN_MT.
1106 (INSN_MT): New define for MT ASE.
1108 2005-08-25 Chao-ying Fu <fu@mips.com>
1110 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1111 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1112 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1113 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1114 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1115 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1117 (INSN_DSP): New define for DSP ASE.
1119 2005-08-18 Alan Modra <amodra@bigpond.net.au>
1123 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1125 * ppc.h (PPC_OPCODE_E300): Define.
1127 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1129 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1131 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1134 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1137 2005-07-27 Jan Beulich <jbeulich@novell.com>
1139 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1140 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1141 Add movq-s as 64-bit variants of movd-s.
1143 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1145 * hppa.h: Fix punctuation in comment.
1147 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1148 implicit space-register addressing. Set space-register bits on opcodes
1149 using implicit space-register addressing. Add various missing pa20
1150 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1151 space-register addressing. Use "fE" instead of "fe" in various
1154 2005-07-18 Jan Beulich <jbeulich@novell.com>
1156 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1158 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1160 * i386.h (i386_optab): Support Intel VMX Instructions.
1162 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1164 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1166 2005-07-05 Jan Beulich <jbeulich@novell.com>
1168 * i386.h (i386_optab): Add new insns.
1170 2005-07-01 Nick Clifton <nickc@redhat.com>
1172 * sparc.h: Add typedefs to structure declarations.
1174 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1177 * i386.h (i386_optab): Update comments for 64bit addressing on
1178 mov. Allow 64bit addressing for mov and movq.
1180 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1182 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1183 respectively, in various floating-point load and store patterns.
1185 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1187 * hppa.h (FLAG_STRICT): Correct comment.
1188 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1189 PA 2.0 mneumonics when equivalent. Entries with cache control
1190 completers now require PA 1.1. Adjust whitespace.
1192 2005-05-19 Anton Blanchard <anton@samba.org>
1194 * ppc.h (PPC_OPCODE_POWER5): Define.
1196 2005-05-10 Nick Clifton <nickc@redhat.com>
1198 * Update the address and phone number of the FSF organization in
1199 the GPL notices in the following files:
1200 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1201 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1202 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1203 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1204 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1205 tic54x.h, tic80.h, v850.h, vax.h
1207 2005-05-09 Jan Beulich <jbeulich@novell.com>
1209 * i386.h (i386_optab): Add ht and hnt.
1211 2005-04-18 Mark Kettenis <kettenis@gnu.org>
1213 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1214 Add xcrypt-ctr. Provide aliases without hyphens.
1216 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1218 Moved from ../ChangeLog
1220 2005-04-12 Paul Brook <paul@codesourcery.com>
1221 * m88k.h: Rename psr macros to avoid conflicts.
1223 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1224 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1225 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1226 and ARM_ARCH_V6ZKT2.
1228 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1229 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1230 Remove redundant instruction types.
1231 (struct argument): X_op - new field.
1232 (struct cst4_entry): Remove.
1233 (no_op_insn): Declare.
1235 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1236 * crx.h (enum argtype): Rename types, remove unused types.
1238 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1239 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1240 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1241 (enum operand_type): Rearrange operands, edit comments.
1242 replace us<N> with ui<N> for unsigned immediate.
1243 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1244 displacements (respectively).
1245 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1246 (instruction type): Add NO_TYPE_INS.
1247 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1248 (operand_entry): New field - 'flags'.
1249 (operand flags): New.
1251 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1252 * crx.h (operand_type): Remove redundant types i3, i4,
1254 Add new unsigned immediate types us3, us4, us5, us16.
1256 2005-04-12 Mark Kettenis <kettenis@gnu.org>
1258 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1259 adjust them accordingly.
1261 2005-04-01 Jan Beulich <jbeulich@novell.com>
1263 * i386.h (i386_optab): Add rdtscp.
1265 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1267 * i386.h (i386_optab): Don't allow the `l' suffix for moving
1268 between memory and segment register. Allow movq for moving between
1269 general-purpose register and segment register.
1271 2005-02-09 Jan Beulich <jbeulich@novell.com>
1274 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1275 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1278 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1280 * m68k.h (m68008, m68ec030, m68882): Remove.
1282 (cpu_m68k, cpu_cf): New.
1283 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1284 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1286 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
1288 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1289 * cgen.h (enum cgen_parse_operand_type): Add
1290 CGEN_PARSE_OPERAND_SYMBOLIC.
1292 2005-01-21 Fred Fish <fnf@specifixinc.com>
1294 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1295 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1296 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1298 2005-01-19 Fred Fish <fnf@specifixinc.com>
1300 * mips.h (struct mips_opcode): Add new pinfo2 member.
1301 (INSN_ALIAS): New define for opcode table entries that are
1302 specific instances of another entry, such as 'move' for an 'or'
1303 with a zero operand.
1304 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1305 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1307 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1309 * mips.h (CPU_RM9000): Define.
1310 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1312 2004-11-25 Jan Beulich <jbeulich@novell.com>
1314 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1315 to/from test registers are illegal in 64-bit mode. Add missing
1316 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1317 (previously one had to explicitly encode a rex64 prefix). Re-enable
1318 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1319 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1321 2004-11-23 Jan Beulich <jbeulich@novell.com>
1323 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1324 available only with SSE2. Change the MMX additions introduced by SSE
1325 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1326 instructions by their now designated identifier (since combining i686
1327 and 3DNow! does not really imply 3DNow!A).
1329 2004-11-19 Alan Modra <amodra@bigpond.net.au>
1331 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1332 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1334 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1335 Vineet Sharma <vineets@noida.hcltech.com>
1337 * maxq.h: New file: Disassembly information for the maxq port.
1339 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1341 * i386.h (i386_optab): Put back "movzb".
1343 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
1345 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1346 comments. Remove member cris_ver_sim. Add members
1347 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1348 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1349 (struct cris_support_reg, struct cris_cond15): New types.
1350 (cris_conds15): Declare.
1351 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1352 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1353 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1354 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1355 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1356 SIZE_FIELD_UNSIGNED.
1358 2004-11-04 Jan Beulich <jbeulich@novell.com>
1360 * i386.h (sldx_Suf): Remove.
1361 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1362 (q_FP): Define, implying no REX64.
1363 (x_FP, sl_FP): Imply FloatMF.
1364 (i386_optab): Split reg and mem forms of moving from segment registers
1365 so that the memory forms can ignore the 16-/32-bit operand size
1366 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1367 all non-floating-point instructions. Unite 32- and 64-bit forms of
1368 movsx, movzx, and movd. Adjust floating point operations for the above
1369 changes to the *FP macros. Add DefaultSize to floating point control
1370 insns operating on larger memory ranges. Remove left over comments
1371 hinting at certain insns being Intel-syntax ones where the ones
1372 actually meant are already gone.
1374 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1376 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1379 2004-09-30 Paul Brook <paul@codesourcery.com>
1381 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1382 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1384 2004-09-11 Theodore A. Roth <troth@openavr.org>
1386 * avr.h: Add support for
1387 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1389 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1391 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1393 2004-08-24 Dmitry Diky <diwil@spec.ru>
1395 * msp430.h (msp430_opc): Add new instructions.
1396 (msp430_rcodes): Declare new instructions.
1397 (msp430_hcodes): Likewise..
1399 2004-08-13 Nick Clifton <nickc@redhat.com>
1402 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1405 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1407 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1409 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1411 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1413 2004-07-21 Jan Beulich <jbeulich@novell.com>
1415 * i386.h: Adjust instruction descriptions to better match the
1418 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
1420 * arm.h: Remove all old content. Replace with architecture defines
1421 from gas/config/tc-arm.c.
1423 2004-07-09 Andreas Schwab <schwab@suse.de>
1425 * m68k.h: Fix comment.
1427 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1431 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1433 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1435 2004-05-24 Peter Barada <peter@the-baradas.com>
1437 * m68k.h: Add 'size' to m68k_opcode.
1439 2004-05-05 Peter Barada <peter@the-baradas.com>
1441 * m68k.h: Switch from ColdFire chip name to core variant.
1443 2004-04-22 Peter Barada <peter@the-baradas.com>
1445 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1446 descriptions for new EMAC cases.
1447 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1448 handle Motorola MAC syntax.
1449 Allow disassembly of ColdFire V4e object files.
1451 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1453 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1455 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1457 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1459 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1461 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1463 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1465 * i386.h (i386_optab): Added xstore/xcrypt insns.
1467 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1469 * h8300.h (32bit ldc/stc): Add relaxing support.
1471 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1473 * h8300.h (BITOP): Pass MEMRELAX flag.
1475 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1477 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1480 For older changes see ChangeLog-9103
1486 version-control: never