1 2011-06-13 Walter Lee <walt@tilera.com>
6 2011-05-31 Paul Brook <paul@codesourcery.com>
8 * arm.h (ARM_ARCH_V7R_IDIV): Define.
10 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
12 * s390.h: Replace S390_OPERAND_REG_EVEN with
13 S390_OPERAND_REG_PAIR.
15 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
17 * s390.h: Add S390_OPCODE_REG_EVEN flag.
19 2011-04-18 Julian Brown <julian@codesourcery.com>
21 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
23 2011-04-11 Dan McDonald <dan@wellkeeper.com>
26 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
28 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
30 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
31 New instruction set flags.
32 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
34 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
36 * mips.h (M_PREF_AB): New enum value.
38 2011-02-12 Mike Frysinger <vapier@gentoo.org>
40 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
42 (is_macmod_pmove, is_macmod_hmove): New functions.
44 2011-02-11 Mike Frysinger <vapier@gentoo.org>
46 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
48 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
50 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
51 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
53 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
56 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
59 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
62 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
64 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
66 * mips.h: Update commentary after last commit.
68 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
70 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
71 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
72 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
74 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
76 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
78 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
80 * mips.h: Fix previous commit.
82 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
84 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
85 (INSN_LOONGSON_3A): Clear bit 31.
87 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
90 * arm.h (ARM_AEXT_V6M_ONLY): New define.
91 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
92 (ARM_ARCH_V6M_ONLY): New define.
94 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
96 * mips.h (INSN_LOONGSON_3A): Defined.
97 (CPU_LOONGSON_3A): Defined.
98 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
100 2010-10-09 Matt Rice <ratmice@gmail.com>
102 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
103 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
105 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
107 * arm.h (ARM_EXT_VIRT): New define.
108 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
109 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
112 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
114 * arm.h (ARM_AEXT_ADIV): New define.
115 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
117 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
119 * arm.h (ARM_EXT_OS): New define.
120 (ARM_AEXT_V6SM): Likewise.
121 (ARM_ARCH_V6SM): Likewise.
123 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
125 * arm.h (ARM_EXT_MP): Add.
126 (ARM_ARCH_V7A_MP): Likewise.
128 2010-09-22 Mike Frysinger <vapier@gentoo.org>
130 * bfin.h: Declare pseudoChr structs/defines.
132 2010-09-21 Mike Frysinger <vapier@gentoo.org>
134 * bfin.h: Strip trailing whitespace.
136 2010-07-29 DJ Delorie <dj@redhat.com>
138 * rx.h (RX_Operand_Type): Add TwoReg.
139 (RX_Opcode_ID): Remove ediv and ediv2.
141 2010-07-27 DJ Delorie <dj@redhat.com>
143 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
145 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
146 Ina Pandit <ina.pandit@kpitcummins.com>
148 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
149 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
150 PROCESSOR_V850E2_ALL.
151 Remove PROCESSOR_V850EA support.
152 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
153 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
154 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
155 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
156 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
157 V850_OPERAND_PERCENT.
158 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
160 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
163 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
165 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
166 (MIPS16_INSN_BRANCH): Rename to...
167 (MIPS16_INSN_COND_BRANCH): ... this.
169 2010-07-03 Alan Modra <amodra@gmail.com>
171 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
172 Renumber other PPC_OPCODE defines.
174 2010-07-03 Alan Modra <amodra@gmail.com>
176 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
178 2010-06-29 Alan Modra <amodra@gmail.com>
180 * maxq.h: Delete file.
182 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
184 * ppc.h (PPC_OPCODE_E500): Define.
186 2010-05-26 Catherine Moore <clm@codesourcery.com>
188 * opcode/mips.h (INSN_MIPS16): Remove.
190 2010-04-21 Joseph Myers <joseph@codesourcery.com>
192 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
194 2010-04-15 Nick Clifton <nickc@redhat.com>
196 * alpha.h: Update copyright notice to use GPLv3.
202 * convex.h: Likewise.
216 * m68hc11.h: Likewise.
222 * mn10200.h: Likewise.
223 * mn10300.h: Likewise.
224 * msp430.h: Likewise.
235 * score-datadep.h: Likewise.
236 * score-inst.h: Likewise.
238 * spu-insns.h: Likewise.
242 * tic54x.h: Likewise.
247 2010-03-25 Joseph Myers <joseph@codesourcery.com>
249 * tic6x-control-registers.h, tic6x-insn-formats.h,
250 tic6x-opcode-table.h, tic6x.h: New.
252 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
254 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
256 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
258 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
260 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
262 * ia64.h (ia64_find_opcode): Remove argument name.
263 (ia64_find_next_opcode): Likewise.
264 (ia64_dis_opcode): Likewise.
265 (ia64_free_opcode): Likewise.
266 (ia64_find_dependency): Likewise.
268 2009-11-22 Doug Evans <dje@sebabeach.org>
270 * cgen.h: Include bfd_stdint.h.
271 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
273 2009-11-18 Paul Brook <paul@codesourcery.com>
275 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
277 2009-11-17 Paul Brook <paul@codesourcery.com>
278 Daniel Jacobowitz <dan@codesourcery.com>
280 * arm.h (ARM_EXT_V6_DSP): Define.
281 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
282 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
284 2009-11-04 DJ Delorie <dj@redhat.com>
286 * rx.h (rx_decode_opcode) (mvtipl): Add.
287 (mvtcp, mvfcp, opecp): Remove.
289 2009-11-02 Paul Brook <paul@codesourcery.com>
291 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
292 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
293 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
294 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
295 FPU_ARCH_NEON_VFP_V4): Define.
297 2009-10-23 Doug Evans <dje@sebabeach.org>
299 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
300 * cgen.h: Update. Improve multi-inclusion macro name.
302 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
304 * ppc.h (PPC_OPCODE_476): Define.
306 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
308 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
310 2009-09-29 DJ Delorie <dj@redhat.com>
314 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
316 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
318 2009-09-21 Ben Elliston <bje@au.ibm.com>
320 * ppc.h (PPC_OPCODE_PPCA2): New.
322 2009-09-05 Martin Thuresson <martin@mtme.org>
324 * ia64.h (struct ia64_operand): Renamed member class to op_class.
326 2009-08-29 Martin Thuresson <martin@mtme.org>
328 * tic30.h (template): Rename type template to
329 insn_template. Updated code to use new name.
330 * tic54x.h (template): Rename type template to
333 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
335 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
337 2009-06-11 Anthony Green <green@moxielogic.com>
339 * moxie.h (MOXIE_F3_PCREL): Define.
340 (moxie_form3_opc_info): Grow.
342 2009-06-06 Anthony Green <green@moxielogic.com>
344 * moxie.h (MOXIE_F1_M): Define.
346 2009-04-15 Anthony Green <green@moxielogic.com>
350 2009-04-06 DJ Delorie <dj@redhat.com>
352 * h8300.h: Add relaxation attributes to MOVA opcodes.
354 2009-03-10 Alan Modra <amodra@bigpond.net.au>
356 * ppc.h (ppc_parse_cpu): Declare.
358 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
360 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
361 and _IMM11 for mbitclr and mbitset.
362 * score-datadep.h: Update dependency information.
364 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
366 * ppc.h (PPC_OPCODE_POWER7): New.
368 2009-02-06 Doug Evans <dje@google.com>
370 * i386.h: Add comment regarding sse* insns and prefixes.
372 2009-02-03 Sandip Matte <sandip@rmicorp.com>
374 * mips.h (INSN_XLR): Define.
375 (INSN_CHIP_MASK): Update.
377 (OPCODE_IS_MEMBER): Update.
378 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
380 2009-01-28 Doug Evans <dje@google.com>
382 * opcode/i386.h: Add multiple inclusion protection.
383 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
384 (EDI_REG_NUM): New macros.
385 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
386 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
387 (REX_PREFIX_P): New macro.
389 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
391 * ppc.h (struct powerpc_opcode): New field "deprecated".
392 (PPC_OPCODE_NOPOWER4): Delete.
394 2008-11-28 Joshua Kinard <kumba@gentoo.org>
396 * mips.h: Define CPU_R14000, CPU_R16000.
397 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
399 2008-11-18 Catherine Moore <clm@codesourcery.com>
401 * arm.h (FPU_NEON_FP16): New.
402 (FPU_ARCH_NEON_FP16): New.
404 2008-11-06 Chao-ying Fu <fu@mips.com>
406 * mips.h: Doucument '1' for 5-bit sync type.
408 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
410 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
413 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
415 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
417 2008-07-30 Michael J. Eager <eager@eagercon.com>
419 * ppc.h (PPC_OPCODE_405): Define.
420 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
422 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
424 * ppc.h (ppc_cpu_t): New typedef.
425 (struct powerpc_opcode <flags>): Use it.
426 (struct powerpc_operand <insert, extract>): Likewise.
427 (struct powerpc_macro <flags>): Likewise.
429 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
431 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
432 Update comment before MIPS16 field descriptors to mention MIPS16.
433 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
435 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
436 New bit masks and shift counts for cins and exts.
438 * mips.h: Document new field descriptors +Q.
439 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
441 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
443 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
444 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
446 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
448 * ppc.h: (PPC_OPCODE_E500MC): New.
450 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
452 * i386.h (MAX_OPERANDS): Set to 5.
453 (MAX_MNEM_SIZE): Changed to 20.
455 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
457 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
459 2008-03-09 Paul Brook <paul@codesourcery.com>
461 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
463 2008-03-04 Paul Brook <paul@codesourcery.com>
465 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
466 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
467 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
469 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
470 Nick Clifton <nickc@redhat.com>
473 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
474 with a 32-bit displacement but without the top bit of the 4th byte
477 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
479 * cr16.h (cr16_num_optab): Declared.
481 2008-02-14 Hakan Ardo <hakan@debian.org>
484 * avr.h (AVR_ISA_2xxe): Define.
486 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
488 * mips.h: Update copyright.
489 (INSN_CHIP_MASK): New macro.
490 (INSN_OCTEON): New macro.
491 (CPU_OCTEON): New macro.
492 (OPCODE_IS_MEMBER): Handle Octeon instructions.
494 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
496 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
498 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
500 * avr.h (AVR_ISA_USB162): Add new opcode set.
501 (AVR_ISA_AVR3): Likewise.
503 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
505 * mips.h (INSN_LOONGSON_2E): New.
506 (INSN_LOONGSON_2F): New.
507 (CPU_LOONGSON_2E): New.
508 (CPU_LOONGSON_2F): New.
509 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
511 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
513 * mips.h (INSN_ISA*): Redefine certain values as an
514 enumeration. Update comments.
515 (mips_isa_table): New.
516 (ISA_MIPS*): Redefine to match enumeration.
517 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
520 2007-08-08 Ben Elliston <bje@au.ibm.com>
522 * ppc.h (PPC_OPCODE_PPCPS): New.
524 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
526 * m68k.h: Document j K & E.
528 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
530 * cr16.h: New file for CR16 target.
532 2007-05-02 Alan Modra <amodra@bigpond.net.au>
534 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
536 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
538 * m68k.h (mcfisa_c): New.
539 (mcfusp, mcf_mask): Adjust.
541 2007-04-20 Alan Modra <amodra@bigpond.net.au>
543 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
544 (num_powerpc_operands): Declare.
545 (PPC_OPERAND_SIGNED et al): Redefine as hex.
546 (PPC_OPERAND_PLUS1): Define.
548 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
550 * i386.h (REX_MODE64): Renamed to ...
552 (REX_EXTX): Renamed to ...
554 (REX_EXTY): Renamed to ...
556 (REX_EXTZ): Renamed to ...
559 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
561 * i386.h: Add entries from config/tc-i386.h and move tables
562 to opcodes/i386-opc.h.
564 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
566 * i386.h (FloatDR): Removed.
567 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
569 2007-03-01 Alan Modra <amodra@bigpond.net.au>
571 * spu-insns.h: Add soma double-float insns.
573 2007-02-20 Thiemo Seufer <ths@mips.com>
574 Chao-Ying Fu <fu@mips.com>
576 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
577 (INSN_DSPR2): Add flag for DSP R2 instructions.
578 (M_BALIGN): New macro.
580 2007-02-14 Alan Modra <amodra@bigpond.net.au>
582 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
583 and Seg3ShortFrom with Shortform.
585 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
588 * i386.h (i386_optab): Put the real "test" before the pseudo
591 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
593 * m68k.h (m68010up): OR fido_a.
595 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
597 * m68k.h (fido_a): New.
599 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
601 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
602 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
605 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
607 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
609 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
611 * score-inst.h (enum score_insn_type): Add Insn_internal.
613 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
614 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
615 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
616 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
617 Alan Modra <amodra@bigpond.net.au>
619 * spu-insns.h: New file.
622 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
624 * ppc.h (PPC_OPCODE_CELL): Define.
626 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
628 * i386.h : Modify opcode to support for the change in POPCNT opcode
629 in amdfam10 architecture.
631 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
633 * i386.h: Replace CpuMNI with CpuSSSE3.
635 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
636 Joseph Myers <joseph@codesourcery.com>
637 Ian Lance Taylor <ian@wasabisystems.com>
638 Ben Elliston <bje@wasabisystems.com>
640 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
642 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
644 * score-datadep.h: New file.
645 * score-inst.h: New file.
647 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
649 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
650 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
653 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
654 Michael Meissner <michael.meissner@amd.com>
656 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
658 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
660 * i386.h (i386_optab): Add "nop" with memory reference.
662 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
664 * i386.h (i386_optab): Update comment for 64bit NOP.
666 2006-06-06 Ben Elliston <bje@au.ibm.com>
667 Anton Blanchard <anton@samba.org>
669 * ppc.h (PPC_OPCODE_POWER6): Define.
672 2006-06-05 Thiemo Seufer <ths@mips.com>
674 * mips.h: Improve description of MT flags.
676 2006-05-25 Richard Sandiford <richard@codesourcery.com>
678 * m68k.h (mcf_mask): Define.
680 2006-05-05 Thiemo Seufer <ths@mips.com>
681 David Ung <davidu@mips.com>
683 * mips.h (enum): Add macro M_CACHE_AB.
685 2006-05-04 Thiemo Seufer <ths@mips.com>
686 Nigel Stephens <nigel@mips.com>
687 David Ung <davidu@mips.com>
689 * mips.h: Add INSN_SMARTMIPS define.
691 2006-04-30 Thiemo Seufer <ths@mips.com>
692 David Ung <davidu@mips.com>
694 * mips.h: Defines udi bits and masks. Add description of
695 characters which may appear in the args field of udi
698 2006-04-26 Thiemo Seufer <ths@networkno.de>
700 * mips.h: Improve comments describing the bitfield instruction
703 2006-04-26 Julian Brown <julian@codesourcery.com>
705 * arm.h (FPU_VFP_EXT_V3): Define constant.
706 (FPU_NEON_EXT_V1): Likewise.
707 (FPU_VFP_HARD): Update.
708 (FPU_VFP_V3): Define macro.
709 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
711 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
713 * avr.h (AVR_ISA_PWMx): New.
715 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
717 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
718 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
719 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
720 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
721 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
723 2006-03-10 Paul Brook <paul@codesourcery.com>
725 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
727 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
729 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
730 first. Correct mask of bb "B" opcode.
732 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
734 * i386.h (i386_optab): Support Intel Merom New Instructions.
736 2006-02-24 Paul Brook <paul@codesourcery.com>
738 * arm.h: Add V7 feature bits.
740 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
742 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
744 2006-01-31 Paul Brook <paul@codesourcery.com>
745 Richard Earnshaw <rearnsha@arm.com>
747 * arm.h: Use ARM_CPU_FEATURE.
748 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
749 (arm_feature_set): Change to a structure.
750 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
751 ARM_FEATURE): New macros.
753 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
755 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
756 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
757 (ADD_PC_INCR_OPCODE): Don't define.
759 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
762 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
764 2005-11-14 David Ung <davidu@mips.com>
766 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
767 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
768 save/restore encoding of the args field.
770 2005-10-28 Dave Brolley <brolley@redhat.com>
772 Contribute the following changes:
773 2005-02-16 Dave Brolley <brolley@redhat.com>
775 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
776 cgen_isa_mask_* to cgen_bitset_*.
779 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
781 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
782 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
783 (CGEN_CPU_TABLE): Make isas a ponter.
785 2003-09-29 Dave Brolley <brolley@redhat.com>
787 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
788 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
789 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
791 2002-12-13 Dave Brolley <brolley@redhat.com>
793 * cgen.h (symcat.h): #include it.
794 (cgen-bitset.h): #include it.
795 (CGEN_ATTR_VALUE_TYPE): Now a union.
796 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
797 (CGEN_ATTR_ENTRY): 'value' now unsigned.
798 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
799 * cgen-bitset.h: New file.
801 2005-09-30 Catherine Moore <clm@cm00re.com>
805 2005-10-24 Jan Beulich <jbeulich@novell.com>
807 * ia64.h (enum ia64_opnd): Move memory operand out of set of
810 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
812 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
813 Add FLAG_STRICT to pa10 ftest opcode.
815 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
817 * hppa.h (pa_opcodes): Remove lha entries.
819 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
821 * hppa.h (FLAG_STRICT): Revise comment.
822 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
823 before corresponding pa11 opcodes. Add strict pa10 register-immediate
826 2005-09-30 Catherine Moore <clm@cm00re.com>
830 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
832 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
834 2005-09-06 Chao-ying Fu <fu@mips.com>
836 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
837 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
839 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
840 (INSN_ASE_MASK): Update to include INSN_MT.
841 (INSN_MT): New define for MT ASE.
843 2005-08-25 Chao-ying Fu <fu@mips.com>
845 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
846 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
847 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
848 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
849 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
850 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
852 (INSN_DSP): New define for DSP ASE.
854 2005-08-18 Alan Modra <amodra@bigpond.net.au>
858 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
860 * ppc.h (PPC_OPCODE_E300): Define.
862 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
864 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
866 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
869 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
872 2005-07-27 Jan Beulich <jbeulich@novell.com>
874 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
875 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
876 Add movq-s as 64-bit variants of movd-s.
878 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
880 * hppa.h: Fix punctuation in comment.
882 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
883 implicit space-register addressing. Set space-register bits on opcodes
884 using implicit space-register addressing. Add various missing pa20
885 long-immediate opcodes. Remove various opcodes using implicit 3-bit
886 space-register addressing. Use "fE" instead of "fe" in various
889 2005-07-18 Jan Beulich <jbeulich@novell.com>
891 * i386.h (i386_optab): Operands of aam and aad are unsigned.
893 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
895 * i386.h (i386_optab): Support Intel VMX Instructions.
897 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
899 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
901 2005-07-05 Jan Beulich <jbeulich@novell.com>
903 * i386.h (i386_optab): Add new insns.
905 2005-07-01 Nick Clifton <nickc@redhat.com>
907 * sparc.h: Add typedefs to structure declarations.
909 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
912 * i386.h (i386_optab): Update comments for 64bit addressing on
913 mov. Allow 64bit addressing for mov and movq.
915 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
917 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
918 respectively, in various floating-point load and store patterns.
920 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
922 * hppa.h (FLAG_STRICT): Correct comment.
923 (pa_opcodes): Update load and store entries to allow both PA 1.X and
924 PA 2.0 mneumonics when equivalent. Entries with cache control
925 completers now require PA 1.1. Adjust whitespace.
927 2005-05-19 Anton Blanchard <anton@samba.org>
929 * ppc.h (PPC_OPCODE_POWER5): Define.
931 2005-05-10 Nick Clifton <nickc@redhat.com>
933 * Update the address and phone number of the FSF organization in
934 the GPL notices in the following files:
935 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
936 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
937 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
938 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
939 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
940 tic54x.h, tic80.h, v850.h, vax.h
942 2005-05-09 Jan Beulich <jbeulich@novell.com>
944 * i386.h (i386_optab): Add ht and hnt.
946 2005-04-18 Mark Kettenis <kettenis@gnu.org>
948 * i386.h: Insert hyphens into selected VIA PadLock extensions.
949 Add xcrypt-ctr. Provide aliases without hyphens.
951 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
953 Moved from ../ChangeLog
955 2005-04-12 Paul Brook <paul@codesourcery.com>
956 * m88k.h: Rename psr macros to avoid conflicts.
958 2005-03-12 Zack Weinberg <zack@codesourcery.com>
959 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
960 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
963 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
964 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
965 Remove redundant instruction types.
966 (struct argument): X_op - new field.
967 (struct cst4_entry): Remove.
968 (no_op_insn): Declare.
970 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
971 * crx.h (enum argtype): Rename types, remove unused types.
973 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
974 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
975 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
976 (enum operand_type): Rearrange operands, edit comments.
977 replace us<N> with ui<N> for unsigned immediate.
978 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
979 displacements (respectively).
980 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
981 (instruction type): Add NO_TYPE_INS.
982 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
983 (operand_entry): New field - 'flags'.
984 (operand flags): New.
986 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
987 * crx.h (operand_type): Remove redundant types i3, i4,
989 Add new unsigned immediate types us3, us4, us5, us16.
991 2005-04-12 Mark Kettenis <kettenis@gnu.org>
993 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
994 adjust them accordingly.
996 2005-04-01 Jan Beulich <jbeulich@novell.com>
998 * i386.h (i386_optab): Add rdtscp.
1000 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1002 * i386.h (i386_optab): Don't allow the `l' suffix for moving
1003 between memory and segment register. Allow movq for moving between
1004 general-purpose register and segment register.
1006 2005-02-09 Jan Beulich <jbeulich@novell.com>
1009 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1010 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1013 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1015 * m68k.h (m68008, m68ec030, m68882): Remove.
1017 (cpu_m68k, cpu_cf): New.
1018 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1019 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1021 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
1023 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1024 * cgen.h (enum cgen_parse_operand_type): Add
1025 CGEN_PARSE_OPERAND_SYMBOLIC.
1027 2005-01-21 Fred Fish <fnf@specifixinc.com>
1029 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1030 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1031 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1033 2005-01-19 Fred Fish <fnf@specifixinc.com>
1035 * mips.h (struct mips_opcode): Add new pinfo2 member.
1036 (INSN_ALIAS): New define for opcode table entries that are
1037 specific instances of another entry, such as 'move' for an 'or'
1038 with a zero operand.
1039 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1040 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1042 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1044 * mips.h (CPU_RM9000): Define.
1045 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1047 2004-11-25 Jan Beulich <jbeulich@novell.com>
1049 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1050 to/from test registers are illegal in 64-bit mode. Add missing
1051 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1052 (previously one had to explicitly encode a rex64 prefix). Re-enable
1053 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1054 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1056 2004-11-23 Jan Beulich <jbeulich@novell.com>
1058 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1059 available only with SSE2. Change the MMX additions introduced by SSE
1060 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1061 instructions by their now designated identifier (since combining i686
1062 and 3DNow! does not really imply 3DNow!A).
1064 2004-11-19 Alan Modra <amodra@bigpond.net.au>
1066 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1067 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1069 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1070 Vineet Sharma <vineets@noida.hcltech.com>
1072 * maxq.h: New file: Disassembly information for the maxq port.
1074 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1076 * i386.h (i386_optab): Put back "movzb".
1078 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
1080 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1081 comments. Remove member cris_ver_sim. Add members
1082 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1083 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1084 (struct cris_support_reg, struct cris_cond15): New types.
1085 (cris_conds15): Declare.
1086 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1087 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1088 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1089 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1090 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1091 SIZE_FIELD_UNSIGNED.
1093 2004-11-04 Jan Beulich <jbeulich@novell.com>
1095 * i386.h (sldx_Suf): Remove.
1096 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1097 (q_FP): Define, implying no REX64.
1098 (x_FP, sl_FP): Imply FloatMF.
1099 (i386_optab): Split reg and mem forms of moving from segment registers
1100 so that the memory forms can ignore the 16-/32-bit operand size
1101 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1102 all non-floating-point instructions. Unite 32- and 64-bit forms of
1103 movsx, movzx, and movd. Adjust floating point operations for the above
1104 changes to the *FP macros. Add DefaultSize to floating point control
1105 insns operating on larger memory ranges. Remove left over comments
1106 hinting at certain insns being Intel-syntax ones where the ones
1107 actually meant are already gone.
1109 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1111 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1114 2004-09-30 Paul Brook <paul@codesourcery.com>
1116 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1117 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1119 2004-09-11 Theodore A. Roth <troth@openavr.org>
1121 * avr.h: Add support for
1122 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1124 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1126 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1128 2004-08-24 Dmitry Diky <diwil@spec.ru>
1130 * msp430.h (msp430_opc): Add new instructions.
1131 (msp430_rcodes): Declare new instructions.
1132 (msp430_hcodes): Likewise..
1134 2004-08-13 Nick Clifton <nickc@redhat.com>
1137 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1140 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1142 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1144 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1146 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1148 2004-07-21 Jan Beulich <jbeulich@novell.com>
1150 * i386.h: Adjust instruction descriptions to better match the
1153 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
1155 * arm.h: Remove all old content. Replace with architecture defines
1156 from gas/config/tc-arm.c.
1158 2004-07-09 Andreas Schwab <schwab@suse.de>
1160 * m68k.h: Fix comment.
1162 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1166 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1168 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1170 2004-05-24 Peter Barada <peter@the-baradas.com>
1172 * m68k.h: Add 'size' to m68k_opcode.
1174 2004-05-05 Peter Barada <peter@the-baradas.com>
1176 * m68k.h: Switch from ColdFire chip name to core variant.
1178 2004-04-22 Peter Barada <peter@the-baradas.com>
1180 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1181 descriptions for new EMAC cases.
1182 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1183 handle Motorola MAC syntax.
1184 Allow disassembly of ColdFire V4e object files.
1186 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1188 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1190 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1192 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1194 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1196 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1198 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1200 * i386.h (i386_optab): Added xstore/xcrypt insns.
1202 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1204 * h8300.h (32bit ldc/stc): Add relaxing support.
1206 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1208 * h8300.h (BITOP): Pass MEMRELAX flag.
1210 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1212 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1215 For older changes see ChangeLog-9103
1221 version-control: never