1 2014-10-09 Jose E. Marchesi <jose.marchesi@oracle.com>
3 * sparc.h (sparc_opcode): new field `hwcaps2'.
4 (HWCAP2_FJATHPLUS): New define.
5 (HWCAP2_VIS3B): Likewise.
6 (HWCAP2_ADP): Likewise.
7 (HWCAP2_SPARC5): Likewise.
8 (HWCAP2_MWAIT): Likewise.
9 (HWCAP2_XMPMUL): Likewise.
10 (HWCAP2_XMONT): Likewise.
11 (HWCAP2_NSEC): Likewise.
12 (HWCAP2_FJATHHPC): Likewise.
13 (HWCAP2_FJDES): Likewise.
14 (HWCAP2_FJAES): Likewise.
15 Document the new operand kind `{', corresponding to the mcdper
16 ancillary state register.
17 Document the new operand kind }, which represents frsd floating
18 point registers (double precision) which must be the same than
19 frs1 in its containing instruction.
21 2014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
23 * nds32.h: Add new opcode declaration.
25 2014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
26 Matthew Fortune <matthew.fortune@imgtec.com>
28 * mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT,
29 OP_CHECK_PREV and OP_NON_ZERO_REG. Add descriptions for the MIPS R6
30 instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B,
31 +I, +O, +R, +:, +\, +", +;
32 (mips_check_prev_operand): New struct.
33 (INSN2_FORBIDDEN_SLOT): New define.
34 (INSN_ISA32R6): New define.
35 (INSN_ISA64R6): New define.
36 (INSN_UPTO32R6): New define.
37 (INSN_UPTO64R6): New define.
38 (mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6.
39 (ISA_MIPS32R6): New define.
40 (ISA_MIPS64R6): New define.
41 (CPU_MIPS32R6): New define.
42 (CPU_MIPS64R6): New define.
43 (cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6.
45 2014-09-03 Jiong Wang <jiong.wang@arm.com>
47 * aarch64.h (AARCH64_FEATURE_LSE): New feature added.
48 (aarch64_opnd): Add AARCH64_OPND_PAIRREG.
49 (aarch64_insn_class): Add lse_atomic.
50 (F_LSE_SZ): New field added.
51 (opcode_has_special_coder): Recognize F_LSE_SZ.
53 2014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
55 * mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B'
58 2014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
60 * mips.h (INSN_LOAD_COPROC_DELAY): Rename to...
61 (INSN_LOAD_COPROC): New define.
62 (INSN_COPROC_MOVE_DELAY): Rename to...
63 (INSN_COPROC_MOVE): New define.
65 2014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
66 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
67 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
68 Soundararajan <Sounderarajan.D@atmel.com>
70 * avr.h (AVR_ISA_TINY): Define avrtiny specific ISA.
71 (AVR_ISA_2xxxa): Define ISA without LPM.
72 (AVR_ISA_AVRTINY): Define avrtiny arch ISA.
73 Add doc for contraint used in 16 bit lds/sts.
74 Adjust ISA group for icall, ijmp, pop and push.
75 Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints.
77 2014-05-19 Nick Clifton <nickc@redhat.com>
79 * msp430.h (struct msp430_operand_s): Add vshift field.
81 2014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
83 * mips.h (INSN_ISA_MASK): Updated.
84 (INSN_ISA32R3): New define.
85 (INSN_ISA32R5): New define.
86 (INSN_ISA64R3): New define.
87 (INSN_ISA64R5): New define.
88 (INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
89 INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
90 (mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
92 (INSN_UPTO32R3): New define.
93 (INSN_UPTO32R5): New define.
94 (INSN_UPTO64R3): New define.
95 (INSN_UPTO64R5): New define.
96 (ISA_MIPS32R3): New define.
97 (ISA_MIPS32R5): New define.
98 (ISA_MIPS64R3): New define.
99 (ISA_MIPS64R5): New define.
100 (CPU_MIPS32R3): New define.
101 (CPU_MIPS32R5): New define.
102 (CPU_MIPS64R3): New define.
103 (CPU_MIPS64R5): New define.
105 2014-05-01 Richard Sandiford <rdsandiford@googlemail.com>
107 * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values.
109 2014-04-22 Christian Svensson <blue@cmd.nu>
113 2014-03-05 Alan Modra <amodra@gmail.com>
115 Update copyright years.
117 2013-12-16 Andrew Bennett <andrew.bennett@imgtec.com>
119 * mips.h: Updated description of +o, +u, +v and +w for MIPS and
122 2013-12-13 Kuan-Lin Chen <kuanlinchentw@gmail.com>
123 Wei-Cheng Wang <cole945@gmail.com>
125 * nds32.h: New file for Andes NDS32.
127 2013-12-07 Mike Frysinger <vapier@gentoo.org>
129 * bfin.h: Remove +x file mode.
131 2013-11-20 Yufeng Zhang <yufeng.zhang@arm.com>
133 * aarch64.h (aarch64_pstatefields): Change element type to
136 2013-11-18 Renlin Li <Renlin.Li@arm.com>
138 * arm.h (ARM_AEXT_V7VE): New define.
139 (ARM_ARCH_V7VE): New define.
140 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
142 2013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
146 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
148 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
149 (aarch64_sys_reg_writeonly_p): Ditto.
151 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
153 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
154 (aarch64_sys_reg_writeonly_p): Ditto.
156 2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
158 * aarch64.h (aarch64_sys_reg): New typedef.
159 (aarch64_sys_regs): Change to define with the new type.
160 (aarch64_sys_reg_deprecated_p): Declare.
162 2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
164 * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
165 (enum aarch64_opnd): Add AARCH64_OPND_COND1.
167 2013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
169 * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
170 (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
171 For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
172 +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
173 For MIPS, update extension character sequences after +.
174 (ASE_MSA): New define.
175 (ASE_MSA64): New define.
176 For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
177 +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
178 For microMIPS, update extension character sequences after +.
180 2013-08-23 Yuri Chornoivan <yurchor@ukr.net>
185 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
187 * mips.h: Remove references to "+I" and imm2_expr.
189 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
191 * mips.h (M_DEXT, M_DINS): Delete.
193 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
195 * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
196 (mips_optional_operand_p): New function.
198 2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
199 Richard Sandiford <rdsandiford@googlemail.com>
201 * mips.h: Document new VU0 operand characters.
202 (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
203 (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
204 (OP_REG_R5900_ACC): New mips_reg_operand_types.
205 (INSN2_VU0_CHANNEL_SUFFIX): New macro.
206 (mips_vu0_channel_mask): Declare.
208 2013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
210 * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
211 (mips_int_operand_min, mips_int_operand_max): New functions.
212 (mips_decode_pcrel_operand): Use mips_decode_int_operand.
214 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
216 * mips.h (mips_decode_reg_operand): New function.
217 (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
218 (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
219 (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
221 (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
222 (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
223 (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
224 (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
225 (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
226 (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
227 (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
228 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
229 (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
230 (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
231 macros to cover the gaps.
232 (INSN2_MOD_SP): Replace with...
233 (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
234 (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
235 (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
236 (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
237 (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
240 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
242 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
243 (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
244 (MIPS16_INSN_COND_BRANCH): Delete.
246 2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
247 Kirill Yukhin <kirill.yukhin@intel.com>
248 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
250 * i386.h (BND_PREFIX_OPCODE): New.
252 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
254 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
255 OP_SAVE_RESTORE_LIST.
256 (decode_mips16_operand): Declare.
258 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
260 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
261 (mips_operand, mips_int_operand, mips_mapped_int_operand)
262 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
263 (mips_pcrel_operand): New structures.
264 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
265 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
266 (decode_mips_operand, decode_micromips_operand): Declare.
268 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
270 * mips.h: Document MIPS16 "I" opcode.
272 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
274 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
275 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
276 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
277 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
278 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
279 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
280 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
281 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
282 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
283 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
284 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
285 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
286 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
288 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
289 (M_USD_AB): ...these.
291 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
293 * mips.h: Remove documentation of "[" and "]". Update documentation
294 of "k" and the MDMX formats.
296 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
298 * mips.h: Update documentation of "+s" and "+S".
300 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
302 * mips.h: Document "+i".
304 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
306 * mips.h: Remove "mi" documentation. Update "mh" documentation.
307 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
309 (INSN2_WRITE_GPR_MHI): Rename to...
310 (INSN2_WRITE_GPR_MH): ...this.
312 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
314 * mips.h: Remove documentation of "+D" and "+T".
316 2013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
318 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
319 Use "source" rather than "destination" for microMIPS "G".
321 2013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
323 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
326 2013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
328 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
330 2013-06-17 Catherine Moore <clm@codesourcery.com>
331 Maciej W. Rozycki <macro@codesourcery.com>
332 Chao-Ying Fu <fu@mips.com>
334 * mips.h (OP_SH_EVAOFFSET): Define.
335 (OP_MASK_EVAOFFSET): Define.
336 (INSN_ASE_MASK): Delete.
338 (M_CACHEE_AB, M_CACHEE_OB): New.
339 (M_LBE_OB, M_LBE_AB): New.
340 (M_LBUE_OB, M_LBUE_AB): New.
341 (M_LHE_OB, M_LHE_AB): New.
342 (M_LHUE_OB, M_LHUE_AB): New.
343 (M_LLE_AB, M_LLE_OB): New.
344 (M_LWE_OB, M_LWE_AB): New.
345 (M_LWLE_AB, M_LWLE_OB): New.
346 (M_LWRE_AB, M_LWRE_OB): New.
347 (M_PREFE_AB, M_PREFE_OB): New.
348 (M_SCE_AB, M_SCE_OB): New.
349 (M_SBE_OB, M_SBE_AB): New.
350 (M_SHE_OB, M_SHE_AB): New.
351 (M_SWE_OB, M_SWE_AB): New.
352 (M_SWLE_AB, M_SWLE_OB): New.
353 (M_SWRE_AB, M_SWRE_OB): New.
354 (MICROMIPSOP_SH_EVAOFFSET): Define.
355 (MICROMIPSOP_MASK_EVAOFFSET): Define.
357 2013-06-12 Sandra Loosemore <sandra@codesourcery.com>
359 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
361 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
363 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
365 2013-05-09 Andrew Pinski <apinski@cavium.com>
367 * mips.h (OP_MASK_CODE10): Correct definition.
368 (OP_SH_CODE10): Likewise.
369 Add a comment that "+J" is used now for OP_*CODE10.
370 (INSN_ASE_MASK): Update.
371 (INSN_VIRT): New macro.
372 (INSN_VIRT64): New macro
374 2013-05-02 Nick Clifton <nickc@redhat.com>
376 * msp430.h: Add patterns for MSP430X instructions.
378 2013-04-06 David S. Miller <davem@davemloft.net>
380 * sparc.h (F_PREFERRED): Define.
381 (F_PREF_ALIAS): Define.
383 2013-04-03 Nick Clifton <nickc@redhat.com>
385 * v850.h (V850_INVERSE_PCREL): Define.
387 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
390 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
392 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
395 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
397 * tic6xc-opcode-table.h: Add 16-bit insns.
398 * tic6x.h: Add support for 16-bit insns.
400 2013-03-21 Michael Schewe <michael.schewe@gmx.net>
402 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
403 and mov.b/w/l Rs,@(d:32,ERd).
405 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
408 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
409 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
410 tic6x_operand_xregpair operand coding type.
411 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
412 opcode field, usu ORXREGD1324 for the src2 operand and remove the
415 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
418 * tic6x.h (enum tic6x_coding_method): Add
419 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
420 separately the msb and lsb of a register pair. This is needed to
421 encode the opcodes in the same way as TI assembler does.
422 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
423 and rsqrdp opcodes to use the new field coding types.
425 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
427 * arm.h (CRC_EXT_ARMV8): New constant.
428 (ARCH_CRC_ARMV8): New macro.
430 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
432 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
434 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
435 Andrew Jenner <andrew@codesourcery.com>
437 Based on patches from Altera Corporation.
441 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
443 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
445 2013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
448 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
450 2013-01-24 Nick Clifton <nickc@redhat.com>
452 * v850.h: Add e3v5 support.
454 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
456 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
458 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
460 * ppc.h (PPC_OPCODE_POWER8): New define.
461 (PPC_OPCODE_HTM): Likewise.
463 2013-01-10 Will Newton <will.newton@imgtec.com>
467 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
469 * cr16.h (make_instruction): Rename to cr16_make_instruction.
470 (match_opcode): Rename to cr16_match_opcode.
472 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
474 * mips.h: Add support for r5900 instructions including lq and sq.
476 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
478 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
479 (make_instruction,match_opcode): Added function prototypes.
480 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
482 2012-11-23 Alan Modra <amodra@gmail.com>
484 * ppc.h (ppc_parse_cpu): Update prototype.
486 2012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
488 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
489 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
491 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
493 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
495 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
497 * ia64.h (ia64_opnd): Add new operand types.
499 2012-08-21 David S. Miller <davem@davemloft.net>
501 * sparc.h (F3F4): New macro.
503 2012-08-13 Ian Bolton <ian.bolton@arm.com>
504 Laurent Desnogues <laurent.desnogues@arm.com>
505 Jim MacArthur <jim.macarthur@arm.com>
506 Marcus Shawcroft <marcus.shawcroft@arm.com>
507 Nigel Stephens <nigel.stephens@arm.com>
508 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
509 Richard Earnshaw <rearnsha@arm.com>
510 Sofiane Naci <sofiane.naci@arm.com>
511 Tejas Belagod <tejas.belagod@arm.com>
512 Yufeng Zhang <yufeng.zhang@arm.com>
514 * aarch64.h: New file.
516 2012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
517 Maciej W. Rozycki <macro@codesourcery.com>
519 * mips.h (mips_opcode): Add the exclusions field.
520 (OPCODE_IS_MEMBER): Remove macro.
521 (cpu_is_member): New inline function.
522 (opcode_is_member): Likewise.
524 2012-07-31 Chao-Ying Fu <fu@mips.com>
525 Catherine Moore <clm@codesourcery.com>
526 Maciej W. Rozycki <macro@codesourcery.com>
528 * mips.h: Document microMIPS DSP ASE usage.
529 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
530 microMIPS DSP ASE support.
531 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
532 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
533 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
534 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
535 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
536 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
537 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
539 2012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
541 * mips.h: Fix a typo in description.
543 2012-06-07 Georg-Johann Lay <avr@gjlay.de>
545 * avr.h: (AVR_ISA_XCH): New define.
546 (AVR_ISA_XMEGA): Use it.
547 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
549 2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
551 * m68hc11.h: Add XGate definitions.
552 (struct m68hc11_opcode): Add xg_mask field.
554 2012-05-14 Catherine Moore <clm@codesourcery.com>
555 Maciej W. Rozycki <macro@codesourcery.com>
556 Rhonda Wittels <rhonda@codesourcery.com>
558 * ppc.h (PPC_OPCODE_VLE): New definition.
559 (PPC_OP_SA): New macro.
560 (PPC_OP_SE_VLE): New macro.
561 (PPC_OP): Use a variable shift amount.
562 (powerpc_operand): Update comments.
563 (PPC_OPSHIFT_INV): New macro.
564 (PPC_OPERAND_CR): Replace with...
565 (PPC_OPERAND_CR_BIT): ...this and
566 (PPC_OPERAND_CR_REG): ...this.
569 2012-05-03 Sean Keys <skeys@ipdatasys.com>
571 * xgate.h: Header file for XGATE assembler.
573 2012-04-27 David S. Miller <davem@davemloft.net>
575 * sparc.h: Document new arg code' )' for crypto RS3
578 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
579 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
580 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
581 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
582 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
583 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
584 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
585 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
586 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
587 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
588 HWCAP_CBCOND, HWCAP_CRC32): New defines.
590 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
592 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
594 2012-02-27 Alan Modra <amodra@gmail.com>
596 * crx.h (cst4_map): Update declaration.
598 2012-02-25 Walter Lee <walt@tilera.com>
600 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
602 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
603 TILEPRO_OPC_LW_TLS_SN.
605 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
607 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
608 (XRELEASE_PREFIX_OPCODE): Likewise.
610 2011-12-08 Andrew Pinski <apinski@cavium.com>
611 Adam Nemet <anemet@caviumnetworks.com>
613 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
614 (INSN_OCTEON2): New macro.
615 (CPU_OCTEON2): New macro.
616 (OPCODE_IS_MEMBER): Add Octeon2.
618 2011-11-29 Andrew Pinski <apinski@cavium.com>
620 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
621 (INSN_OCTEONP): New macro.
622 (CPU_OCTEONP): New macro.
623 (OPCODE_IS_MEMBER): Add Octeon+.
624 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
626 2011-11-01 DJ Delorie <dj@redhat.com>
630 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
632 * mips.h: Fix a typo in description.
634 2011-09-21 David S. Miller <davem@davemloft.net>
636 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
637 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
638 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
639 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
641 2011-08-09 Chao-ying Fu <fu@mips.com>
642 Maciej W. Rozycki <macro@codesourcery.com>
644 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
645 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
646 (INSN_ASE_MASK): Add the MCU bit.
647 (INSN_MCU): New macro.
648 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
649 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
651 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
653 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
654 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
655 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
656 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
657 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
658 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
659 (INSN2_READ_GPR_MMN): Likewise.
660 (INSN2_READ_FPR_D): Change the bit used.
661 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
662 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
663 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
664 (INSN2_COND_BRANCH): Likewise.
665 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
666 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
667 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
668 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
669 (INSN2_MOD_GPR_MN): Likewise.
671 2011-08-05 David S. Miller <davem@davemloft.net>
673 * sparc.h: Document new format codes '4', '5', and '('.
674 (OPF_LOW4, RS3): New macros.
676 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
678 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
679 order of flags documented.
681 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
683 * mips.h: Clarify the description of microMIPS instruction
685 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
687 2011-07-24 Chao-ying Fu <fu@mips.com>
688 Maciej W. Rozycki <macro@codesourcery.com>
690 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
691 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
692 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
693 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
694 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
695 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
696 (OP_MASK_RS3, OP_SH_RS3): Likewise.
697 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
698 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
699 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
700 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
701 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
702 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
703 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
704 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
705 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
706 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
707 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
708 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
709 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
710 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
711 (INSN_WRITE_GPR_S): New macro.
712 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
713 (INSN2_READ_FPR_D): Likewise.
714 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
715 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
716 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
717 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
718 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
719 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
720 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
721 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
722 (CPU_MICROMIPS): New macro.
723 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
724 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
725 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
726 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
727 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
728 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
729 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
730 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
731 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
732 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
733 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
734 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
735 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
736 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
737 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
738 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
739 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
740 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
741 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
742 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
743 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
744 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
745 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
746 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
747 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
748 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
749 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
750 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
751 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
752 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
753 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
754 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
755 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
756 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
757 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
758 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
759 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
760 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
761 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
762 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
763 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
764 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
765 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
766 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
767 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
768 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
769 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
770 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
771 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
772 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
773 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
774 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
775 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
776 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
777 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
778 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
779 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
780 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
781 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
782 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
783 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
784 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
785 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
786 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
787 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
788 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
789 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
790 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
791 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
792 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
793 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
794 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
795 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
796 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
797 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
798 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
799 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
800 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
801 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
802 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
803 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
804 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
805 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
806 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
807 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
808 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
809 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
810 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
811 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
812 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
813 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
814 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
815 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
816 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
817 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
818 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
819 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
820 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
821 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
822 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
823 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
824 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
825 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
826 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
827 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
828 (micromips_opcodes): New declaration.
829 (bfd_micromips_num_opcodes): Likewise.
831 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
833 * mips.h (INSN_TRAP): Rename to...
834 (INSN_NO_DELAY_SLOT): ... this.
835 (INSN_SYNC): Remove macro.
837 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
839 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
840 a duplicate of AVR_ISA_SPM.
842 2011-07-01 Nick Clifton <nickc@redhat.com>
844 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
846 2011-06-18 Robin Getz <robin.getz@analog.com>
848 * bfin.h (is_macmod_signed): New func
850 2011-06-18 Mike Frysinger <vapier@gentoo.org>
852 * bfin.h (is_macmod_pmove): Add missing space before func args.
853 (is_macmod_hmove): Likewise.
855 2011-06-13 Walter Lee <walt@tilera.com>
857 * tilegx.h: New file.
858 * tilepro.h: New file.
860 2011-05-31 Paul Brook <paul@codesourcery.com>
862 * arm.h (ARM_ARCH_V7R_IDIV): Define.
864 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
866 * s390.h: Replace S390_OPERAND_REG_EVEN with
867 S390_OPERAND_REG_PAIR.
869 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
871 * s390.h: Add S390_OPCODE_REG_EVEN flag.
873 2011-04-18 Julian Brown <julian@codesourcery.com>
875 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
877 2011-04-11 Dan McDonald <dan@wellkeeper.com>
880 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
882 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
884 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
885 New instruction set flags.
886 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
888 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
890 * mips.h (M_PREF_AB): New enum value.
892 2011-02-12 Mike Frysinger <vapier@gentoo.org>
894 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
896 (is_macmod_pmove, is_macmod_hmove): New functions.
898 2011-02-11 Mike Frysinger <vapier@gentoo.org>
900 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
902 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
904 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
905 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
907 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
910 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
913 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
916 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
918 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
920 * mips.h: Update commentary after last commit.
922 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
924 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
925 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
926 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
928 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
930 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
932 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
934 * mips.h: Fix previous commit.
936 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
938 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
939 (INSN_LOONGSON_3A): Clear bit 31.
941 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
944 * arm.h (ARM_AEXT_V6M_ONLY): New define.
945 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
946 (ARM_ARCH_V6M_ONLY): New define.
948 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
950 * mips.h (INSN_LOONGSON_3A): Defined.
951 (CPU_LOONGSON_3A): Defined.
952 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
954 2010-10-09 Matt Rice <ratmice@gmail.com>
956 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
957 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
959 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
961 * arm.h (ARM_EXT_VIRT): New define.
962 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
963 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
966 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
968 * arm.h (ARM_AEXT_ADIV): New define.
969 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
971 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
973 * arm.h (ARM_EXT_OS): New define.
974 (ARM_AEXT_V6SM): Likewise.
975 (ARM_ARCH_V6SM): Likewise.
977 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
979 * arm.h (ARM_EXT_MP): Add.
980 (ARM_ARCH_V7A_MP): Likewise.
982 2010-09-22 Mike Frysinger <vapier@gentoo.org>
984 * bfin.h: Declare pseudoChr structs/defines.
986 2010-09-21 Mike Frysinger <vapier@gentoo.org>
988 * bfin.h: Strip trailing whitespace.
990 2010-07-29 DJ Delorie <dj@redhat.com>
992 * rx.h (RX_Operand_Type): Add TwoReg.
993 (RX_Opcode_ID): Remove ediv and ediv2.
995 2010-07-27 DJ Delorie <dj@redhat.com>
997 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
999 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
1000 Ina Pandit <ina.pandit@kpitcummins.com>
1002 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
1003 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
1004 PROCESSOR_V850E2_ALL.
1005 Remove PROCESSOR_V850EA support.
1006 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
1007 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
1008 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
1009 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
1010 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
1011 V850_OPERAND_PERCENT.
1012 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
1014 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
1017 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
1019 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
1020 (MIPS16_INSN_BRANCH): Rename to...
1021 (MIPS16_INSN_COND_BRANCH): ... this.
1023 2010-07-03 Alan Modra <amodra@gmail.com>
1025 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
1026 Renumber other PPC_OPCODE defines.
1028 2010-07-03 Alan Modra <amodra@gmail.com>
1030 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
1032 2010-06-29 Alan Modra <amodra@gmail.com>
1034 * maxq.h: Delete file.
1036 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
1038 * ppc.h (PPC_OPCODE_E500): Define.
1040 2010-05-26 Catherine Moore <clm@codesourcery.com>
1042 * opcode/mips.h (INSN_MIPS16): Remove.
1044 2010-04-21 Joseph Myers <joseph@codesourcery.com>
1046 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
1048 2010-04-15 Nick Clifton <nickc@redhat.com>
1050 * alpha.h: Update copyright notice to use GPLv3.
1056 * convex.h: Likewise.
1063 * h8300.h: Likewise.
1070 * m68hc11.h: Likewise.
1076 * mn10200.h: Likewise.
1077 * mn10300.h: Likewise.
1078 * msp430.h: Likewise.
1080 * ns32k.h: Likewise.
1082 * pdp11.h: Likewise.
1089 * score-datadep.h: Likewise.
1090 * score-inst.h: Likewise.
1091 * sparc.h: Likewise.
1092 * spu-insns.h: Likewise.
1094 * tic30.h: Likewise.
1095 * tic4x.h: Likewise.
1096 * tic54x.h: Likewise.
1097 * tic80.h: Likewise.
1101 2010-03-25 Joseph Myers <joseph@codesourcery.com>
1103 * tic6x-control-registers.h, tic6x-insn-formats.h,
1104 tic6x-opcode-table.h, tic6x.h: New.
1106 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
1108 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
1110 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
1112 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
1114 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
1116 * ia64.h (ia64_find_opcode): Remove argument name.
1117 (ia64_find_next_opcode): Likewise.
1118 (ia64_dis_opcode): Likewise.
1119 (ia64_free_opcode): Likewise.
1120 (ia64_find_dependency): Likewise.
1122 2009-11-22 Doug Evans <dje@sebabeach.org>
1124 * cgen.h: Include bfd_stdint.h.
1125 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
1127 2009-11-18 Paul Brook <paul@codesourcery.com>
1129 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
1131 2009-11-17 Paul Brook <paul@codesourcery.com>
1132 Daniel Jacobowitz <dan@codesourcery.com>
1134 * arm.h (ARM_EXT_V6_DSP): Define.
1135 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
1136 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
1138 2009-11-04 DJ Delorie <dj@redhat.com>
1140 * rx.h (rx_decode_opcode) (mvtipl): Add.
1141 (mvtcp, mvfcp, opecp): Remove.
1143 2009-11-02 Paul Brook <paul@codesourcery.com>
1145 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
1146 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
1147 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
1148 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
1149 FPU_ARCH_NEON_VFP_V4): Define.
1151 2009-10-23 Doug Evans <dje@sebabeach.org>
1153 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
1154 * cgen.h: Update. Improve multi-inclusion macro name.
1156 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
1158 * ppc.h (PPC_OPCODE_476): Define.
1160 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
1162 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1164 2009-09-29 DJ Delorie <dj@redhat.com>
1168 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
1170 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1172 2009-09-21 Ben Elliston <bje@au.ibm.com>
1174 * ppc.h (PPC_OPCODE_PPCA2): New.
1176 2009-09-05 Martin Thuresson <martin@mtme.org>
1178 * ia64.h (struct ia64_operand): Renamed member class to op_class.
1180 2009-08-29 Martin Thuresson <martin@mtme.org>
1182 * tic30.h (template): Rename type template to
1183 insn_template. Updated code to use new name.
1184 * tic54x.h (template): Rename type template to
1187 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
1189 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1191 2009-06-11 Anthony Green <green@moxielogic.com>
1193 * moxie.h (MOXIE_F3_PCREL): Define.
1194 (moxie_form3_opc_info): Grow.
1196 2009-06-06 Anthony Green <green@moxielogic.com>
1198 * moxie.h (MOXIE_F1_M): Define.
1200 2009-04-15 Anthony Green <green@moxielogic.com>
1204 2009-04-06 DJ Delorie <dj@redhat.com>
1206 * h8300.h: Add relaxation attributes to MOVA opcodes.
1208 2009-03-10 Alan Modra <amodra@bigpond.net.au>
1210 * ppc.h (ppc_parse_cpu): Declare.
1212 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
1214 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1215 and _IMM11 for mbitclr and mbitset.
1216 * score-datadep.h: Update dependency information.
1218 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
1220 * ppc.h (PPC_OPCODE_POWER7): New.
1222 2009-02-06 Doug Evans <dje@google.com>
1224 * i386.h: Add comment regarding sse* insns and prefixes.
1226 2009-02-03 Sandip Matte <sandip@rmicorp.com>
1228 * mips.h (INSN_XLR): Define.
1229 (INSN_CHIP_MASK): Update.
1231 (OPCODE_IS_MEMBER): Update.
1232 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1234 2009-01-28 Doug Evans <dje@google.com>
1236 * opcode/i386.h: Add multiple inclusion protection.
1237 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1238 (EDI_REG_NUM): New macros.
1239 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1240 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1241 (REX_PREFIX_P): New macro.
1243 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
1245 * ppc.h (struct powerpc_opcode): New field "deprecated".
1246 (PPC_OPCODE_NOPOWER4): Delete.
1248 2008-11-28 Joshua Kinard <kumba@gentoo.org>
1250 * mips.h: Define CPU_R14000, CPU_R16000.
1251 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
1253 2008-11-18 Catherine Moore <clm@codesourcery.com>
1255 * arm.h (FPU_NEON_FP16): New.
1256 (FPU_ARCH_NEON_FP16): New.
1258 2008-11-06 Chao-ying Fu <fu@mips.com>
1260 * mips.h: Doucument '1' for 5-bit sync type.
1262 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1264 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1267 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1269 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1271 2008-07-30 Michael J. Eager <eager@eagercon.com>
1273 * ppc.h (PPC_OPCODE_405): Define.
1274 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1276 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1278 * ppc.h (ppc_cpu_t): New typedef.
1279 (struct powerpc_opcode <flags>): Use it.
1280 (struct powerpc_operand <insert, extract>): Likewise.
1281 (struct powerpc_macro <flags>): Likewise.
1283 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1285 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1286 Update comment before MIPS16 field descriptors to mention MIPS16.
1287 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1289 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1290 New bit masks and shift counts for cins and exts.
1292 * mips.h: Document new field descriptors +Q.
1293 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1295 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1297 * mips.h (INSN_MACRO): Move it up to the pinfo macros.
1298 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1300 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
1302 * ppc.h: (PPC_OPCODE_E500MC): New.
1304 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1306 * i386.h (MAX_OPERANDS): Set to 5.
1307 (MAX_MNEM_SIZE): Changed to 20.
1309 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1311 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1313 2008-03-09 Paul Brook <paul@codesourcery.com>
1315 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1317 2008-03-04 Paul Brook <paul@codesourcery.com>
1319 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1320 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1321 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1323 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
1324 Nick Clifton <nickc@redhat.com>
1327 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1328 with a 32-bit displacement but without the top bit of the 4th byte
1331 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1333 * cr16.h (cr16_num_optab): Declared.
1335 2008-02-14 Hakan Ardo <hakan@debian.org>
1338 * avr.h (AVR_ISA_2xxe): Define.
1340 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1342 * mips.h: Update copyright.
1343 (INSN_CHIP_MASK): New macro.
1344 (INSN_OCTEON): New macro.
1345 (CPU_OCTEON): New macro.
1346 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1348 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1350 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1352 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1354 * avr.h (AVR_ISA_USB162): Add new opcode set.
1355 (AVR_ISA_AVR3): Likewise.
1357 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1359 * mips.h (INSN_LOONGSON_2E): New.
1360 (INSN_LOONGSON_2F): New.
1361 (CPU_LOONGSON_2E): New.
1362 (CPU_LOONGSON_2F): New.
1363 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1365 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1367 * mips.h (INSN_ISA*): Redefine certain values as an
1368 enumeration. Update comments.
1369 (mips_isa_table): New.
1370 (ISA_MIPS*): Redefine to match enumeration.
1371 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1374 2007-08-08 Ben Elliston <bje@au.ibm.com>
1376 * ppc.h (PPC_OPCODE_PPCPS): New.
1378 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1380 * m68k.h: Document j K & E.
1382 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1384 * cr16.h: New file for CR16 target.
1386 2007-05-02 Alan Modra <amodra@bigpond.net.au>
1388 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1390 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1392 * m68k.h (mcfisa_c): New.
1393 (mcfusp, mcf_mask): Adjust.
1395 2007-04-20 Alan Modra <amodra@bigpond.net.au>
1397 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1398 (num_powerpc_operands): Declare.
1399 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1400 (PPC_OPERAND_PLUS1): Define.
1402 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
1404 * i386.h (REX_MODE64): Renamed to ...
1406 (REX_EXTX): Renamed to ...
1408 (REX_EXTY): Renamed to ...
1410 (REX_EXTZ): Renamed to ...
1413 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1415 * i386.h: Add entries from config/tc-i386.h and move tables
1416 to opcodes/i386-opc.h.
1418 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1420 * i386.h (FloatDR): Removed.
1421 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1423 2007-03-01 Alan Modra <amodra@bigpond.net.au>
1425 * spu-insns.h: Add soma double-float insns.
1427 2007-02-20 Thiemo Seufer <ths@mips.com>
1428 Chao-Ying Fu <fu@mips.com>
1430 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1431 (INSN_DSPR2): Add flag for DSP R2 instructions.
1432 (M_BALIGN): New macro.
1434 2007-02-14 Alan Modra <amodra@bigpond.net.au>
1436 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1437 and Seg3ShortFrom with Shortform.
1439 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1442 * i386.h (i386_optab): Put the real "test" before the pseudo
1445 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
1447 * m68k.h (m68010up): OR fido_a.
1449 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
1451 * m68k.h (fido_a): New.
1453 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
1455 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1456 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1459 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1461 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1463 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1465 * score-inst.h (enum score_insn_type): Add Insn_internal.
1467 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1468 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1469 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1470 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1471 Alan Modra <amodra@bigpond.net.au>
1473 * spu-insns.h: New file.
1476 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1478 * ppc.h (PPC_OPCODE_CELL): Define.
1480 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1482 * i386.h : Modify opcode to support for the change in POPCNT opcode
1483 in amdfam10 architecture.
1485 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1487 * i386.h: Replace CpuMNI with CpuSSSE3.
1489 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
1490 Joseph Myers <joseph@codesourcery.com>
1491 Ian Lance Taylor <ian@wasabisystems.com>
1492 Ben Elliston <bje@wasabisystems.com>
1494 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1496 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1498 * score-datadep.h: New file.
1499 * score-inst.h: New file.
1501 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1503 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1504 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1505 movdq2q and movq2dq.
1507 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1508 Michael Meissner <michael.meissner@amd.com>
1510 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1512 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1514 * i386.h (i386_optab): Add "nop" with memory reference.
1516 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1518 * i386.h (i386_optab): Update comment for 64bit NOP.
1520 2006-06-06 Ben Elliston <bje@au.ibm.com>
1521 Anton Blanchard <anton@samba.org>
1523 * ppc.h (PPC_OPCODE_POWER6): Define.
1526 2006-06-05 Thiemo Seufer <ths@mips.com>
1528 * mips.h: Improve description of MT flags.
1530 2006-05-25 Richard Sandiford <richard@codesourcery.com>
1532 * m68k.h (mcf_mask): Define.
1534 2006-05-05 Thiemo Seufer <ths@mips.com>
1535 David Ung <davidu@mips.com>
1537 * mips.h (enum): Add macro M_CACHE_AB.
1539 2006-05-04 Thiemo Seufer <ths@mips.com>
1540 Nigel Stephens <nigel@mips.com>
1541 David Ung <davidu@mips.com>
1543 * mips.h: Add INSN_SMARTMIPS define.
1545 2006-04-30 Thiemo Seufer <ths@mips.com>
1546 David Ung <davidu@mips.com>
1548 * mips.h: Defines udi bits and masks. Add description of
1549 characters which may appear in the args field of udi
1552 2006-04-26 Thiemo Seufer <ths@networkno.de>
1554 * mips.h: Improve comments describing the bitfield instruction
1557 2006-04-26 Julian Brown <julian@codesourcery.com>
1559 * arm.h (FPU_VFP_EXT_V3): Define constant.
1560 (FPU_NEON_EXT_V1): Likewise.
1561 (FPU_VFP_HARD): Update.
1562 (FPU_VFP_V3): Define macro.
1563 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1565 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
1567 * avr.h (AVR_ISA_PWMx): New.
1569 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1571 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1572 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1573 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1574 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1575 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1577 2006-03-10 Paul Brook <paul@codesourcery.com>
1579 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1581 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1583 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1584 first. Correct mask of bb "B" opcode.
1586 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1588 * i386.h (i386_optab): Support Intel Merom New Instructions.
1590 2006-02-24 Paul Brook <paul@codesourcery.com>
1592 * arm.h: Add V7 feature bits.
1594 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1596 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1598 2006-01-31 Paul Brook <paul@codesourcery.com>
1599 Richard Earnshaw <rearnsha@arm.com>
1601 * arm.h: Use ARM_CPU_FEATURE.
1602 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1603 (arm_feature_set): Change to a structure.
1604 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1605 ARM_FEATURE): New macros.
1607 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
1609 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1610 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1611 (ADD_PC_INCR_OPCODE): Don't define.
1613 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1616 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1618 2005-11-14 David Ung <davidu@mips.com>
1620 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1621 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1622 save/restore encoding of the args field.
1624 2005-10-28 Dave Brolley <brolley@redhat.com>
1626 Contribute the following changes:
1627 2005-02-16 Dave Brolley <brolley@redhat.com>
1629 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1630 cgen_isa_mask_* to cgen_bitset_*.
1633 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1635 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1636 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1637 (CGEN_CPU_TABLE): Make isas a ponter.
1639 2003-09-29 Dave Brolley <brolley@redhat.com>
1641 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1642 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1643 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1645 2002-12-13 Dave Brolley <brolley@redhat.com>
1647 * cgen.h (symcat.h): #include it.
1648 (cgen-bitset.h): #include it.
1649 (CGEN_ATTR_VALUE_TYPE): Now a union.
1650 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1651 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1652 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1653 * cgen-bitset.h: New file.
1655 2005-09-30 Catherine Moore <clm@cm00re.com>
1659 2005-10-24 Jan Beulich <jbeulich@novell.com>
1661 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1664 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1666 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1667 Add FLAG_STRICT to pa10 ftest opcode.
1669 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1671 * hppa.h (pa_opcodes): Remove lha entries.
1673 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1675 * hppa.h (FLAG_STRICT): Revise comment.
1676 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1677 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1680 2005-09-30 Catherine Moore <clm@cm00re.com>
1684 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1686 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1688 2005-09-06 Chao-ying Fu <fu@mips.com>
1690 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1691 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1693 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1694 (INSN_ASE_MASK): Update to include INSN_MT.
1695 (INSN_MT): New define for MT ASE.
1697 2005-08-25 Chao-ying Fu <fu@mips.com>
1699 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1700 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1701 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1702 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1703 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1704 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1706 (INSN_DSP): New define for DSP ASE.
1708 2005-08-18 Alan Modra <amodra@bigpond.net.au>
1712 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1714 * ppc.h (PPC_OPCODE_E300): Define.
1716 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1718 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1720 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1723 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1726 2005-07-27 Jan Beulich <jbeulich@novell.com>
1728 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1729 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1730 Add movq-s as 64-bit variants of movd-s.
1732 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1734 * hppa.h: Fix punctuation in comment.
1736 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1737 implicit space-register addressing. Set space-register bits on opcodes
1738 using implicit space-register addressing. Add various missing pa20
1739 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1740 space-register addressing. Use "fE" instead of "fe" in various
1743 2005-07-18 Jan Beulich <jbeulich@novell.com>
1745 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1747 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1749 * i386.h (i386_optab): Support Intel VMX Instructions.
1751 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1753 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1755 2005-07-05 Jan Beulich <jbeulich@novell.com>
1757 * i386.h (i386_optab): Add new insns.
1759 2005-07-01 Nick Clifton <nickc@redhat.com>
1761 * sparc.h: Add typedefs to structure declarations.
1763 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1766 * i386.h (i386_optab): Update comments for 64bit addressing on
1767 mov. Allow 64bit addressing for mov and movq.
1769 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1771 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1772 respectively, in various floating-point load and store patterns.
1774 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1776 * hppa.h (FLAG_STRICT): Correct comment.
1777 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1778 PA 2.0 mneumonics when equivalent. Entries with cache control
1779 completers now require PA 1.1. Adjust whitespace.
1781 2005-05-19 Anton Blanchard <anton@samba.org>
1783 * ppc.h (PPC_OPCODE_POWER5): Define.
1785 2005-05-10 Nick Clifton <nickc@redhat.com>
1787 * Update the address and phone number of the FSF organization in
1788 the GPL notices in the following files:
1789 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1790 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1791 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1792 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1793 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1794 tic54x.h, tic80.h, v850.h, vax.h
1796 2005-05-09 Jan Beulich <jbeulich@novell.com>
1798 * i386.h (i386_optab): Add ht and hnt.
1800 2005-04-18 Mark Kettenis <kettenis@gnu.org>
1802 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1803 Add xcrypt-ctr. Provide aliases without hyphens.
1805 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1807 Moved from ../ChangeLog
1809 2005-04-12 Paul Brook <paul@codesourcery.com>
1810 * m88k.h: Rename psr macros to avoid conflicts.
1812 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1813 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1814 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1815 and ARM_ARCH_V6ZKT2.
1817 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1818 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1819 Remove redundant instruction types.
1820 (struct argument): X_op - new field.
1821 (struct cst4_entry): Remove.
1822 (no_op_insn): Declare.
1824 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1825 * crx.h (enum argtype): Rename types, remove unused types.
1827 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1828 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1829 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1830 (enum operand_type): Rearrange operands, edit comments.
1831 replace us<N> with ui<N> for unsigned immediate.
1832 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1833 displacements (respectively).
1834 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1835 (instruction type): Add NO_TYPE_INS.
1836 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1837 (operand_entry): New field - 'flags'.
1838 (operand flags): New.
1840 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1841 * crx.h (operand_type): Remove redundant types i3, i4,
1843 Add new unsigned immediate types us3, us4, us5, us16.
1845 2005-04-12 Mark Kettenis <kettenis@gnu.org>
1847 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1848 adjust them accordingly.
1850 2005-04-01 Jan Beulich <jbeulich@novell.com>
1852 * i386.h (i386_optab): Add rdtscp.
1854 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1856 * i386.h (i386_optab): Don't allow the `l' suffix for moving
1857 between memory and segment register. Allow movq for moving between
1858 general-purpose register and segment register.
1860 2005-02-09 Jan Beulich <jbeulich@novell.com>
1863 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1864 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1867 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1869 * m68k.h (m68008, m68ec030, m68882): Remove.
1871 (cpu_m68k, cpu_cf): New.
1872 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1873 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1875 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
1877 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1878 * cgen.h (enum cgen_parse_operand_type): Add
1879 CGEN_PARSE_OPERAND_SYMBOLIC.
1881 2005-01-21 Fred Fish <fnf@specifixinc.com>
1883 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1884 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1885 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1887 2005-01-19 Fred Fish <fnf@specifixinc.com>
1889 * mips.h (struct mips_opcode): Add new pinfo2 member.
1890 (INSN_ALIAS): New define for opcode table entries that are
1891 specific instances of another entry, such as 'move' for an 'or'
1892 with a zero operand.
1893 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1894 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1896 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1898 * mips.h (CPU_RM9000): Define.
1899 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1901 2004-11-25 Jan Beulich <jbeulich@novell.com>
1903 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1904 to/from test registers are illegal in 64-bit mode. Add missing
1905 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1906 (previously one had to explicitly encode a rex64 prefix). Re-enable
1907 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1908 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1910 2004-11-23 Jan Beulich <jbeulich@novell.com>
1912 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1913 available only with SSE2. Change the MMX additions introduced by SSE
1914 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1915 instructions by their now designated identifier (since combining i686
1916 and 3DNow! does not really imply 3DNow!A).
1918 2004-11-19 Alan Modra <amodra@bigpond.net.au>
1920 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1921 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1923 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1924 Vineet Sharma <vineets@noida.hcltech.com>
1926 * maxq.h: New file: Disassembly information for the maxq port.
1928 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1930 * i386.h (i386_optab): Put back "movzb".
1932 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
1934 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1935 comments. Remove member cris_ver_sim. Add members
1936 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1937 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1938 (struct cris_support_reg, struct cris_cond15): New types.
1939 (cris_conds15): Declare.
1940 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1941 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1942 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1943 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1944 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1945 SIZE_FIELD_UNSIGNED.
1947 2004-11-04 Jan Beulich <jbeulich@novell.com>
1949 * i386.h (sldx_Suf): Remove.
1950 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1951 (q_FP): Define, implying no REX64.
1952 (x_FP, sl_FP): Imply FloatMF.
1953 (i386_optab): Split reg and mem forms of moving from segment registers
1954 so that the memory forms can ignore the 16-/32-bit operand size
1955 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1956 all non-floating-point instructions. Unite 32- and 64-bit forms of
1957 movsx, movzx, and movd. Adjust floating point operations for the above
1958 changes to the *FP macros. Add DefaultSize to floating point control
1959 insns operating on larger memory ranges. Remove left over comments
1960 hinting at certain insns being Intel-syntax ones where the ones
1961 actually meant are already gone.
1963 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1965 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1968 2004-09-30 Paul Brook <paul@codesourcery.com>
1970 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1971 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1973 2004-09-11 Theodore A. Roth <troth@openavr.org>
1975 * avr.h: Add support for
1976 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1978 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1980 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1982 2004-08-24 Dmitry Diky <diwil@spec.ru>
1984 * msp430.h (msp430_opc): Add new instructions.
1985 (msp430_rcodes): Declare new instructions.
1986 (msp430_hcodes): Likewise..
1988 2004-08-13 Nick Clifton <nickc@redhat.com>
1991 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1994 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1996 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1998 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
2000 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
2002 2004-07-21 Jan Beulich <jbeulich@novell.com>
2004 * i386.h: Adjust instruction descriptions to better match the
2007 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
2009 * arm.h: Remove all old content. Replace with architecture defines
2010 from gas/config/tc-arm.c.
2012 2004-07-09 Andreas Schwab <schwab@suse.de>
2014 * m68k.h: Fix comment.
2016 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
2020 2004-06-24 Alan Modra <amodra@bigpond.net.au>
2022 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
2024 2004-05-24 Peter Barada <peter@the-baradas.com>
2026 * m68k.h: Add 'size' to m68k_opcode.
2028 2004-05-05 Peter Barada <peter@the-baradas.com>
2030 * m68k.h: Switch from ColdFire chip name to core variant.
2032 2004-04-22 Peter Barada <peter@the-baradas.com>
2034 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
2035 descriptions for new EMAC cases.
2036 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
2037 handle Motorola MAC syntax.
2038 Allow disassembly of ColdFire V4e object files.
2040 2004-03-16 Alan Modra <amodra@bigpond.net.au>
2042 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
2044 2004-03-12 Jakub Jelinek <jakub@redhat.com>
2046 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
2048 2004-03-12 Michal Ludvig <mludvig@suse.cz>
2050 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
2052 2004-03-12 Michal Ludvig <mludvig@suse.cz>
2054 * i386.h (i386_optab): Added xstore/xcrypt insns.
2056 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
2058 * h8300.h (32bit ldc/stc): Add relaxing support.
2060 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
2062 * h8300.h (BITOP): Pass MEMRELAX flag.
2064 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
2066 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
2069 For older changes see ChangeLog-9103
2071 Copyright (C) 2004-2014 Free Software Foundation, Inc.
2073 Copying and distribution of this file, with or without modification,
2074 are permitted in any medium without royalty provided the copyright
2075 notice and this notice are preserved.
2081 version-control: never