1 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
3 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
4 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
5 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
7 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
9 * mips.h: Fix previous commit.
11 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
13 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
14 (INSN_LOONGSON_3A): Clear bit 31.
16 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
19 * arm.h (ARM_AEXT_V6M_ONLY): New define.
20 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
21 (ARM_ARCH_V6M_ONLY): New define.
23 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
25 * mips.h (INSN_LOONGSON_3A): Defined.
26 (CPU_LOONGSON_3A): Defined.
27 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
29 2010-10-09 Matt Rice <ratmice@gmail.com>
31 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
32 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
34 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
36 * arm.h (ARM_EXT_VIRT): New define.
37 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
38 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
41 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
43 * arm.h (ARM_AEXT_ADIV): New define.
44 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
46 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
48 * arm.h (ARM_EXT_OS): New define.
49 (ARM_AEXT_V6SM): Likewise.
50 (ARM_ARCH_V6SM): Likewise.
52 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
54 * arm.h (ARM_EXT_MP): Add.
55 (ARM_ARCH_V7A_MP): Likewise.
57 2010-09-22 Mike Frysinger <vapier@gentoo.org>
59 * bfin.h: Declare pseudoChr structs/defines.
61 2010-09-21 Mike Frysinger <vapier@gentoo.org>
63 * bfin.h: Strip trailing whitespace.
65 2010-07-29 DJ Delorie <dj@redhat.com>
67 * rx.h (RX_Operand_Type): Add TwoReg.
68 (RX_Opcode_ID): Remove ediv and ediv2.
70 2010-07-27 DJ Delorie <dj@redhat.com>
72 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
74 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
75 Ina Pandit <ina.pandit@kpitcummins.com>
77 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
78 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
80 Remove PROCESSOR_V850EA support.
81 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
82 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
83 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
84 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
85 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
87 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
89 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
92 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
94 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
95 (MIPS16_INSN_BRANCH): Rename to...
96 (MIPS16_INSN_COND_BRANCH): ... this.
98 2010-07-03 Alan Modra <amodra@gmail.com>
100 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
101 Renumber other PPC_OPCODE defines.
103 2010-07-03 Alan Modra <amodra@gmail.com>
105 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
107 2010-06-29 Alan Modra <amodra@gmail.com>
109 * maxq.h: Delete file.
111 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
113 * ppc.h (PPC_OPCODE_E500): Define.
115 2010-05-26 Catherine Moore <clm@codesourcery.com>
117 * opcode/mips.h (INSN_MIPS16): Remove.
119 2010-04-21 Joseph Myers <joseph@codesourcery.com>
121 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
123 2010-04-15 Nick Clifton <nickc@redhat.com>
125 * alpha.h: Update copyright notice to use GPLv3.
131 * convex.h: Likewise.
145 * m68hc11.h: Likewise.
151 * mn10200.h: Likewise.
152 * mn10300.h: Likewise.
153 * msp430.h: Likewise.
164 * score-datadep.h: Likewise.
165 * score-inst.h: Likewise.
167 * spu-insns.h: Likewise.
171 * tic54x.h: Likewise.
176 2010-03-25 Joseph Myers <joseph@codesourcery.com>
178 * tic6x-control-registers.h, tic6x-insn-formats.h,
179 tic6x-opcode-table.h, tic6x.h: New.
181 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
183 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
185 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
187 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
189 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
191 * ia64.h (ia64_find_opcode): Remove argument name.
192 (ia64_find_next_opcode): Likewise.
193 (ia64_dis_opcode): Likewise.
194 (ia64_free_opcode): Likewise.
195 (ia64_find_dependency): Likewise.
197 2009-11-22 Doug Evans <dje@sebabeach.org>
199 * cgen.h: Include bfd_stdint.h.
200 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
202 2009-11-18 Paul Brook <paul@codesourcery.com>
204 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
206 2009-11-17 Paul Brook <paul@codesourcery.com>
207 Daniel Jacobowitz <dan@codesourcery.com>
209 * arm.h (ARM_EXT_V6_DSP): Define.
210 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
211 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
213 2009-11-04 DJ Delorie <dj@redhat.com>
215 * rx.h (rx_decode_opcode) (mvtipl): Add.
216 (mvtcp, mvfcp, opecp): Remove.
218 2009-11-02 Paul Brook <paul@codesourcery.com>
220 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
221 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
222 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
223 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
224 FPU_ARCH_NEON_VFP_V4): Define.
226 2009-10-23 Doug Evans <dje@sebabeach.org>
228 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
229 * cgen.h: Update. Improve multi-inclusion macro name.
231 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
233 * ppc.h (PPC_OPCODE_476): Define.
235 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
237 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
239 2009-09-29 DJ Delorie <dj@redhat.com>
243 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
245 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
247 2009-09-21 Ben Elliston <bje@au.ibm.com>
249 * ppc.h (PPC_OPCODE_PPCA2): New.
251 2009-09-05 Martin Thuresson <martin@mtme.org>
253 * ia64.h (struct ia64_operand): Renamed member class to op_class.
255 2009-08-29 Martin Thuresson <martin@mtme.org>
257 * tic30.h (template): Rename type template to
258 insn_template. Updated code to use new name.
259 * tic54x.h (template): Rename type template to
262 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
264 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
266 2009-06-11 Anthony Green <green@moxielogic.com>
268 * moxie.h (MOXIE_F3_PCREL): Define.
269 (moxie_form3_opc_info): Grow.
271 2009-06-06 Anthony Green <green@moxielogic.com>
273 * moxie.h (MOXIE_F1_M): Define.
275 2009-04-15 Anthony Green <green@moxielogic.com>
279 2009-04-06 DJ Delorie <dj@redhat.com>
281 * h8300.h: Add relaxation attributes to MOVA opcodes.
283 2009-03-10 Alan Modra <amodra@bigpond.net.au>
285 * ppc.h (ppc_parse_cpu): Declare.
287 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
289 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
290 and _IMM11 for mbitclr and mbitset.
291 * score-datadep.h: Update dependency information.
293 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
295 * ppc.h (PPC_OPCODE_POWER7): New.
297 2009-02-06 Doug Evans <dje@google.com>
299 * i386.h: Add comment regarding sse* insns and prefixes.
301 2009-02-03 Sandip Matte <sandip@rmicorp.com>
303 * mips.h (INSN_XLR): Define.
304 (INSN_CHIP_MASK): Update.
306 (OPCODE_IS_MEMBER): Update.
307 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
309 2009-01-28 Doug Evans <dje@google.com>
311 * opcode/i386.h: Add multiple inclusion protection.
312 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
313 (EDI_REG_NUM): New macros.
314 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
315 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
316 (REX_PREFIX_P): New macro.
318 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
320 * ppc.h (struct powerpc_opcode): New field "deprecated".
321 (PPC_OPCODE_NOPOWER4): Delete.
323 2008-11-28 Joshua Kinard <kumba@gentoo.org>
325 * mips.h: Define CPU_R14000, CPU_R16000.
326 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
328 2008-11-18 Catherine Moore <clm@codesourcery.com>
330 * arm.h (FPU_NEON_FP16): New.
331 (FPU_ARCH_NEON_FP16): New.
333 2008-11-06 Chao-ying Fu <fu@mips.com>
335 * mips.h: Doucument '1' for 5-bit sync type.
337 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
339 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
342 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
344 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
346 2008-07-30 Michael J. Eager <eager@eagercon.com>
348 * ppc.h (PPC_OPCODE_405): Define.
349 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
351 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
353 * ppc.h (ppc_cpu_t): New typedef.
354 (struct powerpc_opcode <flags>): Use it.
355 (struct powerpc_operand <insert, extract>): Likewise.
356 (struct powerpc_macro <flags>): Likewise.
358 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
360 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
361 Update comment before MIPS16 field descriptors to mention MIPS16.
362 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
364 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
365 New bit masks and shift counts for cins and exts.
367 * mips.h: Document new field descriptors +Q.
368 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
370 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
372 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
373 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
375 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
377 * ppc.h: (PPC_OPCODE_E500MC): New.
379 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
381 * i386.h (MAX_OPERANDS): Set to 5.
382 (MAX_MNEM_SIZE): Changed to 20.
384 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
386 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
388 2008-03-09 Paul Brook <paul@codesourcery.com>
390 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
392 2008-03-04 Paul Brook <paul@codesourcery.com>
394 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
395 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
396 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
398 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
399 Nick Clifton <nickc@redhat.com>
402 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
403 with a 32-bit displacement but without the top bit of the 4th byte
406 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
408 * cr16.h (cr16_num_optab): Declared.
410 2008-02-14 Hakan Ardo <hakan@debian.org>
413 * avr.h (AVR_ISA_2xxe): Define.
415 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
417 * mips.h: Update copyright.
418 (INSN_CHIP_MASK): New macro.
419 (INSN_OCTEON): New macro.
420 (CPU_OCTEON): New macro.
421 (OPCODE_IS_MEMBER): Handle Octeon instructions.
423 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
425 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
427 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
429 * avr.h (AVR_ISA_USB162): Add new opcode set.
430 (AVR_ISA_AVR3): Likewise.
432 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
434 * mips.h (INSN_LOONGSON_2E): New.
435 (INSN_LOONGSON_2F): New.
436 (CPU_LOONGSON_2E): New.
437 (CPU_LOONGSON_2F): New.
438 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
440 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
442 * mips.h (INSN_ISA*): Redefine certain values as an
443 enumeration. Update comments.
444 (mips_isa_table): New.
445 (ISA_MIPS*): Redefine to match enumeration.
446 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
449 2007-08-08 Ben Elliston <bje@au.ibm.com>
451 * ppc.h (PPC_OPCODE_PPCPS): New.
453 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
455 * m68k.h: Document j K & E.
457 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
459 * cr16.h: New file for CR16 target.
461 2007-05-02 Alan Modra <amodra@bigpond.net.au>
463 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
465 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
467 * m68k.h (mcfisa_c): New.
468 (mcfusp, mcf_mask): Adjust.
470 2007-04-20 Alan Modra <amodra@bigpond.net.au>
472 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
473 (num_powerpc_operands): Declare.
474 (PPC_OPERAND_SIGNED et al): Redefine as hex.
475 (PPC_OPERAND_PLUS1): Define.
477 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
479 * i386.h (REX_MODE64): Renamed to ...
481 (REX_EXTX): Renamed to ...
483 (REX_EXTY): Renamed to ...
485 (REX_EXTZ): Renamed to ...
488 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
490 * i386.h: Add entries from config/tc-i386.h and move tables
491 to opcodes/i386-opc.h.
493 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
495 * i386.h (FloatDR): Removed.
496 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
498 2007-03-01 Alan Modra <amodra@bigpond.net.au>
500 * spu-insns.h: Add soma double-float insns.
502 2007-02-20 Thiemo Seufer <ths@mips.com>
503 Chao-Ying Fu <fu@mips.com>
505 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
506 (INSN_DSPR2): Add flag for DSP R2 instructions.
507 (M_BALIGN): New macro.
509 2007-02-14 Alan Modra <amodra@bigpond.net.au>
511 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
512 and Seg3ShortFrom with Shortform.
514 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
517 * i386.h (i386_optab): Put the real "test" before the pseudo
520 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
522 * m68k.h (m68010up): OR fido_a.
524 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
526 * m68k.h (fido_a): New.
528 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
530 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
531 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
534 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
536 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
538 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
540 * score-inst.h (enum score_insn_type): Add Insn_internal.
542 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
543 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
544 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
545 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
546 Alan Modra <amodra@bigpond.net.au>
548 * spu-insns.h: New file.
551 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
553 * ppc.h (PPC_OPCODE_CELL): Define.
555 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
557 * i386.h : Modify opcode to support for the change in POPCNT opcode
558 in amdfam10 architecture.
560 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
562 * i386.h: Replace CpuMNI with CpuSSSE3.
564 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
565 Joseph Myers <joseph@codesourcery.com>
566 Ian Lance Taylor <ian@wasabisystems.com>
567 Ben Elliston <bje@wasabisystems.com>
569 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
571 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
573 * score-datadep.h: New file.
574 * score-inst.h: New file.
576 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
578 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
579 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
582 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
583 Michael Meissner <michael.meissner@amd.com>
585 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
587 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
589 * i386.h (i386_optab): Add "nop" with memory reference.
591 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
593 * i386.h (i386_optab): Update comment for 64bit NOP.
595 2006-06-06 Ben Elliston <bje@au.ibm.com>
596 Anton Blanchard <anton@samba.org>
598 * ppc.h (PPC_OPCODE_POWER6): Define.
601 2006-06-05 Thiemo Seufer <ths@mips.com>
603 * mips.h: Improve description of MT flags.
605 2006-05-25 Richard Sandiford <richard@codesourcery.com>
607 * m68k.h (mcf_mask): Define.
609 2006-05-05 Thiemo Seufer <ths@mips.com>
610 David Ung <davidu@mips.com>
612 * mips.h (enum): Add macro M_CACHE_AB.
614 2006-05-04 Thiemo Seufer <ths@mips.com>
615 Nigel Stephens <nigel@mips.com>
616 David Ung <davidu@mips.com>
618 * mips.h: Add INSN_SMARTMIPS define.
620 2006-04-30 Thiemo Seufer <ths@mips.com>
621 David Ung <davidu@mips.com>
623 * mips.h: Defines udi bits and masks. Add description of
624 characters which may appear in the args field of udi
627 2006-04-26 Thiemo Seufer <ths@networkno.de>
629 * mips.h: Improve comments describing the bitfield instruction
632 2006-04-26 Julian Brown <julian@codesourcery.com>
634 * arm.h (FPU_VFP_EXT_V3): Define constant.
635 (FPU_NEON_EXT_V1): Likewise.
636 (FPU_VFP_HARD): Update.
637 (FPU_VFP_V3): Define macro.
638 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
640 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
642 * avr.h (AVR_ISA_PWMx): New.
644 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
646 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
647 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
648 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
649 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
650 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
652 2006-03-10 Paul Brook <paul@codesourcery.com>
654 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
656 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
658 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
659 first. Correct mask of bb "B" opcode.
661 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
663 * i386.h (i386_optab): Support Intel Merom New Instructions.
665 2006-02-24 Paul Brook <paul@codesourcery.com>
667 * arm.h: Add V7 feature bits.
669 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
671 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
673 2006-01-31 Paul Brook <paul@codesourcery.com>
674 Richard Earnshaw <rearnsha@arm.com>
676 * arm.h: Use ARM_CPU_FEATURE.
677 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
678 (arm_feature_set): Change to a structure.
679 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
680 ARM_FEATURE): New macros.
682 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
684 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
685 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
686 (ADD_PC_INCR_OPCODE): Don't define.
688 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
691 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
693 2005-11-14 David Ung <davidu@mips.com>
695 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
696 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
697 save/restore encoding of the args field.
699 2005-10-28 Dave Brolley <brolley@redhat.com>
701 Contribute the following changes:
702 2005-02-16 Dave Brolley <brolley@redhat.com>
704 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
705 cgen_isa_mask_* to cgen_bitset_*.
708 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
710 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
711 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
712 (CGEN_CPU_TABLE): Make isas a ponter.
714 2003-09-29 Dave Brolley <brolley@redhat.com>
716 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
717 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
718 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
720 2002-12-13 Dave Brolley <brolley@redhat.com>
722 * cgen.h (symcat.h): #include it.
723 (cgen-bitset.h): #include it.
724 (CGEN_ATTR_VALUE_TYPE): Now a union.
725 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
726 (CGEN_ATTR_ENTRY): 'value' now unsigned.
727 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
728 * cgen-bitset.h: New file.
730 2005-09-30 Catherine Moore <clm@cm00re.com>
734 2005-10-24 Jan Beulich <jbeulich@novell.com>
736 * ia64.h (enum ia64_opnd): Move memory operand out of set of
739 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
741 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
742 Add FLAG_STRICT to pa10 ftest opcode.
744 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
746 * hppa.h (pa_opcodes): Remove lha entries.
748 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
750 * hppa.h (FLAG_STRICT): Revise comment.
751 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
752 before corresponding pa11 opcodes. Add strict pa10 register-immediate
755 2005-09-30 Catherine Moore <clm@cm00re.com>
759 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
761 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
763 2005-09-06 Chao-ying Fu <fu@mips.com>
765 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
766 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
768 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
769 (INSN_ASE_MASK): Update to include INSN_MT.
770 (INSN_MT): New define for MT ASE.
772 2005-08-25 Chao-ying Fu <fu@mips.com>
774 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
775 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
776 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
777 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
778 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
779 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
781 (INSN_DSP): New define for DSP ASE.
783 2005-08-18 Alan Modra <amodra@bigpond.net.au>
787 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
789 * ppc.h (PPC_OPCODE_E300): Define.
791 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
793 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
795 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
798 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
801 2005-07-27 Jan Beulich <jbeulich@novell.com>
803 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
804 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
805 Add movq-s as 64-bit variants of movd-s.
807 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
809 * hppa.h: Fix punctuation in comment.
811 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
812 implicit space-register addressing. Set space-register bits on opcodes
813 using implicit space-register addressing. Add various missing pa20
814 long-immediate opcodes. Remove various opcodes using implicit 3-bit
815 space-register addressing. Use "fE" instead of "fe" in various
818 2005-07-18 Jan Beulich <jbeulich@novell.com>
820 * i386.h (i386_optab): Operands of aam and aad are unsigned.
822 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
824 * i386.h (i386_optab): Support Intel VMX Instructions.
826 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
828 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
830 2005-07-05 Jan Beulich <jbeulich@novell.com>
832 * i386.h (i386_optab): Add new insns.
834 2005-07-01 Nick Clifton <nickc@redhat.com>
836 * sparc.h: Add typedefs to structure declarations.
838 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
841 * i386.h (i386_optab): Update comments for 64bit addressing on
842 mov. Allow 64bit addressing for mov and movq.
844 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
846 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
847 respectively, in various floating-point load and store patterns.
849 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
851 * hppa.h (FLAG_STRICT): Correct comment.
852 (pa_opcodes): Update load and store entries to allow both PA 1.X and
853 PA 2.0 mneumonics when equivalent. Entries with cache control
854 completers now require PA 1.1. Adjust whitespace.
856 2005-05-19 Anton Blanchard <anton@samba.org>
858 * ppc.h (PPC_OPCODE_POWER5): Define.
860 2005-05-10 Nick Clifton <nickc@redhat.com>
862 * Update the address and phone number of the FSF organization in
863 the GPL notices in the following files:
864 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
865 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
866 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
867 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
868 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
869 tic54x.h, tic80.h, v850.h, vax.h
871 2005-05-09 Jan Beulich <jbeulich@novell.com>
873 * i386.h (i386_optab): Add ht and hnt.
875 2005-04-18 Mark Kettenis <kettenis@gnu.org>
877 * i386.h: Insert hyphens into selected VIA PadLock extensions.
878 Add xcrypt-ctr. Provide aliases without hyphens.
880 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
882 Moved from ../ChangeLog
884 2005-04-12 Paul Brook <paul@codesourcery.com>
885 * m88k.h: Rename psr macros to avoid conflicts.
887 2005-03-12 Zack Weinberg <zack@codesourcery.com>
888 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
889 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
892 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
893 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
894 Remove redundant instruction types.
895 (struct argument): X_op - new field.
896 (struct cst4_entry): Remove.
897 (no_op_insn): Declare.
899 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
900 * crx.h (enum argtype): Rename types, remove unused types.
902 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
903 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
904 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
905 (enum operand_type): Rearrange operands, edit comments.
906 replace us<N> with ui<N> for unsigned immediate.
907 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
908 displacements (respectively).
909 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
910 (instruction type): Add NO_TYPE_INS.
911 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
912 (operand_entry): New field - 'flags'.
913 (operand flags): New.
915 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
916 * crx.h (operand_type): Remove redundant types i3, i4,
918 Add new unsigned immediate types us3, us4, us5, us16.
920 2005-04-12 Mark Kettenis <kettenis@gnu.org>
922 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
923 adjust them accordingly.
925 2005-04-01 Jan Beulich <jbeulich@novell.com>
927 * i386.h (i386_optab): Add rdtscp.
929 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
931 * i386.h (i386_optab): Don't allow the `l' suffix for moving
932 between memory and segment register. Allow movq for moving between
933 general-purpose register and segment register.
935 2005-02-09 Jan Beulich <jbeulich@novell.com>
938 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
939 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
942 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
944 * m68k.h (m68008, m68ec030, m68882): Remove.
946 (cpu_m68k, cpu_cf): New.
947 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
948 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
950 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
952 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
953 * cgen.h (enum cgen_parse_operand_type): Add
954 CGEN_PARSE_OPERAND_SYMBOLIC.
956 2005-01-21 Fred Fish <fnf@specifixinc.com>
958 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
959 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
960 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
962 2005-01-19 Fred Fish <fnf@specifixinc.com>
964 * mips.h (struct mips_opcode): Add new pinfo2 member.
965 (INSN_ALIAS): New define for opcode table entries that are
966 specific instances of another entry, such as 'move' for an 'or'
968 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
969 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
971 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
973 * mips.h (CPU_RM9000): Define.
974 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
976 2004-11-25 Jan Beulich <jbeulich@novell.com>
978 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
979 to/from test registers are illegal in 64-bit mode. Add missing
980 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
981 (previously one had to explicitly encode a rex64 prefix). Re-enable
982 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
983 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
985 2004-11-23 Jan Beulich <jbeulich@novell.com>
987 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
988 available only with SSE2. Change the MMX additions introduced by SSE
989 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
990 instructions by their now designated identifier (since combining i686
991 and 3DNow! does not really imply 3DNow!A).
993 2004-11-19 Alan Modra <amodra@bigpond.net.au>
995 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
996 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
998 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
999 Vineet Sharma <vineets@noida.hcltech.com>
1001 * maxq.h: New file: Disassembly information for the maxq port.
1003 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1005 * i386.h (i386_optab): Put back "movzb".
1007 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
1009 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1010 comments. Remove member cris_ver_sim. Add members
1011 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1012 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1013 (struct cris_support_reg, struct cris_cond15): New types.
1014 (cris_conds15): Declare.
1015 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1016 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1017 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1018 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1019 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1020 SIZE_FIELD_UNSIGNED.
1022 2004-11-04 Jan Beulich <jbeulich@novell.com>
1024 * i386.h (sldx_Suf): Remove.
1025 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1026 (q_FP): Define, implying no REX64.
1027 (x_FP, sl_FP): Imply FloatMF.
1028 (i386_optab): Split reg and mem forms of moving from segment registers
1029 so that the memory forms can ignore the 16-/32-bit operand size
1030 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1031 all non-floating-point instructions. Unite 32- and 64-bit forms of
1032 movsx, movzx, and movd. Adjust floating point operations for the above
1033 changes to the *FP macros. Add DefaultSize to floating point control
1034 insns operating on larger memory ranges. Remove left over comments
1035 hinting at certain insns being Intel-syntax ones where the ones
1036 actually meant are already gone.
1038 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1040 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1043 2004-09-30 Paul Brook <paul@codesourcery.com>
1045 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1046 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1048 2004-09-11 Theodore A. Roth <troth@openavr.org>
1050 * avr.h: Add support for
1051 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1053 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1055 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1057 2004-08-24 Dmitry Diky <diwil@spec.ru>
1059 * msp430.h (msp430_opc): Add new instructions.
1060 (msp430_rcodes): Declare new instructions.
1061 (msp430_hcodes): Likewise..
1063 2004-08-13 Nick Clifton <nickc@redhat.com>
1066 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1069 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1071 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1073 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1075 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1077 2004-07-21 Jan Beulich <jbeulich@novell.com>
1079 * i386.h: Adjust instruction descriptions to better match the
1082 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
1084 * arm.h: Remove all old content. Replace with architecture defines
1085 from gas/config/tc-arm.c.
1087 2004-07-09 Andreas Schwab <schwab@suse.de>
1089 * m68k.h: Fix comment.
1091 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1095 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1097 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1099 2004-05-24 Peter Barada <peter@the-baradas.com>
1101 * m68k.h: Add 'size' to m68k_opcode.
1103 2004-05-05 Peter Barada <peter@the-baradas.com>
1105 * m68k.h: Switch from ColdFire chip name to core variant.
1107 2004-04-22 Peter Barada <peter@the-baradas.com>
1109 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1110 descriptions for new EMAC cases.
1111 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1112 handle Motorola MAC syntax.
1113 Allow disassembly of ColdFire V4e object files.
1115 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1117 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1119 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1121 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1123 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1125 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1127 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1129 * i386.h (i386_optab): Added xstore/xcrypt insns.
1131 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1133 * h8300.h (32bit ldc/stc): Add relaxing support.
1135 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1137 * h8300.h (BITOP): Pass MEMRELAX flag.
1139 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1141 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1144 For older changes see ChangeLog-9103
1150 version-control: never