1 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
3 * arm.h (ARM_EXT_VIRT): New define.
4 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
5 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
8 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
10 * arm.h (ARM_AEXT_ADIV): New define.
11 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
13 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
15 * arm.h (ARM_EXT_OS): New define.
16 (ARM_AEXT_V6SM): Likewise.
17 (ARM_ARCH_V6SM): Likewise.
19 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
21 * arm.h (ARM_EXT_MP): Add.
22 (ARM_ARCH_V7A_MP): Likewise.
24 2010-09-22 Mike Frysinger <vapier@gentoo.org>
26 * bfin.h: Declare pseudoChr structs/defines.
28 2010-09-21 Mike Frysinger <vapier@gentoo.org>
30 * bfin.h: Strip trailing whitespace.
32 2010-07-29 DJ Delorie <dj@redhat.com>
34 * rx.h (RX_Operand_Type): Add TwoReg.
35 (RX_Opcode_ID): Remove ediv and ediv2.
37 2010-07-27 DJ Delorie <dj@redhat.com>
39 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
41 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
42 Ina Pandit <ina.pandit@kpitcummins.com>
44 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
45 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
47 Remove PROCESSOR_V850EA support.
48 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
49 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
50 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
51 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
52 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
54 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
56 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
59 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
61 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
62 (MIPS16_INSN_BRANCH): Rename to...
63 (MIPS16_INSN_COND_BRANCH): ... this.
65 2010-07-03 Alan Modra <amodra@gmail.com>
67 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
68 Renumber other PPC_OPCODE defines.
70 2010-07-03 Alan Modra <amodra@gmail.com>
72 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
74 2010-06-29 Alan Modra <amodra@gmail.com>
76 * maxq.h: Delete file.
78 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
80 * ppc.h (PPC_OPCODE_E500): Define.
82 2010-05-26 Catherine Moore <clm@codesourcery.com>
84 * opcode/mips.h (INSN_MIPS16): Remove.
86 2010-04-21 Joseph Myers <joseph@codesourcery.com>
88 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
90 2010-04-15 Nick Clifton <nickc@redhat.com>
92 * alpha.h: Update copyright notice to use GPLv3.
112 * m68hc11.h: Likewise.
118 * mn10200.h: Likewise.
119 * mn10300.h: Likewise.
120 * msp430.h: Likewise.
131 * score-datadep.h: Likewise.
132 * score-inst.h: Likewise.
134 * spu-insns.h: Likewise.
138 * tic54x.h: Likewise.
143 2010-03-25 Joseph Myers <joseph@codesourcery.com>
145 * tic6x-control-registers.h, tic6x-insn-formats.h,
146 tic6x-opcode-table.h, tic6x.h: New.
148 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
150 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
152 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
154 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
156 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
158 * ia64.h (ia64_find_opcode): Remove argument name.
159 (ia64_find_next_opcode): Likewise.
160 (ia64_dis_opcode): Likewise.
161 (ia64_free_opcode): Likewise.
162 (ia64_find_dependency): Likewise.
164 2009-11-22 Doug Evans <dje@sebabeach.org>
166 * cgen.h: Include bfd_stdint.h.
167 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
169 2009-11-18 Paul Brook <paul@codesourcery.com>
171 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
173 2009-11-17 Paul Brook <paul@codesourcery.com>
174 Daniel Jacobowitz <dan@codesourcery.com>
176 * arm.h (ARM_EXT_V6_DSP): Define.
177 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
178 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
180 2009-11-04 DJ Delorie <dj@redhat.com>
182 * rx.h (rx_decode_opcode) (mvtipl): Add.
183 (mvtcp, mvfcp, opecp): Remove.
185 2009-11-02 Paul Brook <paul@codesourcery.com>
187 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
188 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
189 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
190 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
191 FPU_ARCH_NEON_VFP_V4): Define.
193 2009-10-23 Doug Evans <dje@sebabeach.org>
195 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
196 * cgen.h: Update. Improve multi-inclusion macro name.
198 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
200 * ppc.h (PPC_OPCODE_476): Define.
202 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
204 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
206 2009-09-29 DJ Delorie <dj@redhat.com>
210 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
212 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
214 2009-09-21 Ben Elliston <bje@au.ibm.com>
216 * ppc.h (PPC_OPCODE_PPCA2): New.
218 2009-09-05 Martin Thuresson <martin@mtme.org>
220 * ia64.h (struct ia64_operand): Renamed member class to op_class.
222 2009-08-29 Martin Thuresson <martin@mtme.org>
224 * tic30.h (template): Rename type template to
225 insn_template. Updated code to use new name.
226 * tic54x.h (template): Rename type template to
229 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
231 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
233 2009-06-11 Anthony Green <green@moxielogic.com>
235 * moxie.h (MOXIE_F3_PCREL): Define.
236 (moxie_form3_opc_info): Grow.
238 2009-06-06 Anthony Green <green@moxielogic.com>
240 * moxie.h (MOXIE_F1_M): Define.
242 2009-04-15 Anthony Green <green@moxielogic.com>
246 2009-04-06 DJ Delorie <dj@redhat.com>
248 * h8300.h: Add relaxation attributes to MOVA opcodes.
250 2009-03-10 Alan Modra <amodra@bigpond.net.au>
252 * ppc.h (ppc_parse_cpu): Declare.
254 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
256 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
257 and _IMM11 for mbitclr and mbitset.
258 * score-datadep.h: Update dependency information.
260 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
262 * ppc.h (PPC_OPCODE_POWER7): New.
264 2009-02-06 Doug Evans <dje@google.com>
266 * i386.h: Add comment regarding sse* insns and prefixes.
268 2009-02-03 Sandip Matte <sandip@rmicorp.com>
270 * mips.h (INSN_XLR): Define.
271 (INSN_CHIP_MASK): Update.
273 (OPCODE_IS_MEMBER): Update.
274 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
276 2009-01-28 Doug Evans <dje@google.com>
278 * opcode/i386.h: Add multiple inclusion protection.
279 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
280 (EDI_REG_NUM): New macros.
281 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
282 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
283 (REX_PREFIX_P): New macro.
285 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
287 * ppc.h (struct powerpc_opcode): New field "deprecated".
288 (PPC_OPCODE_NOPOWER4): Delete.
290 2008-11-28 Joshua Kinard <kumba@gentoo.org>
292 * mips.h: Define CPU_R14000, CPU_R16000.
293 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
295 2008-11-18 Catherine Moore <clm@codesourcery.com>
297 * arm.h (FPU_NEON_FP16): New.
298 (FPU_ARCH_NEON_FP16): New.
300 2008-11-06 Chao-ying Fu <fu@mips.com>
302 * mips.h: Doucument '1' for 5-bit sync type.
304 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
306 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
309 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
311 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
313 2008-07-30 Michael J. Eager <eager@eagercon.com>
315 * ppc.h (PPC_OPCODE_405): Define.
316 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
318 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
320 * ppc.h (ppc_cpu_t): New typedef.
321 (struct powerpc_opcode <flags>): Use it.
322 (struct powerpc_operand <insert, extract>): Likewise.
323 (struct powerpc_macro <flags>): Likewise.
325 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
327 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
328 Update comment before MIPS16 field descriptors to mention MIPS16.
329 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
331 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
332 New bit masks and shift counts for cins and exts.
334 * mips.h: Document new field descriptors +Q.
335 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
337 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
339 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
340 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
342 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
344 * ppc.h: (PPC_OPCODE_E500MC): New.
346 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
348 * i386.h (MAX_OPERANDS): Set to 5.
349 (MAX_MNEM_SIZE): Changed to 20.
351 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
353 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
355 2008-03-09 Paul Brook <paul@codesourcery.com>
357 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
359 2008-03-04 Paul Brook <paul@codesourcery.com>
361 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
362 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
363 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
365 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
366 Nick Clifton <nickc@redhat.com>
369 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
370 with a 32-bit displacement but without the top bit of the 4th byte
373 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
375 * cr16.h (cr16_num_optab): Declared.
377 2008-02-14 Hakan Ardo <hakan@debian.org>
380 * avr.h (AVR_ISA_2xxe): Define.
382 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
384 * mips.h: Update copyright.
385 (INSN_CHIP_MASK): New macro.
386 (INSN_OCTEON): New macro.
387 (CPU_OCTEON): New macro.
388 (OPCODE_IS_MEMBER): Handle Octeon instructions.
390 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
392 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
394 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
396 * avr.h (AVR_ISA_USB162): Add new opcode set.
397 (AVR_ISA_AVR3): Likewise.
399 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
401 * mips.h (INSN_LOONGSON_2E): New.
402 (INSN_LOONGSON_2F): New.
403 (CPU_LOONGSON_2E): New.
404 (CPU_LOONGSON_2F): New.
405 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
407 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
409 * mips.h (INSN_ISA*): Redefine certain values as an
410 enumeration. Update comments.
411 (mips_isa_table): New.
412 (ISA_MIPS*): Redefine to match enumeration.
413 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
416 2007-08-08 Ben Elliston <bje@au.ibm.com>
418 * ppc.h (PPC_OPCODE_PPCPS): New.
420 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
422 * m68k.h: Document j K & E.
424 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
426 * cr16.h: New file for CR16 target.
428 2007-05-02 Alan Modra <amodra@bigpond.net.au>
430 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
432 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
434 * m68k.h (mcfisa_c): New.
435 (mcfusp, mcf_mask): Adjust.
437 2007-04-20 Alan Modra <amodra@bigpond.net.au>
439 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
440 (num_powerpc_operands): Declare.
441 (PPC_OPERAND_SIGNED et al): Redefine as hex.
442 (PPC_OPERAND_PLUS1): Define.
444 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
446 * i386.h (REX_MODE64): Renamed to ...
448 (REX_EXTX): Renamed to ...
450 (REX_EXTY): Renamed to ...
452 (REX_EXTZ): Renamed to ...
455 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
457 * i386.h: Add entries from config/tc-i386.h and move tables
458 to opcodes/i386-opc.h.
460 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
462 * i386.h (FloatDR): Removed.
463 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
465 2007-03-01 Alan Modra <amodra@bigpond.net.au>
467 * spu-insns.h: Add soma double-float insns.
469 2007-02-20 Thiemo Seufer <ths@mips.com>
470 Chao-Ying Fu <fu@mips.com>
472 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
473 (INSN_DSPR2): Add flag for DSP R2 instructions.
474 (M_BALIGN): New macro.
476 2007-02-14 Alan Modra <amodra@bigpond.net.au>
478 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
479 and Seg3ShortFrom with Shortform.
481 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
484 * i386.h (i386_optab): Put the real "test" before the pseudo
487 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
489 * m68k.h (m68010up): OR fido_a.
491 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
493 * m68k.h (fido_a): New.
495 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
497 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
498 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
501 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
503 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
505 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
507 * score-inst.h (enum score_insn_type): Add Insn_internal.
509 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
510 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
511 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
512 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
513 Alan Modra <amodra@bigpond.net.au>
515 * spu-insns.h: New file.
518 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
520 * ppc.h (PPC_OPCODE_CELL): Define.
522 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
524 * i386.h : Modify opcode to support for the change in POPCNT opcode
525 in amdfam10 architecture.
527 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
529 * i386.h: Replace CpuMNI with CpuSSSE3.
531 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
532 Joseph Myers <joseph@codesourcery.com>
533 Ian Lance Taylor <ian@wasabisystems.com>
534 Ben Elliston <bje@wasabisystems.com>
536 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
538 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
540 * score-datadep.h: New file.
541 * score-inst.h: New file.
543 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
545 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
546 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
549 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
550 Michael Meissner <michael.meissner@amd.com>
552 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
554 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
556 * i386.h (i386_optab): Add "nop" with memory reference.
558 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
560 * i386.h (i386_optab): Update comment for 64bit NOP.
562 2006-06-06 Ben Elliston <bje@au.ibm.com>
563 Anton Blanchard <anton@samba.org>
565 * ppc.h (PPC_OPCODE_POWER6): Define.
568 2006-06-05 Thiemo Seufer <ths@mips.com>
570 * mips.h: Improve description of MT flags.
572 2006-05-25 Richard Sandiford <richard@codesourcery.com>
574 * m68k.h (mcf_mask): Define.
576 2006-05-05 Thiemo Seufer <ths@mips.com>
577 David Ung <davidu@mips.com>
579 * mips.h (enum): Add macro M_CACHE_AB.
581 2006-05-04 Thiemo Seufer <ths@mips.com>
582 Nigel Stephens <nigel@mips.com>
583 David Ung <davidu@mips.com>
585 * mips.h: Add INSN_SMARTMIPS define.
587 2006-04-30 Thiemo Seufer <ths@mips.com>
588 David Ung <davidu@mips.com>
590 * mips.h: Defines udi bits and masks. Add description of
591 characters which may appear in the args field of udi
594 2006-04-26 Thiemo Seufer <ths@networkno.de>
596 * mips.h: Improve comments describing the bitfield instruction
599 2006-04-26 Julian Brown <julian@codesourcery.com>
601 * arm.h (FPU_VFP_EXT_V3): Define constant.
602 (FPU_NEON_EXT_V1): Likewise.
603 (FPU_VFP_HARD): Update.
604 (FPU_VFP_V3): Define macro.
605 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
607 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
609 * avr.h (AVR_ISA_PWMx): New.
611 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
613 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
614 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
615 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
616 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
617 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
619 2006-03-10 Paul Brook <paul@codesourcery.com>
621 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
623 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
625 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
626 first. Correct mask of bb "B" opcode.
628 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
630 * i386.h (i386_optab): Support Intel Merom New Instructions.
632 2006-02-24 Paul Brook <paul@codesourcery.com>
634 * arm.h: Add V7 feature bits.
636 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
638 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
640 2006-01-31 Paul Brook <paul@codesourcery.com>
641 Richard Earnshaw <rearnsha@arm.com>
643 * arm.h: Use ARM_CPU_FEATURE.
644 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
645 (arm_feature_set): Change to a structure.
646 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
647 ARM_FEATURE): New macros.
649 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
651 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
652 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
653 (ADD_PC_INCR_OPCODE): Don't define.
655 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
658 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
660 2005-11-14 David Ung <davidu@mips.com>
662 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
663 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
664 save/restore encoding of the args field.
666 2005-10-28 Dave Brolley <brolley@redhat.com>
668 Contribute the following changes:
669 2005-02-16 Dave Brolley <brolley@redhat.com>
671 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
672 cgen_isa_mask_* to cgen_bitset_*.
675 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
677 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
678 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
679 (CGEN_CPU_TABLE): Make isas a ponter.
681 2003-09-29 Dave Brolley <brolley@redhat.com>
683 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
684 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
685 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
687 2002-12-13 Dave Brolley <brolley@redhat.com>
689 * cgen.h (symcat.h): #include it.
690 (cgen-bitset.h): #include it.
691 (CGEN_ATTR_VALUE_TYPE): Now a union.
692 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
693 (CGEN_ATTR_ENTRY): 'value' now unsigned.
694 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
695 * cgen-bitset.h: New file.
697 2005-09-30 Catherine Moore <clm@cm00re.com>
701 2005-10-24 Jan Beulich <jbeulich@novell.com>
703 * ia64.h (enum ia64_opnd): Move memory operand out of set of
706 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
708 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
709 Add FLAG_STRICT to pa10 ftest opcode.
711 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
713 * hppa.h (pa_opcodes): Remove lha entries.
715 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
717 * hppa.h (FLAG_STRICT): Revise comment.
718 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
719 before corresponding pa11 opcodes. Add strict pa10 register-immediate
722 2005-09-30 Catherine Moore <clm@cm00re.com>
726 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
728 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
730 2005-09-06 Chao-ying Fu <fu@mips.com>
732 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
733 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
735 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
736 (INSN_ASE_MASK): Update to include INSN_MT.
737 (INSN_MT): New define for MT ASE.
739 2005-08-25 Chao-ying Fu <fu@mips.com>
741 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
742 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
743 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
744 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
745 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
746 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
748 (INSN_DSP): New define for DSP ASE.
750 2005-08-18 Alan Modra <amodra@bigpond.net.au>
754 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
756 * ppc.h (PPC_OPCODE_E300): Define.
758 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
760 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
762 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
765 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
768 2005-07-27 Jan Beulich <jbeulich@novell.com>
770 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
771 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
772 Add movq-s as 64-bit variants of movd-s.
774 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
776 * hppa.h: Fix punctuation in comment.
778 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
779 implicit space-register addressing. Set space-register bits on opcodes
780 using implicit space-register addressing. Add various missing pa20
781 long-immediate opcodes. Remove various opcodes using implicit 3-bit
782 space-register addressing. Use "fE" instead of "fe" in various
785 2005-07-18 Jan Beulich <jbeulich@novell.com>
787 * i386.h (i386_optab): Operands of aam and aad are unsigned.
789 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
791 * i386.h (i386_optab): Support Intel VMX Instructions.
793 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
795 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
797 2005-07-05 Jan Beulich <jbeulich@novell.com>
799 * i386.h (i386_optab): Add new insns.
801 2005-07-01 Nick Clifton <nickc@redhat.com>
803 * sparc.h: Add typedefs to structure declarations.
805 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
808 * i386.h (i386_optab): Update comments for 64bit addressing on
809 mov. Allow 64bit addressing for mov and movq.
811 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
813 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
814 respectively, in various floating-point load and store patterns.
816 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
818 * hppa.h (FLAG_STRICT): Correct comment.
819 (pa_opcodes): Update load and store entries to allow both PA 1.X and
820 PA 2.0 mneumonics when equivalent. Entries with cache control
821 completers now require PA 1.1. Adjust whitespace.
823 2005-05-19 Anton Blanchard <anton@samba.org>
825 * ppc.h (PPC_OPCODE_POWER5): Define.
827 2005-05-10 Nick Clifton <nickc@redhat.com>
829 * Update the address and phone number of the FSF organization in
830 the GPL notices in the following files:
831 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
832 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
833 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
834 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
835 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
836 tic54x.h, tic80.h, v850.h, vax.h
838 2005-05-09 Jan Beulich <jbeulich@novell.com>
840 * i386.h (i386_optab): Add ht and hnt.
842 2005-04-18 Mark Kettenis <kettenis@gnu.org>
844 * i386.h: Insert hyphens into selected VIA PadLock extensions.
845 Add xcrypt-ctr. Provide aliases without hyphens.
847 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
849 Moved from ../ChangeLog
851 2005-04-12 Paul Brook <paul@codesourcery.com>
852 * m88k.h: Rename psr macros to avoid conflicts.
854 2005-03-12 Zack Weinberg <zack@codesourcery.com>
855 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
856 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
859 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
860 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
861 Remove redundant instruction types.
862 (struct argument): X_op - new field.
863 (struct cst4_entry): Remove.
864 (no_op_insn): Declare.
866 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
867 * crx.h (enum argtype): Rename types, remove unused types.
869 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
870 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
871 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
872 (enum operand_type): Rearrange operands, edit comments.
873 replace us<N> with ui<N> for unsigned immediate.
874 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
875 displacements (respectively).
876 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
877 (instruction type): Add NO_TYPE_INS.
878 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
879 (operand_entry): New field - 'flags'.
880 (operand flags): New.
882 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
883 * crx.h (operand_type): Remove redundant types i3, i4,
885 Add new unsigned immediate types us3, us4, us5, us16.
887 2005-04-12 Mark Kettenis <kettenis@gnu.org>
889 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
890 adjust them accordingly.
892 2005-04-01 Jan Beulich <jbeulich@novell.com>
894 * i386.h (i386_optab): Add rdtscp.
896 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
898 * i386.h (i386_optab): Don't allow the `l' suffix for moving
899 between memory and segment register. Allow movq for moving between
900 general-purpose register and segment register.
902 2005-02-09 Jan Beulich <jbeulich@novell.com>
905 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
906 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
909 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
911 * m68k.h (m68008, m68ec030, m68882): Remove.
913 (cpu_m68k, cpu_cf): New.
914 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
915 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
917 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
919 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
920 * cgen.h (enum cgen_parse_operand_type): Add
921 CGEN_PARSE_OPERAND_SYMBOLIC.
923 2005-01-21 Fred Fish <fnf@specifixinc.com>
925 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
926 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
927 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
929 2005-01-19 Fred Fish <fnf@specifixinc.com>
931 * mips.h (struct mips_opcode): Add new pinfo2 member.
932 (INSN_ALIAS): New define for opcode table entries that are
933 specific instances of another entry, such as 'move' for an 'or'
935 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
936 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
938 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
940 * mips.h (CPU_RM9000): Define.
941 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
943 2004-11-25 Jan Beulich <jbeulich@novell.com>
945 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
946 to/from test registers are illegal in 64-bit mode. Add missing
947 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
948 (previously one had to explicitly encode a rex64 prefix). Re-enable
949 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
950 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
952 2004-11-23 Jan Beulich <jbeulich@novell.com>
954 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
955 available only with SSE2. Change the MMX additions introduced by SSE
956 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
957 instructions by their now designated identifier (since combining i686
958 and 3DNow! does not really imply 3DNow!A).
960 2004-11-19 Alan Modra <amodra@bigpond.net.au>
962 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
963 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
965 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
966 Vineet Sharma <vineets@noida.hcltech.com>
968 * maxq.h: New file: Disassembly information for the maxq port.
970 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
972 * i386.h (i386_optab): Put back "movzb".
974 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
976 * cris.h (enum cris_insn_version_usage): Tweak formatting and
977 comments. Remove member cris_ver_sim. Add members
978 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
979 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
980 (struct cris_support_reg, struct cris_cond15): New types.
981 (cris_conds15): Declare.
982 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
983 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
984 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
985 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
986 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
989 2004-11-04 Jan Beulich <jbeulich@novell.com>
991 * i386.h (sldx_Suf): Remove.
992 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
993 (q_FP): Define, implying no REX64.
994 (x_FP, sl_FP): Imply FloatMF.
995 (i386_optab): Split reg and mem forms of moving from segment registers
996 so that the memory forms can ignore the 16-/32-bit operand size
997 distinction. Adjust a few others for Intel mode. Remove *FP uses from
998 all non-floating-point instructions. Unite 32- and 64-bit forms of
999 movsx, movzx, and movd. Adjust floating point operations for the above
1000 changes to the *FP macros. Add DefaultSize to floating point control
1001 insns operating on larger memory ranges. Remove left over comments
1002 hinting at certain insns being Intel-syntax ones where the ones
1003 actually meant are already gone.
1005 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1007 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1010 2004-09-30 Paul Brook <paul@codesourcery.com>
1012 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1013 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1015 2004-09-11 Theodore A. Roth <troth@openavr.org>
1017 * avr.h: Add support for
1018 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1020 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1022 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1024 2004-08-24 Dmitry Diky <diwil@spec.ru>
1026 * msp430.h (msp430_opc): Add new instructions.
1027 (msp430_rcodes): Declare new instructions.
1028 (msp430_hcodes): Likewise..
1030 2004-08-13 Nick Clifton <nickc@redhat.com>
1033 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1036 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1038 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1040 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1042 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1044 2004-07-21 Jan Beulich <jbeulich@novell.com>
1046 * i386.h: Adjust instruction descriptions to better match the
1049 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
1051 * arm.h: Remove all old content. Replace with architecture defines
1052 from gas/config/tc-arm.c.
1054 2004-07-09 Andreas Schwab <schwab@suse.de>
1056 * m68k.h: Fix comment.
1058 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1062 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1064 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1066 2004-05-24 Peter Barada <peter@the-baradas.com>
1068 * m68k.h: Add 'size' to m68k_opcode.
1070 2004-05-05 Peter Barada <peter@the-baradas.com>
1072 * m68k.h: Switch from ColdFire chip name to core variant.
1074 2004-04-22 Peter Barada <peter@the-baradas.com>
1076 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1077 descriptions for new EMAC cases.
1078 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1079 handle Motorola MAC syntax.
1080 Allow disassembly of ColdFire V4e object files.
1082 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1084 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1086 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1088 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1090 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1092 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1094 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1096 * i386.h (i386_optab): Added xstore/xcrypt insns.
1098 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1100 * h8300.h (32bit ldc/stc): Add relaxing support.
1102 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1104 * h8300.h (BITOP): Pass MEMRELAX flag.
1106 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1108 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1111 For older changes see ChangeLog-9103
1117 version-control: never