1 2011-02-12 Mike Frysinger <vapier@gentoo.org>
3 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
5 (is_macmod_pmove, is_macmod_hmove): New functions.
7 2011-02-11 Mike Frysinger <vapier@gentoo.org>
9 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
11 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
13 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
14 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
16 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
19 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
22 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
25 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
27 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
29 * mips.h: Update commentary after last commit.
31 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
33 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
34 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
35 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
37 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
39 * mips.h: Fix previous commit.
41 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
43 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
44 (INSN_LOONGSON_3A): Clear bit 31.
46 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
49 * arm.h (ARM_AEXT_V6M_ONLY): New define.
50 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
51 (ARM_ARCH_V6M_ONLY): New define.
53 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
55 * mips.h (INSN_LOONGSON_3A): Defined.
56 (CPU_LOONGSON_3A): Defined.
57 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
59 2010-10-09 Matt Rice <ratmice@gmail.com>
61 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
62 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
64 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
66 * arm.h (ARM_EXT_VIRT): New define.
67 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
68 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
71 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
73 * arm.h (ARM_AEXT_ADIV): New define.
74 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
76 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
78 * arm.h (ARM_EXT_OS): New define.
79 (ARM_AEXT_V6SM): Likewise.
80 (ARM_ARCH_V6SM): Likewise.
82 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
84 * arm.h (ARM_EXT_MP): Add.
85 (ARM_ARCH_V7A_MP): Likewise.
87 2010-09-22 Mike Frysinger <vapier@gentoo.org>
89 * bfin.h: Declare pseudoChr structs/defines.
91 2010-09-21 Mike Frysinger <vapier@gentoo.org>
93 * bfin.h: Strip trailing whitespace.
95 2010-07-29 DJ Delorie <dj@redhat.com>
97 * rx.h (RX_Operand_Type): Add TwoReg.
98 (RX_Opcode_ID): Remove ediv and ediv2.
100 2010-07-27 DJ Delorie <dj@redhat.com>
102 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
104 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
105 Ina Pandit <ina.pandit@kpitcummins.com>
107 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
108 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
109 PROCESSOR_V850E2_ALL.
110 Remove PROCESSOR_V850EA support.
111 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
112 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
113 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
114 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
115 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
116 V850_OPERAND_PERCENT.
117 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
119 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
122 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
124 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
125 (MIPS16_INSN_BRANCH): Rename to...
126 (MIPS16_INSN_COND_BRANCH): ... this.
128 2010-07-03 Alan Modra <amodra@gmail.com>
130 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
131 Renumber other PPC_OPCODE defines.
133 2010-07-03 Alan Modra <amodra@gmail.com>
135 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
137 2010-06-29 Alan Modra <amodra@gmail.com>
139 * maxq.h: Delete file.
141 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
143 * ppc.h (PPC_OPCODE_E500): Define.
145 2010-05-26 Catherine Moore <clm@codesourcery.com>
147 * opcode/mips.h (INSN_MIPS16): Remove.
149 2010-04-21 Joseph Myers <joseph@codesourcery.com>
151 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
153 2010-04-15 Nick Clifton <nickc@redhat.com>
155 * alpha.h: Update copyright notice to use GPLv3.
161 * convex.h: Likewise.
175 * m68hc11.h: Likewise.
181 * mn10200.h: Likewise.
182 * mn10300.h: Likewise.
183 * msp430.h: Likewise.
194 * score-datadep.h: Likewise.
195 * score-inst.h: Likewise.
197 * spu-insns.h: Likewise.
201 * tic54x.h: Likewise.
206 2010-03-25 Joseph Myers <joseph@codesourcery.com>
208 * tic6x-control-registers.h, tic6x-insn-formats.h,
209 tic6x-opcode-table.h, tic6x.h: New.
211 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
213 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
215 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
217 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
219 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
221 * ia64.h (ia64_find_opcode): Remove argument name.
222 (ia64_find_next_opcode): Likewise.
223 (ia64_dis_opcode): Likewise.
224 (ia64_free_opcode): Likewise.
225 (ia64_find_dependency): Likewise.
227 2009-11-22 Doug Evans <dje@sebabeach.org>
229 * cgen.h: Include bfd_stdint.h.
230 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
232 2009-11-18 Paul Brook <paul@codesourcery.com>
234 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
236 2009-11-17 Paul Brook <paul@codesourcery.com>
237 Daniel Jacobowitz <dan@codesourcery.com>
239 * arm.h (ARM_EXT_V6_DSP): Define.
240 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
241 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
243 2009-11-04 DJ Delorie <dj@redhat.com>
245 * rx.h (rx_decode_opcode) (mvtipl): Add.
246 (mvtcp, mvfcp, opecp): Remove.
248 2009-11-02 Paul Brook <paul@codesourcery.com>
250 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
251 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
252 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
253 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
254 FPU_ARCH_NEON_VFP_V4): Define.
256 2009-10-23 Doug Evans <dje@sebabeach.org>
258 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
259 * cgen.h: Update. Improve multi-inclusion macro name.
261 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
263 * ppc.h (PPC_OPCODE_476): Define.
265 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
267 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
269 2009-09-29 DJ Delorie <dj@redhat.com>
273 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
275 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
277 2009-09-21 Ben Elliston <bje@au.ibm.com>
279 * ppc.h (PPC_OPCODE_PPCA2): New.
281 2009-09-05 Martin Thuresson <martin@mtme.org>
283 * ia64.h (struct ia64_operand): Renamed member class to op_class.
285 2009-08-29 Martin Thuresson <martin@mtme.org>
287 * tic30.h (template): Rename type template to
288 insn_template. Updated code to use new name.
289 * tic54x.h (template): Rename type template to
292 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
294 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
296 2009-06-11 Anthony Green <green@moxielogic.com>
298 * moxie.h (MOXIE_F3_PCREL): Define.
299 (moxie_form3_opc_info): Grow.
301 2009-06-06 Anthony Green <green@moxielogic.com>
303 * moxie.h (MOXIE_F1_M): Define.
305 2009-04-15 Anthony Green <green@moxielogic.com>
309 2009-04-06 DJ Delorie <dj@redhat.com>
311 * h8300.h: Add relaxation attributes to MOVA opcodes.
313 2009-03-10 Alan Modra <amodra@bigpond.net.au>
315 * ppc.h (ppc_parse_cpu): Declare.
317 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
319 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
320 and _IMM11 for mbitclr and mbitset.
321 * score-datadep.h: Update dependency information.
323 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
325 * ppc.h (PPC_OPCODE_POWER7): New.
327 2009-02-06 Doug Evans <dje@google.com>
329 * i386.h: Add comment regarding sse* insns and prefixes.
331 2009-02-03 Sandip Matte <sandip@rmicorp.com>
333 * mips.h (INSN_XLR): Define.
334 (INSN_CHIP_MASK): Update.
336 (OPCODE_IS_MEMBER): Update.
337 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
339 2009-01-28 Doug Evans <dje@google.com>
341 * opcode/i386.h: Add multiple inclusion protection.
342 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
343 (EDI_REG_NUM): New macros.
344 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
345 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
346 (REX_PREFIX_P): New macro.
348 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
350 * ppc.h (struct powerpc_opcode): New field "deprecated".
351 (PPC_OPCODE_NOPOWER4): Delete.
353 2008-11-28 Joshua Kinard <kumba@gentoo.org>
355 * mips.h: Define CPU_R14000, CPU_R16000.
356 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
358 2008-11-18 Catherine Moore <clm@codesourcery.com>
360 * arm.h (FPU_NEON_FP16): New.
361 (FPU_ARCH_NEON_FP16): New.
363 2008-11-06 Chao-ying Fu <fu@mips.com>
365 * mips.h: Doucument '1' for 5-bit sync type.
367 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
369 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
372 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
374 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
376 2008-07-30 Michael J. Eager <eager@eagercon.com>
378 * ppc.h (PPC_OPCODE_405): Define.
379 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
381 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
383 * ppc.h (ppc_cpu_t): New typedef.
384 (struct powerpc_opcode <flags>): Use it.
385 (struct powerpc_operand <insert, extract>): Likewise.
386 (struct powerpc_macro <flags>): Likewise.
388 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
390 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
391 Update comment before MIPS16 field descriptors to mention MIPS16.
392 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
394 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
395 New bit masks and shift counts for cins and exts.
397 * mips.h: Document new field descriptors +Q.
398 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
400 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
402 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
403 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
405 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
407 * ppc.h: (PPC_OPCODE_E500MC): New.
409 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
411 * i386.h (MAX_OPERANDS): Set to 5.
412 (MAX_MNEM_SIZE): Changed to 20.
414 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
416 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
418 2008-03-09 Paul Brook <paul@codesourcery.com>
420 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
422 2008-03-04 Paul Brook <paul@codesourcery.com>
424 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
425 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
426 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
428 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
429 Nick Clifton <nickc@redhat.com>
432 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
433 with a 32-bit displacement but without the top bit of the 4th byte
436 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
438 * cr16.h (cr16_num_optab): Declared.
440 2008-02-14 Hakan Ardo <hakan@debian.org>
443 * avr.h (AVR_ISA_2xxe): Define.
445 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
447 * mips.h: Update copyright.
448 (INSN_CHIP_MASK): New macro.
449 (INSN_OCTEON): New macro.
450 (CPU_OCTEON): New macro.
451 (OPCODE_IS_MEMBER): Handle Octeon instructions.
453 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
455 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
457 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
459 * avr.h (AVR_ISA_USB162): Add new opcode set.
460 (AVR_ISA_AVR3): Likewise.
462 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
464 * mips.h (INSN_LOONGSON_2E): New.
465 (INSN_LOONGSON_2F): New.
466 (CPU_LOONGSON_2E): New.
467 (CPU_LOONGSON_2F): New.
468 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
470 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
472 * mips.h (INSN_ISA*): Redefine certain values as an
473 enumeration. Update comments.
474 (mips_isa_table): New.
475 (ISA_MIPS*): Redefine to match enumeration.
476 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
479 2007-08-08 Ben Elliston <bje@au.ibm.com>
481 * ppc.h (PPC_OPCODE_PPCPS): New.
483 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
485 * m68k.h: Document j K & E.
487 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
489 * cr16.h: New file for CR16 target.
491 2007-05-02 Alan Modra <amodra@bigpond.net.au>
493 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
495 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
497 * m68k.h (mcfisa_c): New.
498 (mcfusp, mcf_mask): Adjust.
500 2007-04-20 Alan Modra <amodra@bigpond.net.au>
502 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
503 (num_powerpc_operands): Declare.
504 (PPC_OPERAND_SIGNED et al): Redefine as hex.
505 (PPC_OPERAND_PLUS1): Define.
507 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
509 * i386.h (REX_MODE64): Renamed to ...
511 (REX_EXTX): Renamed to ...
513 (REX_EXTY): Renamed to ...
515 (REX_EXTZ): Renamed to ...
518 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
520 * i386.h: Add entries from config/tc-i386.h and move tables
521 to opcodes/i386-opc.h.
523 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
525 * i386.h (FloatDR): Removed.
526 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
528 2007-03-01 Alan Modra <amodra@bigpond.net.au>
530 * spu-insns.h: Add soma double-float insns.
532 2007-02-20 Thiemo Seufer <ths@mips.com>
533 Chao-Ying Fu <fu@mips.com>
535 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
536 (INSN_DSPR2): Add flag for DSP R2 instructions.
537 (M_BALIGN): New macro.
539 2007-02-14 Alan Modra <amodra@bigpond.net.au>
541 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
542 and Seg3ShortFrom with Shortform.
544 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
547 * i386.h (i386_optab): Put the real "test" before the pseudo
550 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
552 * m68k.h (m68010up): OR fido_a.
554 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
556 * m68k.h (fido_a): New.
558 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
560 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
561 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
564 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
566 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
568 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
570 * score-inst.h (enum score_insn_type): Add Insn_internal.
572 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
573 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
574 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
575 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
576 Alan Modra <amodra@bigpond.net.au>
578 * spu-insns.h: New file.
581 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
583 * ppc.h (PPC_OPCODE_CELL): Define.
585 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
587 * i386.h : Modify opcode to support for the change in POPCNT opcode
588 in amdfam10 architecture.
590 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
592 * i386.h: Replace CpuMNI with CpuSSSE3.
594 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
595 Joseph Myers <joseph@codesourcery.com>
596 Ian Lance Taylor <ian@wasabisystems.com>
597 Ben Elliston <bje@wasabisystems.com>
599 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
601 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
603 * score-datadep.h: New file.
604 * score-inst.h: New file.
606 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
608 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
609 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
612 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
613 Michael Meissner <michael.meissner@amd.com>
615 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
617 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
619 * i386.h (i386_optab): Add "nop" with memory reference.
621 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
623 * i386.h (i386_optab): Update comment for 64bit NOP.
625 2006-06-06 Ben Elliston <bje@au.ibm.com>
626 Anton Blanchard <anton@samba.org>
628 * ppc.h (PPC_OPCODE_POWER6): Define.
631 2006-06-05 Thiemo Seufer <ths@mips.com>
633 * mips.h: Improve description of MT flags.
635 2006-05-25 Richard Sandiford <richard@codesourcery.com>
637 * m68k.h (mcf_mask): Define.
639 2006-05-05 Thiemo Seufer <ths@mips.com>
640 David Ung <davidu@mips.com>
642 * mips.h (enum): Add macro M_CACHE_AB.
644 2006-05-04 Thiemo Seufer <ths@mips.com>
645 Nigel Stephens <nigel@mips.com>
646 David Ung <davidu@mips.com>
648 * mips.h: Add INSN_SMARTMIPS define.
650 2006-04-30 Thiemo Seufer <ths@mips.com>
651 David Ung <davidu@mips.com>
653 * mips.h: Defines udi bits and masks. Add description of
654 characters which may appear in the args field of udi
657 2006-04-26 Thiemo Seufer <ths@networkno.de>
659 * mips.h: Improve comments describing the bitfield instruction
662 2006-04-26 Julian Brown <julian@codesourcery.com>
664 * arm.h (FPU_VFP_EXT_V3): Define constant.
665 (FPU_NEON_EXT_V1): Likewise.
666 (FPU_VFP_HARD): Update.
667 (FPU_VFP_V3): Define macro.
668 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
670 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
672 * avr.h (AVR_ISA_PWMx): New.
674 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
676 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
677 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
678 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
679 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
680 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
682 2006-03-10 Paul Brook <paul@codesourcery.com>
684 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
686 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
688 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
689 first. Correct mask of bb "B" opcode.
691 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
693 * i386.h (i386_optab): Support Intel Merom New Instructions.
695 2006-02-24 Paul Brook <paul@codesourcery.com>
697 * arm.h: Add V7 feature bits.
699 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
701 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
703 2006-01-31 Paul Brook <paul@codesourcery.com>
704 Richard Earnshaw <rearnsha@arm.com>
706 * arm.h: Use ARM_CPU_FEATURE.
707 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
708 (arm_feature_set): Change to a structure.
709 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
710 ARM_FEATURE): New macros.
712 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
714 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
715 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
716 (ADD_PC_INCR_OPCODE): Don't define.
718 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
721 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
723 2005-11-14 David Ung <davidu@mips.com>
725 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
726 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
727 save/restore encoding of the args field.
729 2005-10-28 Dave Brolley <brolley@redhat.com>
731 Contribute the following changes:
732 2005-02-16 Dave Brolley <brolley@redhat.com>
734 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
735 cgen_isa_mask_* to cgen_bitset_*.
738 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
740 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
741 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
742 (CGEN_CPU_TABLE): Make isas a ponter.
744 2003-09-29 Dave Brolley <brolley@redhat.com>
746 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
747 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
748 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
750 2002-12-13 Dave Brolley <brolley@redhat.com>
752 * cgen.h (symcat.h): #include it.
753 (cgen-bitset.h): #include it.
754 (CGEN_ATTR_VALUE_TYPE): Now a union.
755 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
756 (CGEN_ATTR_ENTRY): 'value' now unsigned.
757 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
758 * cgen-bitset.h: New file.
760 2005-09-30 Catherine Moore <clm@cm00re.com>
764 2005-10-24 Jan Beulich <jbeulich@novell.com>
766 * ia64.h (enum ia64_opnd): Move memory operand out of set of
769 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
771 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
772 Add FLAG_STRICT to pa10 ftest opcode.
774 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
776 * hppa.h (pa_opcodes): Remove lha entries.
778 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
780 * hppa.h (FLAG_STRICT): Revise comment.
781 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
782 before corresponding pa11 opcodes. Add strict pa10 register-immediate
785 2005-09-30 Catherine Moore <clm@cm00re.com>
789 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
791 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
793 2005-09-06 Chao-ying Fu <fu@mips.com>
795 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
796 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
798 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
799 (INSN_ASE_MASK): Update to include INSN_MT.
800 (INSN_MT): New define for MT ASE.
802 2005-08-25 Chao-ying Fu <fu@mips.com>
804 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
805 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
806 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
807 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
808 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
809 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
811 (INSN_DSP): New define for DSP ASE.
813 2005-08-18 Alan Modra <amodra@bigpond.net.au>
817 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
819 * ppc.h (PPC_OPCODE_E300): Define.
821 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
823 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
825 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
828 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
831 2005-07-27 Jan Beulich <jbeulich@novell.com>
833 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
834 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
835 Add movq-s as 64-bit variants of movd-s.
837 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
839 * hppa.h: Fix punctuation in comment.
841 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
842 implicit space-register addressing. Set space-register bits on opcodes
843 using implicit space-register addressing. Add various missing pa20
844 long-immediate opcodes. Remove various opcodes using implicit 3-bit
845 space-register addressing. Use "fE" instead of "fe" in various
848 2005-07-18 Jan Beulich <jbeulich@novell.com>
850 * i386.h (i386_optab): Operands of aam and aad are unsigned.
852 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
854 * i386.h (i386_optab): Support Intel VMX Instructions.
856 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
858 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
860 2005-07-05 Jan Beulich <jbeulich@novell.com>
862 * i386.h (i386_optab): Add new insns.
864 2005-07-01 Nick Clifton <nickc@redhat.com>
866 * sparc.h: Add typedefs to structure declarations.
868 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
871 * i386.h (i386_optab): Update comments for 64bit addressing on
872 mov. Allow 64bit addressing for mov and movq.
874 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
876 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
877 respectively, in various floating-point load and store patterns.
879 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
881 * hppa.h (FLAG_STRICT): Correct comment.
882 (pa_opcodes): Update load and store entries to allow both PA 1.X and
883 PA 2.0 mneumonics when equivalent. Entries with cache control
884 completers now require PA 1.1. Adjust whitespace.
886 2005-05-19 Anton Blanchard <anton@samba.org>
888 * ppc.h (PPC_OPCODE_POWER5): Define.
890 2005-05-10 Nick Clifton <nickc@redhat.com>
892 * Update the address and phone number of the FSF organization in
893 the GPL notices in the following files:
894 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
895 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
896 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
897 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
898 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
899 tic54x.h, tic80.h, v850.h, vax.h
901 2005-05-09 Jan Beulich <jbeulich@novell.com>
903 * i386.h (i386_optab): Add ht and hnt.
905 2005-04-18 Mark Kettenis <kettenis@gnu.org>
907 * i386.h: Insert hyphens into selected VIA PadLock extensions.
908 Add xcrypt-ctr. Provide aliases without hyphens.
910 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
912 Moved from ../ChangeLog
914 2005-04-12 Paul Brook <paul@codesourcery.com>
915 * m88k.h: Rename psr macros to avoid conflicts.
917 2005-03-12 Zack Weinberg <zack@codesourcery.com>
918 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
919 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
922 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
923 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
924 Remove redundant instruction types.
925 (struct argument): X_op - new field.
926 (struct cst4_entry): Remove.
927 (no_op_insn): Declare.
929 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
930 * crx.h (enum argtype): Rename types, remove unused types.
932 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
933 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
934 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
935 (enum operand_type): Rearrange operands, edit comments.
936 replace us<N> with ui<N> for unsigned immediate.
937 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
938 displacements (respectively).
939 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
940 (instruction type): Add NO_TYPE_INS.
941 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
942 (operand_entry): New field - 'flags'.
943 (operand flags): New.
945 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
946 * crx.h (operand_type): Remove redundant types i3, i4,
948 Add new unsigned immediate types us3, us4, us5, us16.
950 2005-04-12 Mark Kettenis <kettenis@gnu.org>
952 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
953 adjust them accordingly.
955 2005-04-01 Jan Beulich <jbeulich@novell.com>
957 * i386.h (i386_optab): Add rdtscp.
959 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
961 * i386.h (i386_optab): Don't allow the `l' suffix for moving
962 between memory and segment register. Allow movq for moving between
963 general-purpose register and segment register.
965 2005-02-09 Jan Beulich <jbeulich@novell.com>
968 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
969 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
972 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
974 * m68k.h (m68008, m68ec030, m68882): Remove.
976 (cpu_m68k, cpu_cf): New.
977 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
978 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
980 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
982 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
983 * cgen.h (enum cgen_parse_operand_type): Add
984 CGEN_PARSE_OPERAND_SYMBOLIC.
986 2005-01-21 Fred Fish <fnf@specifixinc.com>
988 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
989 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
990 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
992 2005-01-19 Fred Fish <fnf@specifixinc.com>
994 * mips.h (struct mips_opcode): Add new pinfo2 member.
995 (INSN_ALIAS): New define for opcode table entries that are
996 specific instances of another entry, such as 'move' for an 'or'
998 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
999 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1001 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1003 * mips.h (CPU_RM9000): Define.
1004 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1006 2004-11-25 Jan Beulich <jbeulich@novell.com>
1008 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1009 to/from test registers are illegal in 64-bit mode. Add missing
1010 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1011 (previously one had to explicitly encode a rex64 prefix). Re-enable
1012 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1013 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1015 2004-11-23 Jan Beulich <jbeulich@novell.com>
1017 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1018 available only with SSE2. Change the MMX additions introduced by SSE
1019 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1020 instructions by their now designated identifier (since combining i686
1021 and 3DNow! does not really imply 3DNow!A).
1023 2004-11-19 Alan Modra <amodra@bigpond.net.au>
1025 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1026 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1028 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1029 Vineet Sharma <vineets@noida.hcltech.com>
1031 * maxq.h: New file: Disassembly information for the maxq port.
1033 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1035 * i386.h (i386_optab): Put back "movzb".
1037 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
1039 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1040 comments. Remove member cris_ver_sim. Add members
1041 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1042 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1043 (struct cris_support_reg, struct cris_cond15): New types.
1044 (cris_conds15): Declare.
1045 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1046 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1047 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1048 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1049 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1050 SIZE_FIELD_UNSIGNED.
1052 2004-11-04 Jan Beulich <jbeulich@novell.com>
1054 * i386.h (sldx_Suf): Remove.
1055 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1056 (q_FP): Define, implying no REX64.
1057 (x_FP, sl_FP): Imply FloatMF.
1058 (i386_optab): Split reg and mem forms of moving from segment registers
1059 so that the memory forms can ignore the 16-/32-bit operand size
1060 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1061 all non-floating-point instructions. Unite 32- and 64-bit forms of
1062 movsx, movzx, and movd. Adjust floating point operations for the above
1063 changes to the *FP macros. Add DefaultSize to floating point control
1064 insns operating on larger memory ranges. Remove left over comments
1065 hinting at certain insns being Intel-syntax ones where the ones
1066 actually meant are already gone.
1068 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1070 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1073 2004-09-30 Paul Brook <paul@codesourcery.com>
1075 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1076 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1078 2004-09-11 Theodore A. Roth <troth@openavr.org>
1080 * avr.h: Add support for
1081 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1083 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1085 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1087 2004-08-24 Dmitry Diky <diwil@spec.ru>
1089 * msp430.h (msp430_opc): Add new instructions.
1090 (msp430_rcodes): Declare new instructions.
1091 (msp430_hcodes): Likewise..
1093 2004-08-13 Nick Clifton <nickc@redhat.com>
1096 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1099 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1101 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1103 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1105 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1107 2004-07-21 Jan Beulich <jbeulich@novell.com>
1109 * i386.h: Adjust instruction descriptions to better match the
1112 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
1114 * arm.h: Remove all old content. Replace with architecture defines
1115 from gas/config/tc-arm.c.
1117 2004-07-09 Andreas Schwab <schwab@suse.de>
1119 * m68k.h: Fix comment.
1121 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1125 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1127 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1129 2004-05-24 Peter Barada <peter@the-baradas.com>
1131 * m68k.h: Add 'size' to m68k_opcode.
1133 2004-05-05 Peter Barada <peter@the-baradas.com>
1135 * m68k.h: Switch from ColdFire chip name to core variant.
1137 2004-04-22 Peter Barada <peter@the-baradas.com>
1139 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1140 descriptions for new EMAC cases.
1141 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1142 handle Motorola MAC syntax.
1143 Allow disassembly of ColdFire V4e object files.
1145 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1147 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1149 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1151 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1153 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1155 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1157 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1159 * i386.h (i386_optab): Added xstore/xcrypt insns.
1161 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1163 * h8300.h (32bit ldc/stc): Add relaxing support.
1165 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1167 * h8300.h (BITOP): Pass MEMRELAX flag.
1169 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1171 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1174 For older changes see ChangeLog-9103
1180 version-control: never