1 2013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
3 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
6 2013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
8 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
10 2013-06-17 Catherine Moore <clm@codesourcery.com>
11 Maciej W. Rozycki <macro@codesourcery.com>
12 Chao-Ying Fu <fu@mips.com>
14 * mips.h (OP_SH_EVAOFFSET): Define.
15 (OP_MASK_EVAOFFSET): Define.
16 (INSN_ASE_MASK): Delete.
18 (M_CACHEE_AB, M_CACHEE_OB): New.
19 (M_LBE_OB, M_LBE_AB): New.
20 (M_LBUE_OB, M_LBUE_AB): New.
21 (M_LHE_OB, M_LHE_AB): New.
22 (M_LHUE_OB, M_LHUE_AB): New.
23 (M_LLE_AB, M_LLE_OB): New.
24 (M_LWE_OB, M_LWE_AB): New.
25 (M_LWLE_AB, M_LWLE_OB): New.
26 (M_LWRE_AB, M_LWRE_OB): New.
27 (M_PREFE_AB, M_PREFE_OB): New.
28 (M_SCE_AB, M_SCE_OB): New.
29 (M_SBE_OB, M_SBE_AB): New.
30 (M_SHE_OB, M_SHE_AB): New.
31 (M_SWE_OB, M_SWE_AB): New.
32 (M_SWLE_AB, M_SWLE_OB): New.
33 (M_SWRE_AB, M_SWRE_OB): New.
34 (MICROMIPSOP_SH_EVAOFFSET): Define.
35 (MICROMIPSOP_MASK_EVAOFFSET): Define.
37 2013-06-12 Sandra Loosemore <sandra@codesourcery.com>
39 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
41 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
43 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
45 2013-05-09 Andrew Pinski <apinski@cavium.com>
47 * mips.h (OP_MASK_CODE10): Correct definition.
48 (OP_SH_CODE10): Likewise.
49 Add a comment that "+J" is used now for OP_*CODE10.
50 (INSN_ASE_MASK): Update.
51 (INSN_VIRT): New macro.
52 (INSN_VIRT64): New macro
54 2013-05-02 Nick Clifton <nickc@redhat.com>
56 * msp430.h: Add patterns for MSP430X instructions.
58 2013-04-06 David S. Miller <davem@davemloft.net>
60 * sparc.h (F_PREFERRED): Define.
61 (F_PREF_ALIAS): Define.
63 2013-04-03 Nick Clifton <nickc@redhat.com>
65 * v850.h (V850_INVERSE_PCREL): Define.
67 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
70 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
72 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
75 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
77 * tic6xc-opcode-table.h: Add 16-bit insns.
78 * tic6x.h: Add support for 16-bit insns.
80 2013-03-21 Michael Schewe <michael.schewe@gmx.net>
82 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
83 and mov.b/w/l Rs,@(d:32,ERd).
85 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
88 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
89 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
90 tic6x_operand_xregpair operand coding type.
91 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
92 opcode field, usu ORXREGD1324 for the src2 operand and remove the
95 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
98 * tic6x.h (enum tic6x_coding_method): Add
99 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
100 separately the msb and lsb of a register pair. This is needed to
101 encode the opcodes in the same way as TI assembler does.
102 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
103 and rsqrdp opcodes to use the new field coding types.
105 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
107 * arm.h (CRC_EXT_ARMV8): New constant.
108 (ARCH_CRC_ARMV8): New macro.
110 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
112 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
114 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
115 Andrew Jenner <andrew@codesourcery.com>
117 Based on patches from Altera Corporation.
121 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
123 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
125 2013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
128 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
130 2013-01-24 Nick Clifton <nickc@redhat.com>
132 * v850.h: Add e3v5 support.
134 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
136 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
138 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
140 * ppc.h (PPC_OPCODE_POWER8): New define.
141 (PPC_OPCODE_HTM): Likewise.
143 2013-01-10 Will Newton <will.newton@imgtec.com>
147 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
149 * cr16.h (make_instruction): Rename to cr16_make_instruction.
150 (match_opcode): Rename to cr16_match_opcode.
152 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
154 * mips.h: Add support for r5900 instructions including lq and sq.
156 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
158 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
159 (make_instruction,match_opcode): Added function prototypes.
160 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
162 2012-11-23 Alan Modra <amodra@gmail.com>
164 * ppc.h (ppc_parse_cpu): Update prototype.
166 2012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
168 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
169 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
171 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
173 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
175 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
177 * ia64.h (ia64_opnd): Add new operand types.
179 2012-08-21 David S. Miller <davem@davemloft.net>
181 * sparc.h (F3F4): New macro.
183 2012-08-13 Ian Bolton <ian.bolton@arm.com>
184 Laurent Desnogues <laurent.desnogues@arm.com>
185 Jim MacArthur <jim.macarthur@arm.com>
186 Marcus Shawcroft <marcus.shawcroft@arm.com>
187 Nigel Stephens <nigel.stephens@arm.com>
188 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
189 Richard Earnshaw <rearnsha@arm.com>
190 Sofiane Naci <sofiane.naci@arm.com>
191 Tejas Belagod <tejas.belagod@arm.com>
192 Yufeng Zhang <yufeng.zhang@arm.com>
194 * aarch64.h: New file.
196 2012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
197 Maciej W. Rozycki <macro@codesourcery.com>
199 * mips.h (mips_opcode): Add the exclusions field.
200 (OPCODE_IS_MEMBER): Remove macro.
201 (cpu_is_member): New inline function.
202 (opcode_is_member): Likewise.
204 2012-07-31 Chao-Ying Fu <fu@mips.com>
205 Catherine Moore <clm@codesourcery.com>
206 Maciej W. Rozycki <macro@codesourcery.com>
208 * mips.h: Document microMIPS DSP ASE usage.
209 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
210 microMIPS DSP ASE support.
211 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
212 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
213 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
214 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
215 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
216 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
217 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
219 2012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
221 * mips.h: Fix a typo in description.
223 2012-06-07 Georg-Johann Lay <avr@gjlay.de>
225 * avr.h: (AVR_ISA_XCH): New define.
226 (AVR_ISA_XMEGA): Use it.
227 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
229 2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
231 * m68hc11.h: Add XGate definitions.
232 (struct m68hc11_opcode): Add xg_mask field.
234 2012-05-14 Catherine Moore <clm@codesourcery.com>
235 Maciej W. Rozycki <macro@codesourcery.com>
236 Rhonda Wittels <rhonda@codesourcery.com>
238 * ppc.h (PPC_OPCODE_VLE): New definition.
239 (PPC_OP_SA): New macro.
240 (PPC_OP_SE_VLE): New macro.
241 (PPC_OP): Use a variable shift amount.
242 (powerpc_operand): Update comments.
243 (PPC_OPSHIFT_INV): New macro.
244 (PPC_OPERAND_CR): Replace with...
245 (PPC_OPERAND_CR_BIT): ...this and
246 (PPC_OPERAND_CR_REG): ...this.
249 2012-05-03 Sean Keys <skeys@ipdatasys.com>
251 * xgate.h: Header file for XGATE assembler.
253 2012-04-27 David S. Miller <davem@davemloft.net>
255 * sparc.h: Document new arg code' )' for crypto RS3
258 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
259 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
260 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
261 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
262 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
263 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
264 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
265 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
266 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
267 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
268 HWCAP_CBCOND, HWCAP_CRC32): New defines.
270 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
272 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
274 2012-02-27 Alan Modra <amodra@gmail.com>
276 * crx.h (cst4_map): Update declaration.
278 2012-02-25 Walter Lee <walt@tilera.com>
280 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
282 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
283 TILEPRO_OPC_LW_TLS_SN.
285 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
287 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
288 (XRELEASE_PREFIX_OPCODE): Likewise.
290 2011-12-08 Andrew Pinski <apinski@cavium.com>
291 Adam Nemet <anemet@caviumnetworks.com>
293 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
294 (INSN_OCTEON2): New macro.
295 (CPU_OCTEON2): New macro.
296 (OPCODE_IS_MEMBER): Add Octeon2.
298 2011-11-29 Andrew Pinski <apinski@cavium.com>
300 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
301 (INSN_OCTEONP): New macro.
302 (CPU_OCTEONP): New macro.
303 (OPCODE_IS_MEMBER): Add Octeon+.
304 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
306 2011-11-01 DJ Delorie <dj@redhat.com>
310 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
312 * mips.h: Fix a typo in description.
314 2011-09-21 David S. Miller <davem@davemloft.net>
316 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
317 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
318 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
319 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
321 2011-08-09 Chao-ying Fu <fu@mips.com>
322 Maciej W. Rozycki <macro@codesourcery.com>
324 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
325 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
326 (INSN_ASE_MASK): Add the MCU bit.
327 (INSN_MCU): New macro.
328 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
329 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
331 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
333 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
334 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
335 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
336 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
337 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
338 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
339 (INSN2_READ_GPR_MMN): Likewise.
340 (INSN2_READ_FPR_D): Change the bit used.
341 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
342 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
343 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
344 (INSN2_COND_BRANCH): Likewise.
345 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
346 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
347 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
348 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
349 (INSN2_MOD_GPR_MN): Likewise.
351 2011-08-05 David S. Miller <davem@davemloft.net>
353 * sparc.h: Document new format codes '4', '5', and '('.
354 (OPF_LOW4, RS3): New macros.
356 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
358 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
359 order of flags documented.
361 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
363 * mips.h: Clarify the description of microMIPS instruction
365 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
367 2011-07-24 Chao-ying Fu <fu@mips.com>
368 Maciej W. Rozycki <macro@codesourcery.com>
370 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
371 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
372 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
373 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
374 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
375 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
376 (OP_MASK_RS3, OP_SH_RS3): Likewise.
377 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
378 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
379 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
380 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
381 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
382 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
383 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
384 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
385 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
386 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
387 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
388 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
389 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
390 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
391 (INSN_WRITE_GPR_S): New macro.
392 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
393 (INSN2_READ_FPR_D): Likewise.
394 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
395 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
396 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
397 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
398 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
399 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
400 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
401 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
402 (CPU_MICROMIPS): New macro.
403 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
404 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
405 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
406 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
407 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
408 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
409 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
410 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
411 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
412 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
413 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
414 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
415 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
416 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
417 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
418 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
419 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
420 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
421 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
422 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
423 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
424 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
425 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
426 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
427 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
428 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
429 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
430 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
431 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
432 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
433 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
434 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
435 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
436 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
437 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
438 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
439 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
440 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
441 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
442 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
443 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
444 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
445 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
446 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
447 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
448 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
449 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
450 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
451 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
452 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
453 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
454 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
455 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
456 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
457 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
458 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
459 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
460 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
461 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
462 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
463 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
464 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
465 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
466 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
467 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
468 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
469 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
470 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
471 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
472 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
473 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
474 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
475 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
476 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
477 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
478 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
479 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
480 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
481 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
482 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
483 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
484 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
485 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
486 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
487 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
488 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
489 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
490 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
491 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
492 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
493 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
494 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
495 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
496 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
497 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
498 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
499 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
500 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
501 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
502 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
503 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
504 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
505 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
506 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
507 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
508 (micromips_opcodes): New declaration.
509 (bfd_micromips_num_opcodes): Likewise.
511 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
513 * mips.h (INSN_TRAP): Rename to...
514 (INSN_NO_DELAY_SLOT): ... this.
515 (INSN_SYNC): Remove macro.
517 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
519 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
520 a duplicate of AVR_ISA_SPM.
522 2011-07-01 Nick Clifton <nickc@redhat.com>
524 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
526 2011-06-18 Robin Getz <robin.getz@analog.com>
528 * bfin.h (is_macmod_signed): New func
530 2011-06-18 Mike Frysinger <vapier@gentoo.org>
532 * bfin.h (is_macmod_pmove): Add missing space before func args.
533 (is_macmod_hmove): Likewise.
535 2011-06-13 Walter Lee <walt@tilera.com>
537 * tilegx.h: New file.
538 * tilepro.h: New file.
540 2011-05-31 Paul Brook <paul@codesourcery.com>
542 * arm.h (ARM_ARCH_V7R_IDIV): Define.
544 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
546 * s390.h: Replace S390_OPERAND_REG_EVEN with
547 S390_OPERAND_REG_PAIR.
549 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
551 * s390.h: Add S390_OPCODE_REG_EVEN flag.
553 2011-04-18 Julian Brown <julian@codesourcery.com>
555 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
557 2011-04-11 Dan McDonald <dan@wellkeeper.com>
560 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
562 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
564 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
565 New instruction set flags.
566 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
568 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
570 * mips.h (M_PREF_AB): New enum value.
572 2011-02-12 Mike Frysinger <vapier@gentoo.org>
574 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
576 (is_macmod_pmove, is_macmod_hmove): New functions.
578 2011-02-11 Mike Frysinger <vapier@gentoo.org>
580 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
582 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
584 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
585 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
587 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
590 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
593 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
596 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
598 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
600 * mips.h: Update commentary after last commit.
602 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
604 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
605 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
606 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
608 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
610 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
612 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
614 * mips.h: Fix previous commit.
616 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
618 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
619 (INSN_LOONGSON_3A): Clear bit 31.
621 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
624 * arm.h (ARM_AEXT_V6M_ONLY): New define.
625 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
626 (ARM_ARCH_V6M_ONLY): New define.
628 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
630 * mips.h (INSN_LOONGSON_3A): Defined.
631 (CPU_LOONGSON_3A): Defined.
632 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
634 2010-10-09 Matt Rice <ratmice@gmail.com>
636 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
637 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
639 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
641 * arm.h (ARM_EXT_VIRT): New define.
642 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
643 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
646 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
648 * arm.h (ARM_AEXT_ADIV): New define.
649 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
651 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
653 * arm.h (ARM_EXT_OS): New define.
654 (ARM_AEXT_V6SM): Likewise.
655 (ARM_ARCH_V6SM): Likewise.
657 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
659 * arm.h (ARM_EXT_MP): Add.
660 (ARM_ARCH_V7A_MP): Likewise.
662 2010-09-22 Mike Frysinger <vapier@gentoo.org>
664 * bfin.h: Declare pseudoChr structs/defines.
666 2010-09-21 Mike Frysinger <vapier@gentoo.org>
668 * bfin.h: Strip trailing whitespace.
670 2010-07-29 DJ Delorie <dj@redhat.com>
672 * rx.h (RX_Operand_Type): Add TwoReg.
673 (RX_Opcode_ID): Remove ediv and ediv2.
675 2010-07-27 DJ Delorie <dj@redhat.com>
677 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
679 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
680 Ina Pandit <ina.pandit@kpitcummins.com>
682 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
683 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
684 PROCESSOR_V850E2_ALL.
685 Remove PROCESSOR_V850EA support.
686 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
687 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
688 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
689 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
690 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
691 V850_OPERAND_PERCENT.
692 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
694 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
697 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
699 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
700 (MIPS16_INSN_BRANCH): Rename to...
701 (MIPS16_INSN_COND_BRANCH): ... this.
703 2010-07-03 Alan Modra <amodra@gmail.com>
705 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
706 Renumber other PPC_OPCODE defines.
708 2010-07-03 Alan Modra <amodra@gmail.com>
710 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
712 2010-06-29 Alan Modra <amodra@gmail.com>
714 * maxq.h: Delete file.
716 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
718 * ppc.h (PPC_OPCODE_E500): Define.
720 2010-05-26 Catherine Moore <clm@codesourcery.com>
722 * opcode/mips.h (INSN_MIPS16): Remove.
724 2010-04-21 Joseph Myers <joseph@codesourcery.com>
726 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
728 2010-04-15 Nick Clifton <nickc@redhat.com>
730 * alpha.h: Update copyright notice to use GPLv3.
736 * convex.h: Likewise.
750 * m68hc11.h: Likewise.
756 * mn10200.h: Likewise.
757 * mn10300.h: Likewise.
758 * msp430.h: Likewise.
769 * score-datadep.h: Likewise.
770 * score-inst.h: Likewise.
772 * spu-insns.h: Likewise.
776 * tic54x.h: Likewise.
781 2010-03-25 Joseph Myers <joseph@codesourcery.com>
783 * tic6x-control-registers.h, tic6x-insn-formats.h,
784 tic6x-opcode-table.h, tic6x.h: New.
786 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
788 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
790 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
792 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
794 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
796 * ia64.h (ia64_find_opcode): Remove argument name.
797 (ia64_find_next_opcode): Likewise.
798 (ia64_dis_opcode): Likewise.
799 (ia64_free_opcode): Likewise.
800 (ia64_find_dependency): Likewise.
802 2009-11-22 Doug Evans <dje@sebabeach.org>
804 * cgen.h: Include bfd_stdint.h.
805 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
807 2009-11-18 Paul Brook <paul@codesourcery.com>
809 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
811 2009-11-17 Paul Brook <paul@codesourcery.com>
812 Daniel Jacobowitz <dan@codesourcery.com>
814 * arm.h (ARM_EXT_V6_DSP): Define.
815 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
816 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
818 2009-11-04 DJ Delorie <dj@redhat.com>
820 * rx.h (rx_decode_opcode) (mvtipl): Add.
821 (mvtcp, mvfcp, opecp): Remove.
823 2009-11-02 Paul Brook <paul@codesourcery.com>
825 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
826 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
827 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
828 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
829 FPU_ARCH_NEON_VFP_V4): Define.
831 2009-10-23 Doug Evans <dje@sebabeach.org>
833 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
834 * cgen.h: Update. Improve multi-inclusion macro name.
836 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
838 * ppc.h (PPC_OPCODE_476): Define.
840 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
842 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
844 2009-09-29 DJ Delorie <dj@redhat.com>
848 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
850 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
852 2009-09-21 Ben Elliston <bje@au.ibm.com>
854 * ppc.h (PPC_OPCODE_PPCA2): New.
856 2009-09-05 Martin Thuresson <martin@mtme.org>
858 * ia64.h (struct ia64_operand): Renamed member class to op_class.
860 2009-08-29 Martin Thuresson <martin@mtme.org>
862 * tic30.h (template): Rename type template to
863 insn_template. Updated code to use new name.
864 * tic54x.h (template): Rename type template to
867 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
869 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
871 2009-06-11 Anthony Green <green@moxielogic.com>
873 * moxie.h (MOXIE_F3_PCREL): Define.
874 (moxie_form3_opc_info): Grow.
876 2009-06-06 Anthony Green <green@moxielogic.com>
878 * moxie.h (MOXIE_F1_M): Define.
880 2009-04-15 Anthony Green <green@moxielogic.com>
884 2009-04-06 DJ Delorie <dj@redhat.com>
886 * h8300.h: Add relaxation attributes to MOVA opcodes.
888 2009-03-10 Alan Modra <amodra@bigpond.net.au>
890 * ppc.h (ppc_parse_cpu): Declare.
892 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
894 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
895 and _IMM11 for mbitclr and mbitset.
896 * score-datadep.h: Update dependency information.
898 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
900 * ppc.h (PPC_OPCODE_POWER7): New.
902 2009-02-06 Doug Evans <dje@google.com>
904 * i386.h: Add comment regarding sse* insns and prefixes.
906 2009-02-03 Sandip Matte <sandip@rmicorp.com>
908 * mips.h (INSN_XLR): Define.
909 (INSN_CHIP_MASK): Update.
911 (OPCODE_IS_MEMBER): Update.
912 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
914 2009-01-28 Doug Evans <dje@google.com>
916 * opcode/i386.h: Add multiple inclusion protection.
917 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
918 (EDI_REG_NUM): New macros.
919 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
920 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
921 (REX_PREFIX_P): New macro.
923 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
925 * ppc.h (struct powerpc_opcode): New field "deprecated".
926 (PPC_OPCODE_NOPOWER4): Delete.
928 2008-11-28 Joshua Kinard <kumba@gentoo.org>
930 * mips.h: Define CPU_R14000, CPU_R16000.
931 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
933 2008-11-18 Catherine Moore <clm@codesourcery.com>
935 * arm.h (FPU_NEON_FP16): New.
936 (FPU_ARCH_NEON_FP16): New.
938 2008-11-06 Chao-ying Fu <fu@mips.com>
940 * mips.h: Doucument '1' for 5-bit sync type.
942 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
944 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
947 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
949 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
951 2008-07-30 Michael J. Eager <eager@eagercon.com>
953 * ppc.h (PPC_OPCODE_405): Define.
954 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
956 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
958 * ppc.h (ppc_cpu_t): New typedef.
959 (struct powerpc_opcode <flags>): Use it.
960 (struct powerpc_operand <insert, extract>): Likewise.
961 (struct powerpc_macro <flags>): Likewise.
963 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
965 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
966 Update comment before MIPS16 field descriptors to mention MIPS16.
967 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
969 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
970 New bit masks and shift counts for cins and exts.
972 * mips.h: Document new field descriptors +Q.
973 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
975 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
977 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
978 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
980 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
982 * ppc.h: (PPC_OPCODE_E500MC): New.
984 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
986 * i386.h (MAX_OPERANDS): Set to 5.
987 (MAX_MNEM_SIZE): Changed to 20.
989 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
991 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
993 2008-03-09 Paul Brook <paul@codesourcery.com>
995 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
997 2008-03-04 Paul Brook <paul@codesourcery.com>
999 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1000 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1001 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1003 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
1004 Nick Clifton <nickc@redhat.com>
1007 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1008 with a 32-bit displacement but without the top bit of the 4th byte
1011 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1013 * cr16.h (cr16_num_optab): Declared.
1015 2008-02-14 Hakan Ardo <hakan@debian.org>
1018 * avr.h (AVR_ISA_2xxe): Define.
1020 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1022 * mips.h: Update copyright.
1023 (INSN_CHIP_MASK): New macro.
1024 (INSN_OCTEON): New macro.
1025 (CPU_OCTEON): New macro.
1026 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1028 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1030 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1032 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1034 * avr.h (AVR_ISA_USB162): Add new opcode set.
1035 (AVR_ISA_AVR3): Likewise.
1037 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1039 * mips.h (INSN_LOONGSON_2E): New.
1040 (INSN_LOONGSON_2F): New.
1041 (CPU_LOONGSON_2E): New.
1042 (CPU_LOONGSON_2F): New.
1043 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1045 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1047 * mips.h (INSN_ISA*): Redefine certain values as an
1048 enumeration. Update comments.
1049 (mips_isa_table): New.
1050 (ISA_MIPS*): Redefine to match enumeration.
1051 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1054 2007-08-08 Ben Elliston <bje@au.ibm.com>
1056 * ppc.h (PPC_OPCODE_PPCPS): New.
1058 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1060 * m68k.h: Document j K & E.
1062 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1064 * cr16.h: New file for CR16 target.
1066 2007-05-02 Alan Modra <amodra@bigpond.net.au>
1068 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1070 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1072 * m68k.h (mcfisa_c): New.
1073 (mcfusp, mcf_mask): Adjust.
1075 2007-04-20 Alan Modra <amodra@bigpond.net.au>
1077 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1078 (num_powerpc_operands): Declare.
1079 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1080 (PPC_OPERAND_PLUS1): Define.
1082 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
1084 * i386.h (REX_MODE64): Renamed to ...
1086 (REX_EXTX): Renamed to ...
1088 (REX_EXTY): Renamed to ...
1090 (REX_EXTZ): Renamed to ...
1093 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1095 * i386.h: Add entries from config/tc-i386.h and move tables
1096 to opcodes/i386-opc.h.
1098 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1100 * i386.h (FloatDR): Removed.
1101 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1103 2007-03-01 Alan Modra <amodra@bigpond.net.au>
1105 * spu-insns.h: Add soma double-float insns.
1107 2007-02-20 Thiemo Seufer <ths@mips.com>
1108 Chao-Ying Fu <fu@mips.com>
1110 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1111 (INSN_DSPR2): Add flag for DSP R2 instructions.
1112 (M_BALIGN): New macro.
1114 2007-02-14 Alan Modra <amodra@bigpond.net.au>
1116 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1117 and Seg3ShortFrom with Shortform.
1119 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1122 * i386.h (i386_optab): Put the real "test" before the pseudo
1125 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
1127 * m68k.h (m68010up): OR fido_a.
1129 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
1131 * m68k.h (fido_a): New.
1133 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
1135 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1136 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1139 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1141 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1143 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1145 * score-inst.h (enum score_insn_type): Add Insn_internal.
1147 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1148 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1149 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1150 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1151 Alan Modra <amodra@bigpond.net.au>
1153 * spu-insns.h: New file.
1156 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1158 * ppc.h (PPC_OPCODE_CELL): Define.
1160 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1162 * i386.h : Modify opcode to support for the change in POPCNT opcode
1163 in amdfam10 architecture.
1165 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1167 * i386.h: Replace CpuMNI with CpuSSSE3.
1169 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
1170 Joseph Myers <joseph@codesourcery.com>
1171 Ian Lance Taylor <ian@wasabisystems.com>
1172 Ben Elliston <bje@wasabisystems.com>
1174 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1176 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1178 * score-datadep.h: New file.
1179 * score-inst.h: New file.
1181 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1183 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1184 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1185 movdq2q and movq2dq.
1187 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1188 Michael Meissner <michael.meissner@amd.com>
1190 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1192 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1194 * i386.h (i386_optab): Add "nop" with memory reference.
1196 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1198 * i386.h (i386_optab): Update comment for 64bit NOP.
1200 2006-06-06 Ben Elliston <bje@au.ibm.com>
1201 Anton Blanchard <anton@samba.org>
1203 * ppc.h (PPC_OPCODE_POWER6): Define.
1206 2006-06-05 Thiemo Seufer <ths@mips.com>
1208 * mips.h: Improve description of MT flags.
1210 2006-05-25 Richard Sandiford <richard@codesourcery.com>
1212 * m68k.h (mcf_mask): Define.
1214 2006-05-05 Thiemo Seufer <ths@mips.com>
1215 David Ung <davidu@mips.com>
1217 * mips.h (enum): Add macro M_CACHE_AB.
1219 2006-05-04 Thiemo Seufer <ths@mips.com>
1220 Nigel Stephens <nigel@mips.com>
1221 David Ung <davidu@mips.com>
1223 * mips.h: Add INSN_SMARTMIPS define.
1225 2006-04-30 Thiemo Seufer <ths@mips.com>
1226 David Ung <davidu@mips.com>
1228 * mips.h: Defines udi bits and masks. Add description of
1229 characters which may appear in the args field of udi
1232 2006-04-26 Thiemo Seufer <ths@networkno.de>
1234 * mips.h: Improve comments describing the bitfield instruction
1237 2006-04-26 Julian Brown <julian@codesourcery.com>
1239 * arm.h (FPU_VFP_EXT_V3): Define constant.
1240 (FPU_NEON_EXT_V1): Likewise.
1241 (FPU_VFP_HARD): Update.
1242 (FPU_VFP_V3): Define macro.
1243 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1245 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
1247 * avr.h (AVR_ISA_PWMx): New.
1249 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1251 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1252 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1253 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1254 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1255 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1257 2006-03-10 Paul Brook <paul@codesourcery.com>
1259 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1261 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1263 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1264 first. Correct mask of bb "B" opcode.
1266 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1268 * i386.h (i386_optab): Support Intel Merom New Instructions.
1270 2006-02-24 Paul Brook <paul@codesourcery.com>
1272 * arm.h: Add V7 feature bits.
1274 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1276 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1278 2006-01-31 Paul Brook <paul@codesourcery.com>
1279 Richard Earnshaw <rearnsha@arm.com>
1281 * arm.h: Use ARM_CPU_FEATURE.
1282 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1283 (arm_feature_set): Change to a structure.
1284 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1285 ARM_FEATURE): New macros.
1287 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
1289 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1290 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1291 (ADD_PC_INCR_OPCODE): Don't define.
1293 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1296 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1298 2005-11-14 David Ung <davidu@mips.com>
1300 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1301 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1302 save/restore encoding of the args field.
1304 2005-10-28 Dave Brolley <brolley@redhat.com>
1306 Contribute the following changes:
1307 2005-02-16 Dave Brolley <brolley@redhat.com>
1309 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1310 cgen_isa_mask_* to cgen_bitset_*.
1313 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1315 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1316 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1317 (CGEN_CPU_TABLE): Make isas a ponter.
1319 2003-09-29 Dave Brolley <brolley@redhat.com>
1321 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1322 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1323 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1325 2002-12-13 Dave Brolley <brolley@redhat.com>
1327 * cgen.h (symcat.h): #include it.
1328 (cgen-bitset.h): #include it.
1329 (CGEN_ATTR_VALUE_TYPE): Now a union.
1330 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1331 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1332 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1333 * cgen-bitset.h: New file.
1335 2005-09-30 Catherine Moore <clm@cm00re.com>
1339 2005-10-24 Jan Beulich <jbeulich@novell.com>
1341 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1344 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1346 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1347 Add FLAG_STRICT to pa10 ftest opcode.
1349 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1351 * hppa.h (pa_opcodes): Remove lha entries.
1353 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1355 * hppa.h (FLAG_STRICT): Revise comment.
1356 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1357 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1360 2005-09-30 Catherine Moore <clm@cm00re.com>
1364 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1366 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1368 2005-09-06 Chao-ying Fu <fu@mips.com>
1370 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1371 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1373 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1374 (INSN_ASE_MASK): Update to include INSN_MT.
1375 (INSN_MT): New define for MT ASE.
1377 2005-08-25 Chao-ying Fu <fu@mips.com>
1379 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1380 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1381 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1382 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1383 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1384 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1386 (INSN_DSP): New define for DSP ASE.
1388 2005-08-18 Alan Modra <amodra@bigpond.net.au>
1392 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1394 * ppc.h (PPC_OPCODE_E300): Define.
1396 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1398 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1400 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1403 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1406 2005-07-27 Jan Beulich <jbeulich@novell.com>
1408 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1409 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1410 Add movq-s as 64-bit variants of movd-s.
1412 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1414 * hppa.h: Fix punctuation in comment.
1416 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1417 implicit space-register addressing. Set space-register bits on opcodes
1418 using implicit space-register addressing. Add various missing pa20
1419 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1420 space-register addressing. Use "fE" instead of "fe" in various
1423 2005-07-18 Jan Beulich <jbeulich@novell.com>
1425 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1427 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1429 * i386.h (i386_optab): Support Intel VMX Instructions.
1431 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1433 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1435 2005-07-05 Jan Beulich <jbeulich@novell.com>
1437 * i386.h (i386_optab): Add new insns.
1439 2005-07-01 Nick Clifton <nickc@redhat.com>
1441 * sparc.h: Add typedefs to structure declarations.
1443 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1446 * i386.h (i386_optab): Update comments for 64bit addressing on
1447 mov. Allow 64bit addressing for mov and movq.
1449 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1451 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1452 respectively, in various floating-point load and store patterns.
1454 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1456 * hppa.h (FLAG_STRICT): Correct comment.
1457 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1458 PA 2.0 mneumonics when equivalent. Entries with cache control
1459 completers now require PA 1.1. Adjust whitespace.
1461 2005-05-19 Anton Blanchard <anton@samba.org>
1463 * ppc.h (PPC_OPCODE_POWER5): Define.
1465 2005-05-10 Nick Clifton <nickc@redhat.com>
1467 * Update the address and phone number of the FSF organization in
1468 the GPL notices in the following files:
1469 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1470 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1471 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1472 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1473 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1474 tic54x.h, tic80.h, v850.h, vax.h
1476 2005-05-09 Jan Beulich <jbeulich@novell.com>
1478 * i386.h (i386_optab): Add ht and hnt.
1480 2005-04-18 Mark Kettenis <kettenis@gnu.org>
1482 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1483 Add xcrypt-ctr. Provide aliases without hyphens.
1485 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1487 Moved from ../ChangeLog
1489 2005-04-12 Paul Brook <paul@codesourcery.com>
1490 * m88k.h: Rename psr macros to avoid conflicts.
1492 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1493 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1494 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1495 and ARM_ARCH_V6ZKT2.
1497 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1498 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1499 Remove redundant instruction types.
1500 (struct argument): X_op - new field.
1501 (struct cst4_entry): Remove.
1502 (no_op_insn): Declare.
1504 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1505 * crx.h (enum argtype): Rename types, remove unused types.
1507 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1508 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1509 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1510 (enum operand_type): Rearrange operands, edit comments.
1511 replace us<N> with ui<N> for unsigned immediate.
1512 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1513 displacements (respectively).
1514 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1515 (instruction type): Add NO_TYPE_INS.
1516 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1517 (operand_entry): New field - 'flags'.
1518 (operand flags): New.
1520 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1521 * crx.h (operand_type): Remove redundant types i3, i4,
1523 Add new unsigned immediate types us3, us4, us5, us16.
1525 2005-04-12 Mark Kettenis <kettenis@gnu.org>
1527 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1528 adjust them accordingly.
1530 2005-04-01 Jan Beulich <jbeulich@novell.com>
1532 * i386.h (i386_optab): Add rdtscp.
1534 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1536 * i386.h (i386_optab): Don't allow the `l' suffix for moving
1537 between memory and segment register. Allow movq for moving between
1538 general-purpose register and segment register.
1540 2005-02-09 Jan Beulich <jbeulich@novell.com>
1543 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1544 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1547 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1549 * m68k.h (m68008, m68ec030, m68882): Remove.
1551 (cpu_m68k, cpu_cf): New.
1552 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1553 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1555 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
1557 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1558 * cgen.h (enum cgen_parse_operand_type): Add
1559 CGEN_PARSE_OPERAND_SYMBOLIC.
1561 2005-01-21 Fred Fish <fnf@specifixinc.com>
1563 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1564 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1565 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1567 2005-01-19 Fred Fish <fnf@specifixinc.com>
1569 * mips.h (struct mips_opcode): Add new pinfo2 member.
1570 (INSN_ALIAS): New define for opcode table entries that are
1571 specific instances of another entry, such as 'move' for an 'or'
1572 with a zero operand.
1573 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1574 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1576 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1578 * mips.h (CPU_RM9000): Define.
1579 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1581 2004-11-25 Jan Beulich <jbeulich@novell.com>
1583 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1584 to/from test registers are illegal in 64-bit mode. Add missing
1585 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1586 (previously one had to explicitly encode a rex64 prefix). Re-enable
1587 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1588 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1590 2004-11-23 Jan Beulich <jbeulich@novell.com>
1592 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1593 available only with SSE2. Change the MMX additions introduced by SSE
1594 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1595 instructions by their now designated identifier (since combining i686
1596 and 3DNow! does not really imply 3DNow!A).
1598 2004-11-19 Alan Modra <amodra@bigpond.net.au>
1600 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1601 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1603 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1604 Vineet Sharma <vineets@noida.hcltech.com>
1606 * maxq.h: New file: Disassembly information for the maxq port.
1608 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1610 * i386.h (i386_optab): Put back "movzb".
1612 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
1614 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1615 comments. Remove member cris_ver_sim. Add members
1616 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1617 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1618 (struct cris_support_reg, struct cris_cond15): New types.
1619 (cris_conds15): Declare.
1620 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1621 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1622 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1623 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1624 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1625 SIZE_FIELD_UNSIGNED.
1627 2004-11-04 Jan Beulich <jbeulich@novell.com>
1629 * i386.h (sldx_Suf): Remove.
1630 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1631 (q_FP): Define, implying no REX64.
1632 (x_FP, sl_FP): Imply FloatMF.
1633 (i386_optab): Split reg and mem forms of moving from segment registers
1634 so that the memory forms can ignore the 16-/32-bit operand size
1635 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1636 all non-floating-point instructions. Unite 32- and 64-bit forms of
1637 movsx, movzx, and movd. Adjust floating point operations for the above
1638 changes to the *FP macros. Add DefaultSize to floating point control
1639 insns operating on larger memory ranges. Remove left over comments
1640 hinting at certain insns being Intel-syntax ones where the ones
1641 actually meant are already gone.
1643 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1645 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1648 2004-09-30 Paul Brook <paul@codesourcery.com>
1650 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1651 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1653 2004-09-11 Theodore A. Roth <troth@openavr.org>
1655 * avr.h: Add support for
1656 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1658 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1660 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1662 2004-08-24 Dmitry Diky <diwil@spec.ru>
1664 * msp430.h (msp430_opc): Add new instructions.
1665 (msp430_rcodes): Declare new instructions.
1666 (msp430_hcodes): Likewise..
1668 2004-08-13 Nick Clifton <nickc@redhat.com>
1671 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1674 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1676 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1678 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1680 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1682 2004-07-21 Jan Beulich <jbeulich@novell.com>
1684 * i386.h: Adjust instruction descriptions to better match the
1687 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
1689 * arm.h: Remove all old content. Replace with architecture defines
1690 from gas/config/tc-arm.c.
1692 2004-07-09 Andreas Schwab <schwab@suse.de>
1694 * m68k.h: Fix comment.
1696 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1700 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1702 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1704 2004-05-24 Peter Barada <peter@the-baradas.com>
1706 * m68k.h: Add 'size' to m68k_opcode.
1708 2004-05-05 Peter Barada <peter@the-baradas.com>
1710 * m68k.h: Switch from ColdFire chip name to core variant.
1712 2004-04-22 Peter Barada <peter@the-baradas.com>
1714 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1715 descriptions for new EMAC cases.
1716 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1717 handle Motorola MAC syntax.
1718 Allow disassembly of ColdFire V4e object files.
1720 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1722 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1724 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1726 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1728 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1730 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1732 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1734 * i386.h (i386_optab): Added xstore/xcrypt insns.
1736 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1738 * h8300.h (32bit ldc/stc): Add relaxing support.
1740 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1742 * h8300.h (BITOP): Pass MEMRELAX flag.
1744 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1746 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1749 For older changes see ChangeLog-9103
1751 Copyright (C) 2004-2012 Free Software Foundation, Inc.
1753 Copying and distribution of this file, with or without modification,
1754 are permitted in any medium without royalty provided the copyright
1755 notice and this notice are preserved.
1761 version-control: never