1 2012-11-23 Alan Modra <amodra@gmail.com>
3 * ppc.h (ppc_parse_cpu): Update prototype.
5 2012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
7 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
8 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
10 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
12 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
14 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
16 * ia64.h (ia64_opnd): Add new operand types.
18 2012-08-21 David S. Miller <davem@davemloft.net>
20 * sparc.h (F3F4): New macro.
22 2012-08-13 Ian Bolton <ian.bolton@arm.com>
23 Laurent Desnogues <laurent.desnogues@arm.com>
24 Jim MacArthur <jim.macarthur@arm.com>
25 Marcus Shawcroft <marcus.shawcroft@arm.com>
26 Nigel Stephens <nigel.stephens@arm.com>
27 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
28 Richard Earnshaw <rearnsha@arm.com>
29 Sofiane Naci <sofiane.naci@arm.com>
30 Tejas Belagod <tejas.belagod@arm.com>
31 Yufeng Zhang <yufeng.zhang@arm.com>
33 * aarch64.h: New file.
35 2012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
36 Maciej W. Rozycki <macro@codesourcery.com>
38 * mips.h (mips_opcode): Add the exclusions field.
39 (OPCODE_IS_MEMBER): Remove macro.
40 (cpu_is_member): New inline function.
41 (opcode_is_member): Likewise.
43 2012-07-31 Chao-Ying Fu <fu@mips.com>
44 Catherine Moore <clm@codesourcery.com>
45 Maciej W. Rozycki <macro@codesourcery.com>
47 * mips.h: Document microMIPS DSP ASE usage.
48 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
49 microMIPS DSP ASE support.
50 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
51 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
52 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
53 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
54 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
55 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
56 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
58 2012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
60 * mips.h: Fix a typo in description.
62 2012-06-07 Georg-Johann Lay <avr@gjlay.de>
64 * avr.h: (AVR_ISA_XCH): New define.
65 (AVR_ISA_XMEGA): Use it.
66 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
68 2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
70 * m68hc11.h: Add XGate definitions.
71 (struct m68hc11_opcode): Add xg_mask field.
73 2012-05-14 Catherine Moore <clm@codesourcery.com>
74 Maciej W. Rozycki <macro@codesourcery.com>
75 Rhonda Wittels <rhonda@codesourcery.com>
77 * ppc.h (PPC_OPCODE_VLE): New definition.
78 (PPC_OP_SA): New macro.
79 (PPC_OP_SE_VLE): New macro.
80 (PPC_OP): Use a variable shift amount.
81 (powerpc_operand): Update comments.
82 (PPC_OPSHIFT_INV): New macro.
83 (PPC_OPERAND_CR): Replace with...
84 (PPC_OPERAND_CR_BIT): ...this and
85 (PPC_OPERAND_CR_REG): ...this.
88 2012-05-03 Sean Keys <skeys@ipdatasys.com>
90 * xgate.h: Header file for XGATE assembler.
92 2012-04-27 David S. Miller <davem@davemloft.net>
94 * sparc.h: Document new arg code' )' for crypto RS3
97 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
98 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
99 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
100 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
101 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
102 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
103 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
104 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
105 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
106 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
107 HWCAP_CBCOND, HWCAP_CRC32): New defines.
109 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
111 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
113 2012-02-27 Alan Modra <amodra@gmail.com>
115 * crx.h (cst4_map): Update declaration.
117 2012-02-25 Walter Lee <walt@tilera.com>
119 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
121 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
122 TILEPRO_OPC_LW_TLS_SN.
124 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
126 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
127 (XRELEASE_PREFIX_OPCODE): Likewise.
129 2011-12-08 Andrew Pinski <apinski@cavium.com>
130 Adam Nemet <anemet@caviumnetworks.com>
132 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
133 (INSN_OCTEON2): New macro.
134 (CPU_OCTEON2): New macro.
135 (OPCODE_IS_MEMBER): Add Octeon2.
137 2011-11-29 Andrew Pinski <apinski@cavium.com>
139 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
140 (INSN_OCTEONP): New macro.
141 (CPU_OCTEONP): New macro.
142 (OPCODE_IS_MEMBER): Add Octeon+.
143 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
145 2011-11-01 DJ Delorie <dj@redhat.com>
149 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
151 * mips.h: Fix a typo in description.
153 2011-09-21 David S. Miller <davem@davemloft.net>
155 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
156 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
157 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
158 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
160 2011-08-09 Chao-ying Fu <fu@mips.com>
161 Maciej W. Rozycki <macro@codesourcery.com>
163 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
164 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
165 (INSN_ASE_MASK): Add the MCU bit.
166 (INSN_MCU): New macro.
167 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
168 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
170 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
172 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
173 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
174 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
175 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
176 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
177 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
178 (INSN2_READ_GPR_MMN): Likewise.
179 (INSN2_READ_FPR_D): Change the bit used.
180 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
181 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
182 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
183 (INSN2_COND_BRANCH): Likewise.
184 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
185 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
186 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
187 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
188 (INSN2_MOD_GPR_MN): Likewise.
190 2011-08-05 David S. Miller <davem@davemloft.net>
192 * sparc.h: Document new format codes '4', '5', and '('.
193 (OPF_LOW4, RS3): New macros.
195 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
197 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
198 order of flags documented.
200 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
202 * mips.h: Clarify the description of microMIPS instruction
204 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
206 2011-07-24 Chao-ying Fu <fu@mips.com>
207 Maciej W. Rozycki <macro@codesourcery.com>
209 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
210 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
211 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
212 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
213 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
214 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
215 (OP_MASK_RS3, OP_SH_RS3): Likewise.
216 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
217 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
218 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
219 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
220 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
221 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
222 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
223 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
224 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
225 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
226 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
227 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
228 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
229 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
230 (INSN_WRITE_GPR_S): New macro.
231 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
232 (INSN2_READ_FPR_D): Likewise.
233 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
234 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
235 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
236 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
237 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
238 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
239 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
240 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
241 (CPU_MICROMIPS): New macro.
242 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
243 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
244 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
245 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
246 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
247 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
248 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
249 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
250 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
251 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
252 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
253 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
254 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
255 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
256 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
257 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
258 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
259 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
260 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
261 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
262 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
263 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
264 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
265 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
266 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
267 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
268 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
269 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
270 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
271 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
272 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
273 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
274 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
275 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
276 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
277 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
278 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
279 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
280 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
281 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
282 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
283 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
284 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
285 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
286 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
287 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
288 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
289 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
290 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
291 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
292 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
293 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
294 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
295 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
296 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
297 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
298 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
299 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
300 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
301 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
302 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
303 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
304 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
305 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
306 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
307 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
308 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
309 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
310 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
311 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
312 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
313 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
314 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
315 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
316 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
317 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
318 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
319 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
320 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
321 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
322 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
323 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
324 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
325 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
326 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
327 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
328 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
329 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
330 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
331 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
332 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
333 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
334 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
335 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
336 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
337 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
338 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
339 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
340 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
341 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
342 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
343 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
344 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
345 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
346 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
347 (micromips_opcodes): New declaration.
348 (bfd_micromips_num_opcodes): Likewise.
350 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
352 * mips.h (INSN_TRAP): Rename to...
353 (INSN_NO_DELAY_SLOT): ... this.
354 (INSN_SYNC): Remove macro.
356 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
358 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
359 a duplicate of AVR_ISA_SPM.
361 2011-07-01 Nick Clifton <nickc@redhat.com>
363 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
365 2011-06-18 Robin Getz <robin.getz@analog.com>
367 * bfin.h (is_macmod_signed): New func
369 2011-06-18 Mike Frysinger <vapier@gentoo.org>
371 * bfin.h (is_macmod_pmove): Add missing space before func args.
372 (is_macmod_hmove): Likewise.
374 2011-06-13 Walter Lee <walt@tilera.com>
376 * tilegx.h: New file.
377 * tilepro.h: New file.
379 2011-05-31 Paul Brook <paul@codesourcery.com>
381 * arm.h (ARM_ARCH_V7R_IDIV): Define.
383 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
385 * s390.h: Replace S390_OPERAND_REG_EVEN with
386 S390_OPERAND_REG_PAIR.
388 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
390 * s390.h: Add S390_OPCODE_REG_EVEN flag.
392 2011-04-18 Julian Brown <julian@codesourcery.com>
394 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
396 2011-04-11 Dan McDonald <dan@wellkeeper.com>
399 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
401 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
403 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
404 New instruction set flags.
405 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
407 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
409 * mips.h (M_PREF_AB): New enum value.
411 2011-02-12 Mike Frysinger <vapier@gentoo.org>
413 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
415 (is_macmod_pmove, is_macmod_hmove): New functions.
417 2011-02-11 Mike Frysinger <vapier@gentoo.org>
419 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
421 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
423 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
424 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
426 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
429 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
432 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
435 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
437 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
439 * mips.h: Update commentary after last commit.
441 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
443 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
444 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
445 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
447 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
449 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
451 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
453 * mips.h: Fix previous commit.
455 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
457 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
458 (INSN_LOONGSON_3A): Clear bit 31.
460 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
463 * arm.h (ARM_AEXT_V6M_ONLY): New define.
464 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
465 (ARM_ARCH_V6M_ONLY): New define.
467 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
469 * mips.h (INSN_LOONGSON_3A): Defined.
470 (CPU_LOONGSON_3A): Defined.
471 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
473 2010-10-09 Matt Rice <ratmice@gmail.com>
475 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
476 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
478 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
480 * arm.h (ARM_EXT_VIRT): New define.
481 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
482 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
485 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
487 * arm.h (ARM_AEXT_ADIV): New define.
488 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
490 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
492 * arm.h (ARM_EXT_OS): New define.
493 (ARM_AEXT_V6SM): Likewise.
494 (ARM_ARCH_V6SM): Likewise.
496 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
498 * arm.h (ARM_EXT_MP): Add.
499 (ARM_ARCH_V7A_MP): Likewise.
501 2010-09-22 Mike Frysinger <vapier@gentoo.org>
503 * bfin.h: Declare pseudoChr structs/defines.
505 2010-09-21 Mike Frysinger <vapier@gentoo.org>
507 * bfin.h: Strip trailing whitespace.
509 2010-07-29 DJ Delorie <dj@redhat.com>
511 * rx.h (RX_Operand_Type): Add TwoReg.
512 (RX_Opcode_ID): Remove ediv and ediv2.
514 2010-07-27 DJ Delorie <dj@redhat.com>
516 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
518 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
519 Ina Pandit <ina.pandit@kpitcummins.com>
521 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
522 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
523 PROCESSOR_V850E2_ALL.
524 Remove PROCESSOR_V850EA support.
525 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
526 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
527 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
528 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
529 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
530 V850_OPERAND_PERCENT.
531 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
533 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
536 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
538 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
539 (MIPS16_INSN_BRANCH): Rename to...
540 (MIPS16_INSN_COND_BRANCH): ... this.
542 2010-07-03 Alan Modra <amodra@gmail.com>
544 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
545 Renumber other PPC_OPCODE defines.
547 2010-07-03 Alan Modra <amodra@gmail.com>
549 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
551 2010-06-29 Alan Modra <amodra@gmail.com>
553 * maxq.h: Delete file.
555 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
557 * ppc.h (PPC_OPCODE_E500): Define.
559 2010-05-26 Catherine Moore <clm@codesourcery.com>
561 * opcode/mips.h (INSN_MIPS16): Remove.
563 2010-04-21 Joseph Myers <joseph@codesourcery.com>
565 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
567 2010-04-15 Nick Clifton <nickc@redhat.com>
569 * alpha.h: Update copyright notice to use GPLv3.
575 * convex.h: Likewise.
589 * m68hc11.h: Likewise.
595 * mn10200.h: Likewise.
596 * mn10300.h: Likewise.
597 * msp430.h: Likewise.
608 * score-datadep.h: Likewise.
609 * score-inst.h: Likewise.
611 * spu-insns.h: Likewise.
615 * tic54x.h: Likewise.
620 2010-03-25 Joseph Myers <joseph@codesourcery.com>
622 * tic6x-control-registers.h, tic6x-insn-formats.h,
623 tic6x-opcode-table.h, tic6x.h: New.
625 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
627 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
629 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
631 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
633 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
635 * ia64.h (ia64_find_opcode): Remove argument name.
636 (ia64_find_next_opcode): Likewise.
637 (ia64_dis_opcode): Likewise.
638 (ia64_free_opcode): Likewise.
639 (ia64_find_dependency): Likewise.
641 2009-11-22 Doug Evans <dje@sebabeach.org>
643 * cgen.h: Include bfd_stdint.h.
644 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
646 2009-11-18 Paul Brook <paul@codesourcery.com>
648 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
650 2009-11-17 Paul Brook <paul@codesourcery.com>
651 Daniel Jacobowitz <dan@codesourcery.com>
653 * arm.h (ARM_EXT_V6_DSP): Define.
654 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
655 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
657 2009-11-04 DJ Delorie <dj@redhat.com>
659 * rx.h (rx_decode_opcode) (mvtipl): Add.
660 (mvtcp, mvfcp, opecp): Remove.
662 2009-11-02 Paul Brook <paul@codesourcery.com>
664 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
665 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
666 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
667 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
668 FPU_ARCH_NEON_VFP_V4): Define.
670 2009-10-23 Doug Evans <dje@sebabeach.org>
672 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
673 * cgen.h: Update. Improve multi-inclusion macro name.
675 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
677 * ppc.h (PPC_OPCODE_476): Define.
679 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
681 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
683 2009-09-29 DJ Delorie <dj@redhat.com>
687 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
689 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
691 2009-09-21 Ben Elliston <bje@au.ibm.com>
693 * ppc.h (PPC_OPCODE_PPCA2): New.
695 2009-09-05 Martin Thuresson <martin@mtme.org>
697 * ia64.h (struct ia64_operand): Renamed member class to op_class.
699 2009-08-29 Martin Thuresson <martin@mtme.org>
701 * tic30.h (template): Rename type template to
702 insn_template. Updated code to use new name.
703 * tic54x.h (template): Rename type template to
706 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
708 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
710 2009-06-11 Anthony Green <green@moxielogic.com>
712 * moxie.h (MOXIE_F3_PCREL): Define.
713 (moxie_form3_opc_info): Grow.
715 2009-06-06 Anthony Green <green@moxielogic.com>
717 * moxie.h (MOXIE_F1_M): Define.
719 2009-04-15 Anthony Green <green@moxielogic.com>
723 2009-04-06 DJ Delorie <dj@redhat.com>
725 * h8300.h: Add relaxation attributes to MOVA opcodes.
727 2009-03-10 Alan Modra <amodra@bigpond.net.au>
729 * ppc.h (ppc_parse_cpu): Declare.
731 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
733 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
734 and _IMM11 for mbitclr and mbitset.
735 * score-datadep.h: Update dependency information.
737 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
739 * ppc.h (PPC_OPCODE_POWER7): New.
741 2009-02-06 Doug Evans <dje@google.com>
743 * i386.h: Add comment regarding sse* insns and prefixes.
745 2009-02-03 Sandip Matte <sandip@rmicorp.com>
747 * mips.h (INSN_XLR): Define.
748 (INSN_CHIP_MASK): Update.
750 (OPCODE_IS_MEMBER): Update.
751 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
753 2009-01-28 Doug Evans <dje@google.com>
755 * opcode/i386.h: Add multiple inclusion protection.
756 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
757 (EDI_REG_NUM): New macros.
758 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
759 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
760 (REX_PREFIX_P): New macro.
762 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
764 * ppc.h (struct powerpc_opcode): New field "deprecated".
765 (PPC_OPCODE_NOPOWER4): Delete.
767 2008-11-28 Joshua Kinard <kumba@gentoo.org>
769 * mips.h: Define CPU_R14000, CPU_R16000.
770 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
772 2008-11-18 Catherine Moore <clm@codesourcery.com>
774 * arm.h (FPU_NEON_FP16): New.
775 (FPU_ARCH_NEON_FP16): New.
777 2008-11-06 Chao-ying Fu <fu@mips.com>
779 * mips.h: Doucument '1' for 5-bit sync type.
781 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
783 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
786 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
788 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
790 2008-07-30 Michael J. Eager <eager@eagercon.com>
792 * ppc.h (PPC_OPCODE_405): Define.
793 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
795 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
797 * ppc.h (ppc_cpu_t): New typedef.
798 (struct powerpc_opcode <flags>): Use it.
799 (struct powerpc_operand <insert, extract>): Likewise.
800 (struct powerpc_macro <flags>): Likewise.
802 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
804 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
805 Update comment before MIPS16 field descriptors to mention MIPS16.
806 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
808 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
809 New bit masks and shift counts for cins and exts.
811 * mips.h: Document new field descriptors +Q.
812 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
814 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
816 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
817 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
819 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
821 * ppc.h: (PPC_OPCODE_E500MC): New.
823 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
825 * i386.h (MAX_OPERANDS): Set to 5.
826 (MAX_MNEM_SIZE): Changed to 20.
828 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
830 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
832 2008-03-09 Paul Brook <paul@codesourcery.com>
834 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
836 2008-03-04 Paul Brook <paul@codesourcery.com>
838 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
839 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
840 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
842 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
843 Nick Clifton <nickc@redhat.com>
846 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
847 with a 32-bit displacement but without the top bit of the 4th byte
850 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
852 * cr16.h (cr16_num_optab): Declared.
854 2008-02-14 Hakan Ardo <hakan@debian.org>
857 * avr.h (AVR_ISA_2xxe): Define.
859 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
861 * mips.h: Update copyright.
862 (INSN_CHIP_MASK): New macro.
863 (INSN_OCTEON): New macro.
864 (CPU_OCTEON): New macro.
865 (OPCODE_IS_MEMBER): Handle Octeon instructions.
867 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
869 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
871 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
873 * avr.h (AVR_ISA_USB162): Add new opcode set.
874 (AVR_ISA_AVR3): Likewise.
876 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
878 * mips.h (INSN_LOONGSON_2E): New.
879 (INSN_LOONGSON_2F): New.
880 (CPU_LOONGSON_2E): New.
881 (CPU_LOONGSON_2F): New.
882 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
884 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
886 * mips.h (INSN_ISA*): Redefine certain values as an
887 enumeration. Update comments.
888 (mips_isa_table): New.
889 (ISA_MIPS*): Redefine to match enumeration.
890 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
893 2007-08-08 Ben Elliston <bje@au.ibm.com>
895 * ppc.h (PPC_OPCODE_PPCPS): New.
897 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
899 * m68k.h: Document j K & E.
901 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
903 * cr16.h: New file for CR16 target.
905 2007-05-02 Alan Modra <amodra@bigpond.net.au>
907 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
909 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
911 * m68k.h (mcfisa_c): New.
912 (mcfusp, mcf_mask): Adjust.
914 2007-04-20 Alan Modra <amodra@bigpond.net.au>
916 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
917 (num_powerpc_operands): Declare.
918 (PPC_OPERAND_SIGNED et al): Redefine as hex.
919 (PPC_OPERAND_PLUS1): Define.
921 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
923 * i386.h (REX_MODE64): Renamed to ...
925 (REX_EXTX): Renamed to ...
927 (REX_EXTY): Renamed to ...
929 (REX_EXTZ): Renamed to ...
932 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
934 * i386.h: Add entries from config/tc-i386.h and move tables
935 to opcodes/i386-opc.h.
937 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
939 * i386.h (FloatDR): Removed.
940 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
942 2007-03-01 Alan Modra <amodra@bigpond.net.au>
944 * spu-insns.h: Add soma double-float insns.
946 2007-02-20 Thiemo Seufer <ths@mips.com>
947 Chao-Ying Fu <fu@mips.com>
949 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
950 (INSN_DSPR2): Add flag for DSP R2 instructions.
951 (M_BALIGN): New macro.
953 2007-02-14 Alan Modra <amodra@bigpond.net.au>
955 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
956 and Seg3ShortFrom with Shortform.
958 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
961 * i386.h (i386_optab): Put the real "test" before the pseudo
964 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
966 * m68k.h (m68010up): OR fido_a.
968 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
970 * m68k.h (fido_a): New.
972 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
974 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
975 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
978 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
980 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
982 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
984 * score-inst.h (enum score_insn_type): Add Insn_internal.
986 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
987 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
988 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
989 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
990 Alan Modra <amodra@bigpond.net.au>
992 * spu-insns.h: New file.
995 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
997 * ppc.h (PPC_OPCODE_CELL): Define.
999 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1001 * i386.h : Modify opcode to support for the change in POPCNT opcode
1002 in amdfam10 architecture.
1004 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1006 * i386.h: Replace CpuMNI with CpuSSSE3.
1008 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
1009 Joseph Myers <joseph@codesourcery.com>
1010 Ian Lance Taylor <ian@wasabisystems.com>
1011 Ben Elliston <bje@wasabisystems.com>
1013 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1015 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1017 * score-datadep.h: New file.
1018 * score-inst.h: New file.
1020 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1022 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1023 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1024 movdq2q and movq2dq.
1026 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1027 Michael Meissner <michael.meissner@amd.com>
1029 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1031 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1033 * i386.h (i386_optab): Add "nop" with memory reference.
1035 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1037 * i386.h (i386_optab): Update comment for 64bit NOP.
1039 2006-06-06 Ben Elliston <bje@au.ibm.com>
1040 Anton Blanchard <anton@samba.org>
1042 * ppc.h (PPC_OPCODE_POWER6): Define.
1045 2006-06-05 Thiemo Seufer <ths@mips.com>
1047 * mips.h: Improve description of MT flags.
1049 2006-05-25 Richard Sandiford <richard@codesourcery.com>
1051 * m68k.h (mcf_mask): Define.
1053 2006-05-05 Thiemo Seufer <ths@mips.com>
1054 David Ung <davidu@mips.com>
1056 * mips.h (enum): Add macro M_CACHE_AB.
1058 2006-05-04 Thiemo Seufer <ths@mips.com>
1059 Nigel Stephens <nigel@mips.com>
1060 David Ung <davidu@mips.com>
1062 * mips.h: Add INSN_SMARTMIPS define.
1064 2006-04-30 Thiemo Seufer <ths@mips.com>
1065 David Ung <davidu@mips.com>
1067 * mips.h: Defines udi bits and masks. Add description of
1068 characters which may appear in the args field of udi
1071 2006-04-26 Thiemo Seufer <ths@networkno.de>
1073 * mips.h: Improve comments describing the bitfield instruction
1076 2006-04-26 Julian Brown <julian@codesourcery.com>
1078 * arm.h (FPU_VFP_EXT_V3): Define constant.
1079 (FPU_NEON_EXT_V1): Likewise.
1080 (FPU_VFP_HARD): Update.
1081 (FPU_VFP_V3): Define macro.
1082 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1084 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
1086 * avr.h (AVR_ISA_PWMx): New.
1088 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1090 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1091 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1092 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1093 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1094 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1096 2006-03-10 Paul Brook <paul@codesourcery.com>
1098 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1100 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1102 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1103 first. Correct mask of bb "B" opcode.
1105 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1107 * i386.h (i386_optab): Support Intel Merom New Instructions.
1109 2006-02-24 Paul Brook <paul@codesourcery.com>
1111 * arm.h: Add V7 feature bits.
1113 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1115 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1117 2006-01-31 Paul Brook <paul@codesourcery.com>
1118 Richard Earnshaw <rearnsha@arm.com>
1120 * arm.h: Use ARM_CPU_FEATURE.
1121 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1122 (arm_feature_set): Change to a structure.
1123 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1124 ARM_FEATURE): New macros.
1126 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
1128 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1129 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1130 (ADD_PC_INCR_OPCODE): Don't define.
1132 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1135 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1137 2005-11-14 David Ung <davidu@mips.com>
1139 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1140 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1141 save/restore encoding of the args field.
1143 2005-10-28 Dave Brolley <brolley@redhat.com>
1145 Contribute the following changes:
1146 2005-02-16 Dave Brolley <brolley@redhat.com>
1148 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1149 cgen_isa_mask_* to cgen_bitset_*.
1152 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1154 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1155 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1156 (CGEN_CPU_TABLE): Make isas a ponter.
1158 2003-09-29 Dave Brolley <brolley@redhat.com>
1160 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1161 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1162 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1164 2002-12-13 Dave Brolley <brolley@redhat.com>
1166 * cgen.h (symcat.h): #include it.
1167 (cgen-bitset.h): #include it.
1168 (CGEN_ATTR_VALUE_TYPE): Now a union.
1169 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1170 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1171 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1172 * cgen-bitset.h: New file.
1174 2005-09-30 Catherine Moore <clm@cm00re.com>
1178 2005-10-24 Jan Beulich <jbeulich@novell.com>
1180 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1183 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1185 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1186 Add FLAG_STRICT to pa10 ftest opcode.
1188 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1190 * hppa.h (pa_opcodes): Remove lha entries.
1192 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1194 * hppa.h (FLAG_STRICT): Revise comment.
1195 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1196 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1199 2005-09-30 Catherine Moore <clm@cm00re.com>
1203 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1205 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1207 2005-09-06 Chao-ying Fu <fu@mips.com>
1209 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1210 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1212 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1213 (INSN_ASE_MASK): Update to include INSN_MT.
1214 (INSN_MT): New define for MT ASE.
1216 2005-08-25 Chao-ying Fu <fu@mips.com>
1218 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1219 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1220 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1221 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1222 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1223 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1225 (INSN_DSP): New define for DSP ASE.
1227 2005-08-18 Alan Modra <amodra@bigpond.net.au>
1231 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1233 * ppc.h (PPC_OPCODE_E300): Define.
1235 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1237 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1239 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1242 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1245 2005-07-27 Jan Beulich <jbeulich@novell.com>
1247 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1248 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1249 Add movq-s as 64-bit variants of movd-s.
1251 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1253 * hppa.h: Fix punctuation in comment.
1255 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1256 implicit space-register addressing. Set space-register bits on opcodes
1257 using implicit space-register addressing. Add various missing pa20
1258 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1259 space-register addressing. Use "fE" instead of "fe" in various
1262 2005-07-18 Jan Beulich <jbeulich@novell.com>
1264 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1266 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1268 * i386.h (i386_optab): Support Intel VMX Instructions.
1270 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1272 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1274 2005-07-05 Jan Beulich <jbeulich@novell.com>
1276 * i386.h (i386_optab): Add new insns.
1278 2005-07-01 Nick Clifton <nickc@redhat.com>
1280 * sparc.h: Add typedefs to structure declarations.
1282 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1285 * i386.h (i386_optab): Update comments for 64bit addressing on
1286 mov. Allow 64bit addressing for mov and movq.
1288 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1290 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1291 respectively, in various floating-point load and store patterns.
1293 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1295 * hppa.h (FLAG_STRICT): Correct comment.
1296 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1297 PA 2.0 mneumonics when equivalent. Entries with cache control
1298 completers now require PA 1.1. Adjust whitespace.
1300 2005-05-19 Anton Blanchard <anton@samba.org>
1302 * ppc.h (PPC_OPCODE_POWER5): Define.
1304 2005-05-10 Nick Clifton <nickc@redhat.com>
1306 * Update the address and phone number of the FSF organization in
1307 the GPL notices in the following files:
1308 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1309 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1310 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1311 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1312 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1313 tic54x.h, tic80.h, v850.h, vax.h
1315 2005-05-09 Jan Beulich <jbeulich@novell.com>
1317 * i386.h (i386_optab): Add ht and hnt.
1319 2005-04-18 Mark Kettenis <kettenis@gnu.org>
1321 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1322 Add xcrypt-ctr. Provide aliases without hyphens.
1324 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1326 Moved from ../ChangeLog
1328 2005-04-12 Paul Brook <paul@codesourcery.com>
1329 * m88k.h: Rename psr macros to avoid conflicts.
1331 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1332 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1333 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1334 and ARM_ARCH_V6ZKT2.
1336 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1337 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1338 Remove redundant instruction types.
1339 (struct argument): X_op - new field.
1340 (struct cst4_entry): Remove.
1341 (no_op_insn): Declare.
1343 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1344 * crx.h (enum argtype): Rename types, remove unused types.
1346 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1347 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1348 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1349 (enum operand_type): Rearrange operands, edit comments.
1350 replace us<N> with ui<N> for unsigned immediate.
1351 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1352 displacements (respectively).
1353 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1354 (instruction type): Add NO_TYPE_INS.
1355 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1356 (operand_entry): New field - 'flags'.
1357 (operand flags): New.
1359 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1360 * crx.h (operand_type): Remove redundant types i3, i4,
1362 Add new unsigned immediate types us3, us4, us5, us16.
1364 2005-04-12 Mark Kettenis <kettenis@gnu.org>
1366 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1367 adjust them accordingly.
1369 2005-04-01 Jan Beulich <jbeulich@novell.com>
1371 * i386.h (i386_optab): Add rdtscp.
1373 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1375 * i386.h (i386_optab): Don't allow the `l' suffix for moving
1376 between memory and segment register. Allow movq for moving between
1377 general-purpose register and segment register.
1379 2005-02-09 Jan Beulich <jbeulich@novell.com>
1382 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1383 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1386 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1388 * m68k.h (m68008, m68ec030, m68882): Remove.
1390 (cpu_m68k, cpu_cf): New.
1391 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1392 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1394 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
1396 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1397 * cgen.h (enum cgen_parse_operand_type): Add
1398 CGEN_PARSE_OPERAND_SYMBOLIC.
1400 2005-01-21 Fred Fish <fnf@specifixinc.com>
1402 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1403 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1404 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1406 2005-01-19 Fred Fish <fnf@specifixinc.com>
1408 * mips.h (struct mips_opcode): Add new pinfo2 member.
1409 (INSN_ALIAS): New define for opcode table entries that are
1410 specific instances of another entry, such as 'move' for an 'or'
1411 with a zero operand.
1412 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1413 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1415 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1417 * mips.h (CPU_RM9000): Define.
1418 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1420 2004-11-25 Jan Beulich <jbeulich@novell.com>
1422 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1423 to/from test registers are illegal in 64-bit mode. Add missing
1424 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1425 (previously one had to explicitly encode a rex64 prefix). Re-enable
1426 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1427 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1429 2004-11-23 Jan Beulich <jbeulich@novell.com>
1431 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1432 available only with SSE2. Change the MMX additions introduced by SSE
1433 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1434 instructions by their now designated identifier (since combining i686
1435 and 3DNow! does not really imply 3DNow!A).
1437 2004-11-19 Alan Modra <amodra@bigpond.net.au>
1439 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1440 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1442 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1443 Vineet Sharma <vineets@noida.hcltech.com>
1445 * maxq.h: New file: Disassembly information for the maxq port.
1447 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1449 * i386.h (i386_optab): Put back "movzb".
1451 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
1453 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1454 comments. Remove member cris_ver_sim. Add members
1455 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1456 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1457 (struct cris_support_reg, struct cris_cond15): New types.
1458 (cris_conds15): Declare.
1459 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1460 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1461 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1462 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1463 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1464 SIZE_FIELD_UNSIGNED.
1466 2004-11-04 Jan Beulich <jbeulich@novell.com>
1468 * i386.h (sldx_Suf): Remove.
1469 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1470 (q_FP): Define, implying no REX64.
1471 (x_FP, sl_FP): Imply FloatMF.
1472 (i386_optab): Split reg and mem forms of moving from segment registers
1473 so that the memory forms can ignore the 16-/32-bit operand size
1474 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1475 all non-floating-point instructions. Unite 32- and 64-bit forms of
1476 movsx, movzx, and movd. Adjust floating point operations for the above
1477 changes to the *FP macros. Add DefaultSize to floating point control
1478 insns operating on larger memory ranges. Remove left over comments
1479 hinting at certain insns being Intel-syntax ones where the ones
1480 actually meant are already gone.
1482 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1484 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1487 2004-09-30 Paul Brook <paul@codesourcery.com>
1489 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1490 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1492 2004-09-11 Theodore A. Roth <troth@openavr.org>
1494 * avr.h: Add support for
1495 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1497 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1499 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1501 2004-08-24 Dmitry Diky <diwil@spec.ru>
1503 * msp430.h (msp430_opc): Add new instructions.
1504 (msp430_rcodes): Declare new instructions.
1505 (msp430_hcodes): Likewise..
1507 2004-08-13 Nick Clifton <nickc@redhat.com>
1510 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1513 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1515 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1517 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1519 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1521 2004-07-21 Jan Beulich <jbeulich@novell.com>
1523 * i386.h: Adjust instruction descriptions to better match the
1526 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
1528 * arm.h: Remove all old content. Replace with architecture defines
1529 from gas/config/tc-arm.c.
1531 2004-07-09 Andreas Schwab <schwab@suse.de>
1533 * m68k.h: Fix comment.
1535 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1539 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1541 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1543 2004-05-24 Peter Barada <peter@the-baradas.com>
1545 * m68k.h: Add 'size' to m68k_opcode.
1547 2004-05-05 Peter Barada <peter@the-baradas.com>
1549 * m68k.h: Switch from ColdFire chip name to core variant.
1551 2004-04-22 Peter Barada <peter@the-baradas.com>
1553 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1554 descriptions for new EMAC cases.
1555 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1556 handle Motorola MAC syntax.
1557 Allow disassembly of ColdFire V4e object files.
1559 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1561 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1563 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1565 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1567 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1569 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1571 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1573 * i386.h (i386_optab): Added xstore/xcrypt insns.
1575 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1577 * h8300.h (32bit ldc/stc): Add relaxing support.
1579 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1581 * h8300.h (BITOP): Pass MEMRELAX flag.
1583 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1585 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1588 For older changes see ChangeLog-9103
1594 version-control: never