1 2012-06-07 Georg-Johann Lay <avr@gjlay.de>
3 * avr.h: (AVR_ISA_XCH): New define.
4 (AVR_ISA_XMEGA): Use it.
5 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
7 2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
9 * m68hc11.h: Add XGate definitions.
10 (struct m68hc11_opcode): Add xg_mask field.
12 2012-05-14 Catherine Moore <clm@codesourcery.com>
13 Maciej W. Rozycki <macro@codesourcery.com>
14 Rhonda Wittels <rhonda@codesourcery.com>
16 * ppc.h (PPC_OPCODE_VLE): New definition.
17 (PPC_OP_SA): New macro.
18 (PPC_OP_SE_VLE): New macro.
19 (PPC_OP): Use a variable shift amount.
20 (powerpc_operand): Update comments.
21 (PPC_OPSHIFT_INV): New macro.
22 (PPC_OPERAND_CR): Replace with...
23 (PPC_OPERAND_CR_BIT): ...this and
24 (PPC_OPERAND_CR_REG): ...this.
27 2012-05-03 Sean Keys <skeys@ipdatasys.com>
29 * xgate.h: Header file for XGATE assembler.
31 2012-04-27 David S. Miller <davem@davemloft.net>
33 * sparc.h: Document new arg code' )' for crypto RS3
36 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
37 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
38 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
39 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
40 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
41 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
42 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
43 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
44 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
45 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
46 HWCAP_CBCOND, HWCAP_CRC32): New defines.
48 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
50 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
52 2012-02-27 Alan Modra <amodra@gmail.com>
54 * crx.h (cst4_map): Update declaration.
56 2012-02-25 Walter Lee <walt@tilera.com>
58 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
60 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
61 TILEPRO_OPC_LW_TLS_SN.
63 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
65 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
66 (XRELEASE_PREFIX_OPCODE): Likewise.
68 2011-12-08 Andrew Pinski <apinski@cavium.com>
69 Adam Nemet <anemet@caviumnetworks.com>
71 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
72 (INSN_OCTEON2): New macro.
73 (CPU_OCTEON2): New macro.
74 (OPCODE_IS_MEMBER): Add Octeon2.
76 2011-11-29 Andrew Pinski <apinski@cavium.com>
78 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
79 (INSN_OCTEONP): New macro.
80 (CPU_OCTEONP): New macro.
81 (OPCODE_IS_MEMBER): Add Octeon+.
82 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
84 2011-11-01 DJ Delorie <dj@redhat.com>
88 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
90 * mips.h: Fix a typo in description.
92 2011-09-21 David S. Miller <davem@davemloft.net>
94 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
95 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
96 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
97 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
99 2011-08-09 Chao-ying Fu <fu@mips.com>
100 Maciej W. Rozycki <macro@codesourcery.com>
102 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
103 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
104 (INSN_ASE_MASK): Add the MCU bit.
105 (INSN_MCU): New macro.
106 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
107 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
109 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
111 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
112 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
113 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
114 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
115 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
116 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
117 (INSN2_READ_GPR_MMN): Likewise.
118 (INSN2_READ_FPR_D): Change the bit used.
119 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
120 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
121 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
122 (INSN2_COND_BRANCH): Likewise.
123 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
124 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
125 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
126 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
127 (INSN2_MOD_GPR_MN): Likewise.
129 2011-08-05 David S. Miller <davem@davemloft.net>
131 * sparc.h: Document new format codes '4', '5', and '('.
132 (OPF_LOW4, RS3): New macros.
134 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
136 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
137 order of flags documented.
139 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
141 * mips.h: Clarify the description of microMIPS instruction
143 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
145 2011-07-24 Chao-ying Fu <fu@mips.com>
146 Maciej W. Rozycki <macro@codesourcery.com>
148 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
149 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
150 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
151 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
152 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
153 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
154 (OP_MASK_RS3, OP_SH_RS3): Likewise.
155 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
156 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
157 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
158 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
159 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
160 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
161 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
162 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
163 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
164 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
165 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
166 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
167 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
168 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
169 (INSN_WRITE_GPR_S): New macro.
170 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
171 (INSN2_READ_FPR_D): Likewise.
172 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
173 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
174 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
175 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
176 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
177 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
178 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
179 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
180 (CPU_MICROMIPS): New macro.
181 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
182 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
183 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
184 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
185 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
186 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
187 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
188 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
189 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
190 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
191 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
192 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
193 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
194 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
195 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
196 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
197 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
198 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
199 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
200 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
201 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
202 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
203 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
204 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
205 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
206 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
207 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
208 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
209 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
210 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
211 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
212 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
213 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
214 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
215 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
216 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
217 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
218 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
219 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
220 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
221 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
222 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
223 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
224 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
225 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
226 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
227 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
228 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
229 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
230 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
231 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
232 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
233 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
234 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
235 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
236 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
237 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
238 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
239 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
240 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
241 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
242 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
243 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
244 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
245 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
246 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
247 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
248 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
249 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
250 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
251 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
252 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
253 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
254 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
255 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
256 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
257 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
258 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
259 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
260 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
261 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
262 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
263 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
264 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
265 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
266 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
267 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
268 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
269 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
270 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
271 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
272 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
273 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
274 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
275 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
276 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
277 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
278 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
279 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
280 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
281 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
282 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
283 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
284 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
285 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
286 (micromips_opcodes): New declaration.
287 (bfd_micromips_num_opcodes): Likewise.
289 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
291 * mips.h (INSN_TRAP): Rename to...
292 (INSN_NO_DELAY_SLOT): ... this.
293 (INSN_SYNC): Remove macro.
295 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
297 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
298 a duplicate of AVR_ISA_SPM.
300 2011-07-01 Nick Clifton <nickc@redhat.com>
302 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
304 2011-06-18 Robin Getz <robin.getz@analog.com>
306 * bfin.h (is_macmod_signed): New func
308 2011-06-18 Mike Frysinger <vapier@gentoo.org>
310 * bfin.h (is_macmod_pmove): Add missing space before func args.
311 (is_macmod_hmove): Likewise.
313 2011-06-13 Walter Lee <walt@tilera.com>
315 * tilegx.h: New file.
316 * tilepro.h: New file.
318 2011-05-31 Paul Brook <paul@codesourcery.com>
320 * arm.h (ARM_ARCH_V7R_IDIV): Define.
322 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
324 * s390.h: Replace S390_OPERAND_REG_EVEN with
325 S390_OPERAND_REG_PAIR.
327 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
329 * s390.h: Add S390_OPCODE_REG_EVEN flag.
331 2011-04-18 Julian Brown <julian@codesourcery.com>
333 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
335 2011-04-11 Dan McDonald <dan@wellkeeper.com>
338 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
340 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
342 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
343 New instruction set flags.
344 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
346 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
348 * mips.h (M_PREF_AB): New enum value.
350 2011-02-12 Mike Frysinger <vapier@gentoo.org>
352 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
354 (is_macmod_pmove, is_macmod_hmove): New functions.
356 2011-02-11 Mike Frysinger <vapier@gentoo.org>
358 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
360 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
362 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
363 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
365 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
368 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
371 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
374 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
376 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
378 * mips.h: Update commentary after last commit.
380 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
382 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
383 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
384 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
386 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
388 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
390 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
392 * mips.h: Fix previous commit.
394 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
396 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
397 (INSN_LOONGSON_3A): Clear bit 31.
399 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
402 * arm.h (ARM_AEXT_V6M_ONLY): New define.
403 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
404 (ARM_ARCH_V6M_ONLY): New define.
406 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
408 * mips.h (INSN_LOONGSON_3A): Defined.
409 (CPU_LOONGSON_3A): Defined.
410 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
412 2010-10-09 Matt Rice <ratmice@gmail.com>
414 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
415 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
417 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
419 * arm.h (ARM_EXT_VIRT): New define.
420 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
421 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
424 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
426 * arm.h (ARM_AEXT_ADIV): New define.
427 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
429 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
431 * arm.h (ARM_EXT_OS): New define.
432 (ARM_AEXT_V6SM): Likewise.
433 (ARM_ARCH_V6SM): Likewise.
435 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
437 * arm.h (ARM_EXT_MP): Add.
438 (ARM_ARCH_V7A_MP): Likewise.
440 2010-09-22 Mike Frysinger <vapier@gentoo.org>
442 * bfin.h: Declare pseudoChr structs/defines.
444 2010-09-21 Mike Frysinger <vapier@gentoo.org>
446 * bfin.h: Strip trailing whitespace.
448 2010-07-29 DJ Delorie <dj@redhat.com>
450 * rx.h (RX_Operand_Type): Add TwoReg.
451 (RX_Opcode_ID): Remove ediv and ediv2.
453 2010-07-27 DJ Delorie <dj@redhat.com>
455 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
457 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
458 Ina Pandit <ina.pandit@kpitcummins.com>
460 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
461 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
462 PROCESSOR_V850E2_ALL.
463 Remove PROCESSOR_V850EA support.
464 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
465 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
466 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
467 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
468 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
469 V850_OPERAND_PERCENT.
470 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
472 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
475 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
477 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
478 (MIPS16_INSN_BRANCH): Rename to...
479 (MIPS16_INSN_COND_BRANCH): ... this.
481 2010-07-03 Alan Modra <amodra@gmail.com>
483 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
484 Renumber other PPC_OPCODE defines.
486 2010-07-03 Alan Modra <amodra@gmail.com>
488 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
490 2010-06-29 Alan Modra <amodra@gmail.com>
492 * maxq.h: Delete file.
494 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
496 * ppc.h (PPC_OPCODE_E500): Define.
498 2010-05-26 Catherine Moore <clm@codesourcery.com>
500 * opcode/mips.h (INSN_MIPS16): Remove.
502 2010-04-21 Joseph Myers <joseph@codesourcery.com>
504 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
506 2010-04-15 Nick Clifton <nickc@redhat.com>
508 * alpha.h: Update copyright notice to use GPLv3.
514 * convex.h: Likewise.
528 * m68hc11.h: Likewise.
534 * mn10200.h: Likewise.
535 * mn10300.h: Likewise.
536 * msp430.h: Likewise.
547 * score-datadep.h: Likewise.
548 * score-inst.h: Likewise.
550 * spu-insns.h: Likewise.
554 * tic54x.h: Likewise.
559 2010-03-25 Joseph Myers <joseph@codesourcery.com>
561 * tic6x-control-registers.h, tic6x-insn-formats.h,
562 tic6x-opcode-table.h, tic6x.h: New.
564 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
566 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
568 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
570 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
572 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
574 * ia64.h (ia64_find_opcode): Remove argument name.
575 (ia64_find_next_opcode): Likewise.
576 (ia64_dis_opcode): Likewise.
577 (ia64_free_opcode): Likewise.
578 (ia64_find_dependency): Likewise.
580 2009-11-22 Doug Evans <dje@sebabeach.org>
582 * cgen.h: Include bfd_stdint.h.
583 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
585 2009-11-18 Paul Brook <paul@codesourcery.com>
587 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
589 2009-11-17 Paul Brook <paul@codesourcery.com>
590 Daniel Jacobowitz <dan@codesourcery.com>
592 * arm.h (ARM_EXT_V6_DSP): Define.
593 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
594 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
596 2009-11-04 DJ Delorie <dj@redhat.com>
598 * rx.h (rx_decode_opcode) (mvtipl): Add.
599 (mvtcp, mvfcp, opecp): Remove.
601 2009-11-02 Paul Brook <paul@codesourcery.com>
603 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
604 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
605 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
606 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
607 FPU_ARCH_NEON_VFP_V4): Define.
609 2009-10-23 Doug Evans <dje@sebabeach.org>
611 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
612 * cgen.h: Update. Improve multi-inclusion macro name.
614 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
616 * ppc.h (PPC_OPCODE_476): Define.
618 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
620 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
622 2009-09-29 DJ Delorie <dj@redhat.com>
626 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
628 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
630 2009-09-21 Ben Elliston <bje@au.ibm.com>
632 * ppc.h (PPC_OPCODE_PPCA2): New.
634 2009-09-05 Martin Thuresson <martin@mtme.org>
636 * ia64.h (struct ia64_operand): Renamed member class to op_class.
638 2009-08-29 Martin Thuresson <martin@mtme.org>
640 * tic30.h (template): Rename type template to
641 insn_template. Updated code to use new name.
642 * tic54x.h (template): Rename type template to
645 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
647 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
649 2009-06-11 Anthony Green <green@moxielogic.com>
651 * moxie.h (MOXIE_F3_PCREL): Define.
652 (moxie_form3_opc_info): Grow.
654 2009-06-06 Anthony Green <green@moxielogic.com>
656 * moxie.h (MOXIE_F1_M): Define.
658 2009-04-15 Anthony Green <green@moxielogic.com>
662 2009-04-06 DJ Delorie <dj@redhat.com>
664 * h8300.h: Add relaxation attributes to MOVA opcodes.
666 2009-03-10 Alan Modra <amodra@bigpond.net.au>
668 * ppc.h (ppc_parse_cpu): Declare.
670 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
672 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
673 and _IMM11 for mbitclr and mbitset.
674 * score-datadep.h: Update dependency information.
676 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
678 * ppc.h (PPC_OPCODE_POWER7): New.
680 2009-02-06 Doug Evans <dje@google.com>
682 * i386.h: Add comment regarding sse* insns and prefixes.
684 2009-02-03 Sandip Matte <sandip@rmicorp.com>
686 * mips.h (INSN_XLR): Define.
687 (INSN_CHIP_MASK): Update.
689 (OPCODE_IS_MEMBER): Update.
690 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
692 2009-01-28 Doug Evans <dje@google.com>
694 * opcode/i386.h: Add multiple inclusion protection.
695 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
696 (EDI_REG_NUM): New macros.
697 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
698 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
699 (REX_PREFIX_P): New macro.
701 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
703 * ppc.h (struct powerpc_opcode): New field "deprecated".
704 (PPC_OPCODE_NOPOWER4): Delete.
706 2008-11-28 Joshua Kinard <kumba@gentoo.org>
708 * mips.h: Define CPU_R14000, CPU_R16000.
709 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
711 2008-11-18 Catherine Moore <clm@codesourcery.com>
713 * arm.h (FPU_NEON_FP16): New.
714 (FPU_ARCH_NEON_FP16): New.
716 2008-11-06 Chao-ying Fu <fu@mips.com>
718 * mips.h: Doucument '1' for 5-bit sync type.
720 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
722 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
725 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
727 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
729 2008-07-30 Michael J. Eager <eager@eagercon.com>
731 * ppc.h (PPC_OPCODE_405): Define.
732 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
734 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
736 * ppc.h (ppc_cpu_t): New typedef.
737 (struct powerpc_opcode <flags>): Use it.
738 (struct powerpc_operand <insert, extract>): Likewise.
739 (struct powerpc_macro <flags>): Likewise.
741 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
743 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
744 Update comment before MIPS16 field descriptors to mention MIPS16.
745 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
747 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
748 New bit masks and shift counts for cins and exts.
750 * mips.h: Document new field descriptors +Q.
751 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
753 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
755 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
756 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
758 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
760 * ppc.h: (PPC_OPCODE_E500MC): New.
762 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
764 * i386.h (MAX_OPERANDS): Set to 5.
765 (MAX_MNEM_SIZE): Changed to 20.
767 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
769 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
771 2008-03-09 Paul Brook <paul@codesourcery.com>
773 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
775 2008-03-04 Paul Brook <paul@codesourcery.com>
777 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
778 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
779 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
781 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
782 Nick Clifton <nickc@redhat.com>
785 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
786 with a 32-bit displacement but without the top bit of the 4th byte
789 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
791 * cr16.h (cr16_num_optab): Declared.
793 2008-02-14 Hakan Ardo <hakan@debian.org>
796 * avr.h (AVR_ISA_2xxe): Define.
798 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
800 * mips.h: Update copyright.
801 (INSN_CHIP_MASK): New macro.
802 (INSN_OCTEON): New macro.
803 (CPU_OCTEON): New macro.
804 (OPCODE_IS_MEMBER): Handle Octeon instructions.
806 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
808 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
810 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
812 * avr.h (AVR_ISA_USB162): Add new opcode set.
813 (AVR_ISA_AVR3): Likewise.
815 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
817 * mips.h (INSN_LOONGSON_2E): New.
818 (INSN_LOONGSON_2F): New.
819 (CPU_LOONGSON_2E): New.
820 (CPU_LOONGSON_2F): New.
821 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
823 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
825 * mips.h (INSN_ISA*): Redefine certain values as an
826 enumeration. Update comments.
827 (mips_isa_table): New.
828 (ISA_MIPS*): Redefine to match enumeration.
829 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
832 2007-08-08 Ben Elliston <bje@au.ibm.com>
834 * ppc.h (PPC_OPCODE_PPCPS): New.
836 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
838 * m68k.h: Document j K & E.
840 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
842 * cr16.h: New file for CR16 target.
844 2007-05-02 Alan Modra <amodra@bigpond.net.au>
846 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
848 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
850 * m68k.h (mcfisa_c): New.
851 (mcfusp, mcf_mask): Adjust.
853 2007-04-20 Alan Modra <amodra@bigpond.net.au>
855 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
856 (num_powerpc_operands): Declare.
857 (PPC_OPERAND_SIGNED et al): Redefine as hex.
858 (PPC_OPERAND_PLUS1): Define.
860 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
862 * i386.h (REX_MODE64): Renamed to ...
864 (REX_EXTX): Renamed to ...
866 (REX_EXTY): Renamed to ...
868 (REX_EXTZ): Renamed to ...
871 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
873 * i386.h: Add entries from config/tc-i386.h and move tables
874 to opcodes/i386-opc.h.
876 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
878 * i386.h (FloatDR): Removed.
879 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
881 2007-03-01 Alan Modra <amodra@bigpond.net.au>
883 * spu-insns.h: Add soma double-float insns.
885 2007-02-20 Thiemo Seufer <ths@mips.com>
886 Chao-Ying Fu <fu@mips.com>
888 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
889 (INSN_DSPR2): Add flag for DSP R2 instructions.
890 (M_BALIGN): New macro.
892 2007-02-14 Alan Modra <amodra@bigpond.net.au>
894 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
895 and Seg3ShortFrom with Shortform.
897 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
900 * i386.h (i386_optab): Put the real "test" before the pseudo
903 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
905 * m68k.h (m68010up): OR fido_a.
907 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
909 * m68k.h (fido_a): New.
911 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
913 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
914 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
917 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
919 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
921 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
923 * score-inst.h (enum score_insn_type): Add Insn_internal.
925 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
926 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
927 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
928 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
929 Alan Modra <amodra@bigpond.net.au>
931 * spu-insns.h: New file.
934 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
936 * ppc.h (PPC_OPCODE_CELL): Define.
938 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
940 * i386.h : Modify opcode to support for the change in POPCNT opcode
941 in amdfam10 architecture.
943 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
945 * i386.h: Replace CpuMNI with CpuSSSE3.
947 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
948 Joseph Myers <joseph@codesourcery.com>
949 Ian Lance Taylor <ian@wasabisystems.com>
950 Ben Elliston <bje@wasabisystems.com>
952 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
954 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
956 * score-datadep.h: New file.
957 * score-inst.h: New file.
959 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
961 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
962 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
965 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
966 Michael Meissner <michael.meissner@amd.com>
968 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
970 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
972 * i386.h (i386_optab): Add "nop" with memory reference.
974 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
976 * i386.h (i386_optab): Update comment for 64bit NOP.
978 2006-06-06 Ben Elliston <bje@au.ibm.com>
979 Anton Blanchard <anton@samba.org>
981 * ppc.h (PPC_OPCODE_POWER6): Define.
984 2006-06-05 Thiemo Seufer <ths@mips.com>
986 * mips.h: Improve description of MT flags.
988 2006-05-25 Richard Sandiford <richard@codesourcery.com>
990 * m68k.h (mcf_mask): Define.
992 2006-05-05 Thiemo Seufer <ths@mips.com>
993 David Ung <davidu@mips.com>
995 * mips.h (enum): Add macro M_CACHE_AB.
997 2006-05-04 Thiemo Seufer <ths@mips.com>
998 Nigel Stephens <nigel@mips.com>
999 David Ung <davidu@mips.com>
1001 * mips.h: Add INSN_SMARTMIPS define.
1003 2006-04-30 Thiemo Seufer <ths@mips.com>
1004 David Ung <davidu@mips.com>
1006 * mips.h: Defines udi bits and masks. Add description of
1007 characters which may appear in the args field of udi
1010 2006-04-26 Thiemo Seufer <ths@networkno.de>
1012 * mips.h: Improve comments describing the bitfield instruction
1015 2006-04-26 Julian Brown <julian@codesourcery.com>
1017 * arm.h (FPU_VFP_EXT_V3): Define constant.
1018 (FPU_NEON_EXT_V1): Likewise.
1019 (FPU_VFP_HARD): Update.
1020 (FPU_VFP_V3): Define macro.
1021 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1023 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
1025 * avr.h (AVR_ISA_PWMx): New.
1027 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1029 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1030 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1031 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1032 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1033 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1035 2006-03-10 Paul Brook <paul@codesourcery.com>
1037 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1039 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1041 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1042 first. Correct mask of bb "B" opcode.
1044 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1046 * i386.h (i386_optab): Support Intel Merom New Instructions.
1048 2006-02-24 Paul Brook <paul@codesourcery.com>
1050 * arm.h: Add V7 feature bits.
1052 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1054 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1056 2006-01-31 Paul Brook <paul@codesourcery.com>
1057 Richard Earnshaw <rearnsha@arm.com>
1059 * arm.h: Use ARM_CPU_FEATURE.
1060 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1061 (arm_feature_set): Change to a structure.
1062 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1063 ARM_FEATURE): New macros.
1065 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
1067 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1068 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1069 (ADD_PC_INCR_OPCODE): Don't define.
1071 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1074 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1076 2005-11-14 David Ung <davidu@mips.com>
1078 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1079 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1080 save/restore encoding of the args field.
1082 2005-10-28 Dave Brolley <brolley@redhat.com>
1084 Contribute the following changes:
1085 2005-02-16 Dave Brolley <brolley@redhat.com>
1087 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1088 cgen_isa_mask_* to cgen_bitset_*.
1091 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1093 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1094 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1095 (CGEN_CPU_TABLE): Make isas a ponter.
1097 2003-09-29 Dave Brolley <brolley@redhat.com>
1099 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1100 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1101 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1103 2002-12-13 Dave Brolley <brolley@redhat.com>
1105 * cgen.h (symcat.h): #include it.
1106 (cgen-bitset.h): #include it.
1107 (CGEN_ATTR_VALUE_TYPE): Now a union.
1108 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1109 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1110 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1111 * cgen-bitset.h: New file.
1113 2005-09-30 Catherine Moore <clm@cm00re.com>
1117 2005-10-24 Jan Beulich <jbeulich@novell.com>
1119 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1122 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1124 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1125 Add FLAG_STRICT to pa10 ftest opcode.
1127 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1129 * hppa.h (pa_opcodes): Remove lha entries.
1131 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1133 * hppa.h (FLAG_STRICT): Revise comment.
1134 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1135 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1138 2005-09-30 Catherine Moore <clm@cm00re.com>
1142 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1144 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1146 2005-09-06 Chao-ying Fu <fu@mips.com>
1148 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1149 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1151 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1152 (INSN_ASE_MASK): Update to include INSN_MT.
1153 (INSN_MT): New define for MT ASE.
1155 2005-08-25 Chao-ying Fu <fu@mips.com>
1157 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1158 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1159 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1160 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1161 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1162 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1164 (INSN_DSP): New define for DSP ASE.
1166 2005-08-18 Alan Modra <amodra@bigpond.net.au>
1170 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1172 * ppc.h (PPC_OPCODE_E300): Define.
1174 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1176 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1178 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1181 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1184 2005-07-27 Jan Beulich <jbeulich@novell.com>
1186 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1187 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1188 Add movq-s as 64-bit variants of movd-s.
1190 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1192 * hppa.h: Fix punctuation in comment.
1194 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1195 implicit space-register addressing. Set space-register bits on opcodes
1196 using implicit space-register addressing. Add various missing pa20
1197 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1198 space-register addressing. Use "fE" instead of "fe" in various
1201 2005-07-18 Jan Beulich <jbeulich@novell.com>
1203 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1205 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1207 * i386.h (i386_optab): Support Intel VMX Instructions.
1209 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1211 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1213 2005-07-05 Jan Beulich <jbeulich@novell.com>
1215 * i386.h (i386_optab): Add new insns.
1217 2005-07-01 Nick Clifton <nickc@redhat.com>
1219 * sparc.h: Add typedefs to structure declarations.
1221 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1224 * i386.h (i386_optab): Update comments for 64bit addressing on
1225 mov. Allow 64bit addressing for mov and movq.
1227 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1229 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1230 respectively, in various floating-point load and store patterns.
1232 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1234 * hppa.h (FLAG_STRICT): Correct comment.
1235 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1236 PA 2.0 mneumonics when equivalent. Entries with cache control
1237 completers now require PA 1.1. Adjust whitespace.
1239 2005-05-19 Anton Blanchard <anton@samba.org>
1241 * ppc.h (PPC_OPCODE_POWER5): Define.
1243 2005-05-10 Nick Clifton <nickc@redhat.com>
1245 * Update the address and phone number of the FSF organization in
1246 the GPL notices in the following files:
1247 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1248 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1249 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1250 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1251 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1252 tic54x.h, tic80.h, v850.h, vax.h
1254 2005-05-09 Jan Beulich <jbeulich@novell.com>
1256 * i386.h (i386_optab): Add ht and hnt.
1258 2005-04-18 Mark Kettenis <kettenis@gnu.org>
1260 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1261 Add xcrypt-ctr. Provide aliases without hyphens.
1263 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1265 Moved from ../ChangeLog
1267 2005-04-12 Paul Brook <paul@codesourcery.com>
1268 * m88k.h: Rename psr macros to avoid conflicts.
1270 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1271 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1272 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1273 and ARM_ARCH_V6ZKT2.
1275 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1276 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1277 Remove redundant instruction types.
1278 (struct argument): X_op - new field.
1279 (struct cst4_entry): Remove.
1280 (no_op_insn): Declare.
1282 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1283 * crx.h (enum argtype): Rename types, remove unused types.
1285 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1286 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1287 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1288 (enum operand_type): Rearrange operands, edit comments.
1289 replace us<N> with ui<N> for unsigned immediate.
1290 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1291 displacements (respectively).
1292 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1293 (instruction type): Add NO_TYPE_INS.
1294 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1295 (operand_entry): New field - 'flags'.
1296 (operand flags): New.
1298 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1299 * crx.h (operand_type): Remove redundant types i3, i4,
1301 Add new unsigned immediate types us3, us4, us5, us16.
1303 2005-04-12 Mark Kettenis <kettenis@gnu.org>
1305 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1306 adjust them accordingly.
1308 2005-04-01 Jan Beulich <jbeulich@novell.com>
1310 * i386.h (i386_optab): Add rdtscp.
1312 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1314 * i386.h (i386_optab): Don't allow the `l' suffix for moving
1315 between memory and segment register. Allow movq for moving between
1316 general-purpose register and segment register.
1318 2005-02-09 Jan Beulich <jbeulich@novell.com>
1321 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1322 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1325 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1327 * m68k.h (m68008, m68ec030, m68882): Remove.
1329 (cpu_m68k, cpu_cf): New.
1330 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1331 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1333 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
1335 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1336 * cgen.h (enum cgen_parse_operand_type): Add
1337 CGEN_PARSE_OPERAND_SYMBOLIC.
1339 2005-01-21 Fred Fish <fnf@specifixinc.com>
1341 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1342 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1343 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1345 2005-01-19 Fred Fish <fnf@specifixinc.com>
1347 * mips.h (struct mips_opcode): Add new pinfo2 member.
1348 (INSN_ALIAS): New define for opcode table entries that are
1349 specific instances of another entry, such as 'move' for an 'or'
1350 with a zero operand.
1351 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1352 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1354 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1356 * mips.h (CPU_RM9000): Define.
1357 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1359 2004-11-25 Jan Beulich <jbeulich@novell.com>
1361 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1362 to/from test registers are illegal in 64-bit mode. Add missing
1363 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1364 (previously one had to explicitly encode a rex64 prefix). Re-enable
1365 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1366 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1368 2004-11-23 Jan Beulich <jbeulich@novell.com>
1370 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1371 available only with SSE2. Change the MMX additions introduced by SSE
1372 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1373 instructions by their now designated identifier (since combining i686
1374 and 3DNow! does not really imply 3DNow!A).
1376 2004-11-19 Alan Modra <amodra@bigpond.net.au>
1378 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1379 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1381 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1382 Vineet Sharma <vineets@noida.hcltech.com>
1384 * maxq.h: New file: Disassembly information for the maxq port.
1386 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1388 * i386.h (i386_optab): Put back "movzb".
1390 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
1392 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1393 comments. Remove member cris_ver_sim. Add members
1394 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1395 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1396 (struct cris_support_reg, struct cris_cond15): New types.
1397 (cris_conds15): Declare.
1398 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1399 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1400 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1401 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1402 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1403 SIZE_FIELD_UNSIGNED.
1405 2004-11-04 Jan Beulich <jbeulich@novell.com>
1407 * i386.h (sldx_Suf): Remove.
1408 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1409 (q_FP): Define, implying no REX64.
1410 (x_FP, sl_FP): Imply FloatMF.
1411 (i386_optab): Split reg and mem forms of moving from segment registers
1412 so that the memory forms can ignore the 16-/32-bit operand size
1413 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1414 all non-floating-point instructions. Unite 32- and 64-bit forms of
1415 movsx, movzx, and movd. Adjust floating point operations for the above
1416 changes to the *FP macros. Add DefaultSize to floating point control
1417 insns operating on larger memory ranges. Remove left over comments
1418 hinting at certain insns being Intel-syntax ones where the ones
1419 actually meant are already gone.
1421 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1423 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1426 2004-09-30 Paul Brook <paul@codesourcery.com>
1428 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1429 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1431 2004-09-11 Theodore A. Roth <troth@openavr.org>
1433 * avr.h: Add support for
1434 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1436 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1438 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1440 2004-08-24 Dmitry Diky <diwil@spec.ru>
1442 * msp430.h (msp430_opc): Add new instructions.
1443 (msp430_rcodes): Declare new instructions.
1444 (msp430_hcodes): Likewise..
1446 2004-08-13 Nick Clifton <nickc@redhat.com>
1449 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1452 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1454 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1456 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1458 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1460 2004-07-21 Jan Beulich <jbeulich@novell.com>
1462 * i386.h: Adjust instruction descriptions to better match the
1465 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
1467 * arm.h: Remove all old content. Replace with architecture defines
1468 from gas/config/tc-arm.c.
1470 2004-07-09 Andreas Schwab <schwab@suse.de>
1472 * m68k.h: Fix comment.
1474 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1478 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1480 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1482 2004-05-24 Peter Barada <peter@the-baradas.com>
1484 * m68k.h: Add 'size' to m68k_opcode.
1486 2004-05-05 Peter Barada <peter@the-baradas.com>
1488 * m68k.h: Switch from ColdFire chip name to core variant.
1490 2004-04-22 Peter Barada <peter@the-baradas.com>
1492 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1493 descriptions for new EMAC cases.
1494 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1495 handle Motorola MAC syntax.
1496 Allow disassembly of ColdFire V4e object files.
1498 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1500 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1502 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1504 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1506 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1508 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1510 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1512 * i386.h (i386_optab): Added xstore/xcrypt insns.
1514 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1516 * h8300.h (32bit ldc/stc): Add relaxing support.
1518 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1520 * h8300.h (BITOP): Pass MEMRELAX flag.
1522 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1524 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1527 For older changes see ChangeLog-9103
1533 version-control: never