1 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
3 * cr16.h (make_instruction): Rename to cr16_make_instruction.
4 (match_opcode): Rename to cr16_match_opcode.
6 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
8 * mips.h: Add support for r5900 instructions including lq and sq.
10 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
12 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
13 (make_instruction,match_opcode): Added function prototypes.
14 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
16 2012-11-23 Alan Modra <amodra@gmail.com>
18 * ppc.h (ppc_parse_cpu): Update prototype.
20 2012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
22 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
23 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
25 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
27 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
29 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
31 * ia64.h (ia64_opnd): Add new operand types.
33 2012-08-21 David S. Miller <davem@davemloft.net>
35 * sparc.h (F3F4): New macro.
37 2012-08-13 Ian Bolton <ian.bolton@arm.com>
38 Laurent Desnogues <laurent.desnogues@arm.com>
39 Jim MacArthur <jim.macarthur@arm.com>
40 Marcus Shawcroft <marcus.shawcroft@arm.com>
41 Nigel Stephens <nigel.stephens@arm.com>
42 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
43 Richard Earnshaw <rearnsha@arm.com>
44 Sofiane Naci <sofiane.naci@arm.com>
45 Tejas Belagod <tejas.belagod@arm.com>
46 Yufeng Zhang <yufeng.zhang@arm.com>
48 * aarch64.h: New file.
50 2012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
51 Maciej W. Rozycki <macro@codesourcery.com>
53 * mips.h (mips_opcode): Add the exclusions field.
54 (OPCODE_IS_MEMBER): Remove macro.
55 (cpu_is_member): New inline function.
56 (opcode_is_member): Likewise.
58 2012-07-31 Chao-Ying Fu <fu@mips.com>
59 Catherine Moore <clm@codesourcery.com>
60 Maciej W. Rozycki <macro@codesourcery.com>
62 * mips.h: Document microMIPS DSP ASE usage.
63 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
64 microMIPS DSP ASE support.
65 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
66 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
67 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
68 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
69 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
70 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
71 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
73 2012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
75 * mips.h: Fix a typo in description.
77 2012-06-07 Georg-Johann Lay <avr@gjlay.de>
79 * avr.h: (AVR_ISA_XCH): New define.
80 (AVR_ISA_XMEGA): Use it.
81 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
83 2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
85 * m68hc11.h: Add XGate definitions.
86 (struct m68hc11_opcode): Add xg_mask field.
88 2012-05-14 Catherine Moore <clm@codesourcery.com>
89 Maciej W. Rozycki <macro@codesourcery.com>
90 Rhonda Wittels <rhonda@codesourcery.com>
92 * ppc.h (PPC_OPCODE_VLE): New definition.
93 (PPC_OP_SA): New macro.
94 (PPC_OP_SE_VLE): New macro.
95 (PPC_OP): Use a variable shift amount.
96 (powerpc_operand): Update comments.
97 (PPC_OPSHIFT_INV): New macro.
98 (PPC_OPERAND_CR): Replace with...
99 (PPC_OPERAND_CR_BIT): ...this and
100 (PPC_OPERAND_CR_REG): ...this.
103 2012-05-03 Sean Keys <skeys@ipdatasys.com>
105 * xgate.h: Header file for XGATE assembler.
107 2012-04-27 David S. Miller <davem@davemloft.net>
109 * sparc.h: Document new arg code' )' for crypto RS3
112 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
113 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
114 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
115 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
116 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
117 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
118 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
119 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
120 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
121 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
122 HWCAP_CBCOND, HWCAP_CRC32): New defines.
124 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
126 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
128 2012-02-27 Alan Modra <amodra@gmail.com>
130 * crx.h (cst4_map): Update declaration.
132 2012-02-25 Walter Lee <walt@tilera.com>
134 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
136 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
137 TILEPRO_OPC_LW_TLS_SN.
139 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
141 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
142 (XRELEASE_PREFIX_OPCODE): Likewise.
144 2011-12-08 Andrew Pinski <apinski@cavium.com>
145 Adam Nemet <anemet@caviumnetworks.com>
147 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
148 (INSN_OCTEON2): New macro.
149 (CPU_OCTEON2): New macro.
150 (OPCODE_IS_MEMBER): Add Octeon2.
152 2011-11-29 Andrew Pinski <apinski@cavium.com>
154 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
155 (INSN_OCTEONP): New macro.
156 (CPU_OCTEONP): New macro.
157 (OPCODE_IS_MEMBER): Add Octeon+.
158 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
160 2011-11-01 DJ Delorie <dj@redhat.com>
164 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
166 * mips.h: Fix a typo in description.
168 2011-09-21 David S. Miller <davem@davemloft.net>
170 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
171 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
172 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
173 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
175 2011-08-09 Chao-ying Fu <fu@mips.com>
176 Maciej W. Rozycki <macro@codesourcery.com>
178 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
179 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
180 (INSN_ASE_MASK): Add the MCU bit.
181 (INSN_MCU): New macro.
182 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
183 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
185 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
187 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
188 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
189 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
190 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
191 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
192 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
193 (INSN2_READ_GPR_MMN): Likewise.
194 (INSN2_READ_FPR_D): Change the bit used.
195 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
196 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
197 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
198 (INSN2_COND_BRANCH): Likewise.
199 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
200 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
201 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
202 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
203 (INSN2_MOD_GPR_MN): Likewise.
205 2011-08-05 David S. Miller <davem@davemloft.net>
207 * sparc.h: Document new format codes '4', '5', and '('.
208 (OPF_LOW4, RS3): New macros.
210 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
212 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
213 order of flags documented.
215 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
217 * mips.h: Clarify the description of microMIPS instruction
219 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
221 2011-07-24 Chao-ying Fu <fu@mips.com>
222 Maciej W. Rozycki <macro@codesourcery.com>
224 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
225 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
226 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
227 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
228 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
229 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
230 (OP_MASK_RS3, OP_SH_RS3): Likewise.
231 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
232 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
233 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
234 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
235 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
236 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
237 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
238 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
239 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
240 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
241 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
242 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
243 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
244 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
245 (INSN_WRITE_GPR_S): New macro.
246 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
247 (INSN2_READ_FPR_D): Likewise.
248 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
249 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
250 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
251 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
252 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
253 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
254 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
255 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
256 (CPU_MICROMIPS): New macro.
257 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
258 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
259 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
260 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
261 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
262 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
263 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
264 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
265 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
266 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
267 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
268 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
269 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
270 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
271 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
272 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
273 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
274 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
275 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
276 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
277 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
278 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
279 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
280 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
281 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
282 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
283 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
284 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
285 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
286 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
287 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
288 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
289 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
290 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
291 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
292 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
293 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
294 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
295 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
296 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
297 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
298 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
299 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
300 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
301 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
302 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
303 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
304 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
305 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
306 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
307 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
308 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
309 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
310 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
311 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
312 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
313 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
314 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
315 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
316 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
317 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
318 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
319 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
320 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
321 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
322 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
323 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
324 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
325 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
326 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
327 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
328 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
329 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
330 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
331 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
332 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
333 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
334 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
335 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
336 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
337 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
338 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
339 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
340 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
341 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
342 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
343 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
344 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
345 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
346 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
347 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
348 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
349 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
350 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
351 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
352 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
353 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
354 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
355 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
356 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
357 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
358 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
359 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
360 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
361 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
362 (micromips_opcodes): New declaration.
363 (bfd_micromips_num_opcodes): Likewise.
365 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
367 * mips.h (INSN_TRAP): Rename to...
368 (INSN_NO_DELAY_SLOT): ... this.
369 (INSN_SYNC): Remove macro.
371 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
373 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
374 a duplicate of AVR_ISA_SPM.
376 2011-07-01 Nick Clifton <nickc@redhat.com>
378 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
380 2011-06-18 Robin Getz <robin.getz@analog.com>
382 * bfin.h (is_macmod_signed): New func
384 2011-06-18 Mike Frysinger <vapier@gentoo.org>
386 * bfin.h (is_macmod_pmove): Add missing space before func args.
387 (is_macmod_hmove): Likewise.
389 2011-06-13 Walter Lee <walt@tilera.com>
391 * tilegx.h: New file.
392 * tilepro.h: New file.
394 2011-05-31 Paul Brook <paul@codesourcery.com>
396 * arm.h (ARM_ARCH_V7R_IDIV): Define.
398 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
400 * s390.h: Replace S390_OPERAND_REG_EVEN with
401 S390_OPERAND_REG_PAIR.
403 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
405 * s390.h: Add S390_OPCODE_REG_EVEN flag.
407 2011-04-18 Julian Brown <julian@codesourcery.com>
409 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
411 2011-04-11 Dan McDonald <dan@wellkeeper.com>
414 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
416 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
418 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
419 New instruction set flags.
420 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
422 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
424 * mips.h (M_PREF_AB): New enum value.
426 2011-02-12 Mike Frysinger <vapier@gentoo.org>
428 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
430 (is_macmod_pmove, is_macmod_hmove): New functions.
432 2011-02-11 Mike Frysinger <vapier@gentoo.org>
434 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
436 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
438 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
439 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
441 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
444 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
447 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
450 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
452 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
454 * mips.h: Update commentary after last commit.
456 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
458 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
459 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
460 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
462 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
464 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
466 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
468 * mips.h: Fix previous commit.
470 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
472 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
473 (INSN_LOONGSON_3A): Clear bit 31.
475 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
478 * arm.h (ARM_AEXT_V6M_ONLY): New define.
479 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
480 (ARM_ARCH_V6M_ONLY): New define.
482 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
484 * mips.h (INSN_LOONGSON_3A): Defined.
485 (CPU_LOONGSON_3A): Defined.
486 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
488 2010-10-09 Matt Rice <ratmice@gmail.com>
490 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
491 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
493 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
495 * arm.h (ARM_EXT_VIRT): New define.
496 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
497 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
500 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
502 * arm.h (ARM_AEXT_ADIV): New define.
503 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
505 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
507 * arm.h (ARM_EXT_OS): New define.
508 (ARM_AEXT_V6SM): Likewise.
509 (ARM_ARCH_V6SM): Likewise.
511 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
513 * arm.h (ARM_EXT_MP): Add.
514 (ARM_ARCH_V7A_MP): Likewise.
516 2010-09-22 Mike Frysinger <vapier@gentoo.org>
518 * bfin.h: Declare pseudoChr structs/defines.
520 2010-09-21 Mike Frysinger <vapier@gentoo.org>
522 * bfin.h: Strip trailing whitespace.
524 2010-07-29 DJ Delorie <dj@redhat.com>
526 * rx.h (RX_Operand_Type): Add TwoReg.
527 (RX_Opcode_ID): Remove ediv and ediv2.
529 2010-07-27 DJ Delorie <dj@redhat.com>
531 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
533 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
534 Ina Pandit <ina.pandit@kpitcummins.com>
536 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
537 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
538 PROCESSOR_V850E2_ALL.
539 Remove PROCESSOR_V850EA support.
540 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
541 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
542 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
543 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
544 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
545 V850_OPERAND_PERCENT.
546 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
548 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
551 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
553 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
554 (MIPS16_INSN_BRANCH): Rename to...
555 (MIPS16_INSN_COND_BRANCH): ... this.
557 2010-07-03 Alan Modra <amodra@gmail.com>
559 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
560 Renumber other PPC_OPCODE defines.
562 2010-07-03 Alan Modra <amodra@gmail.com>
564 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
566 2010-06-29 Alan Modra <amodra@gmail.com>
568 * maxq.h: Delete file.
570 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
572 * ppc.h (PPC_OPCODE_E500): Define.
574 2010-05-26 Catherine Moore <clm@codesourcery.com>
576 * opcode/mips.h (INSN_MIPS16): Remove.
578 2010-04-21 Joseph Myers <joseph@codesourcery.com>
580 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
582 2010-04-15 Nick Clifton <nickc@redhat.com>
584 * alpha.h: Update copyright notice to use GPLv3.
590 * convex.h: Likewise.
604 * m68hc11.h: Likewise.
610 * mn10200.h: Likewise.
611 * mn10300.h: Likewise.
612 * msp430.h: Likewise.
623 * score-datadep.h: Likewise.
624 * score-inst.h: Likewise.
626 * spu-insns.h: Likewise.
630 * tic54x.h: Likewise.
635 2010-03-25 Joseph Myers <joseph@codesourcery.com>
637 * tic6x-control-registers.h, tic6x-insn-formats.h,
638 tic6x-opcode-table.h, tic6x.h: New.
640 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
642 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
644 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
646 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
648 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
650 * ia64.h (ia64_find_opcode): Remove argument name.
651 (ia64_find_next_opcode): Likewise.
652 (ia64_dis_opcode): Likewise.
653 (ia64_free_opcode): Likewise.
654 (ia64_find_dependency): Likewise.
656 2009-11-22 Doug Evans <dje@sebabeach.org>
658 * cgen.h: Include bfd_stdint.h.
659 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
661 2009-11-18 Paul Brook <paul@codesourcery.com>
663 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
665 2009-11-17 Paul Brook <paul@codesourcery.com>
666 Daniel Jacobowitz <dan@codesourcery.com>
668 * arm.h (ARM_EXT_V6_DSP): Define.
669 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
670 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
672 2009-11-04 DJ Delorie <dj@redhat.com>
674 * rx.h (rx_decode_opcode) (mvtipl): Add.
675 (mvtcp, mvfcp, opecp): Remove.
677 2009-11-02 Paul Brook <paul@codesourcery.com>
679 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
680 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
681 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
682 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
683 FPU_ARCH_NEON_VFP_V4): Define.
685 2009-10-23 Doug Evans <dje@sebabeach.org>
687 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
688 * cgen.h: Update. Improve multi-inclusion macro name.
690 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
692 * ppc.h (PPC_OPCODE_476): Define.
694 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
696 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
698 2009-09-29 DJ Delorie <dj@redhat.com>
702 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
704 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
706 2009-09-21 Ben Elliston <bje@au.ibm.com>
708 * ppc.h (PPC_OPCODE_PPCA2): New.
710 2009-09-05 Martin Thuresson <martin@mtme.org>
712 * ia64.h (struct ia64_operand): Renamed member class to op_class.
714 2009-08-29 Martin Thuresson <martin@mtme.org>
716 * tic30.h (template): Rename type template to
717 insn_template. Updated code to use new name.
718 * tic54x.h (template): Rename type template to
721 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
723 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
725 2009-06-11 Anthony Green <green@moxielogic.com>
727 * moxie.h (MOXIE_F3_PCREL): Define.
728 (moxie_form3_opc_info): Grow.
730 2009-06-06 Anthony Green <green@moxielogic.com>
732 * moxie.h (MOXIE_F1_M): Define.
734 2009-04-15 Anthony Green <green@moxielogic.com>
738 2009-04-06 DJ Delorie <dj@redhat.com>
740 * h8300.h: Add relaxation attributes to MOVA opcodes.
742 2009-03-10 Alan Modra <amodra@bigpond.net.au>
744 * ppc.h (ppc_parse_cpu): Declare.
746 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
748 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
749 and _IMM11 for mbitclr and mbitset.
750 * score-datadep.h: Update dependency information.
752 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
754 * ppc.h (PPC_OPCODE_POWER7): New.
756 2009-02-06 Doug Evans <dje@google.com>
758 * i386.h: Add comment regarding sse* insns and prefixes.
760 2009-02-03 Sandip Matte <sandip@rmicorp.com>
762 * mips.h (INSN_XLR): Define.
763 (INSN_CHIP_MASK): Update.
765 (OPCODE_IS_MEMBER): Update.
766 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
768 2009-01-28 Doug Evans <dje@google.com>
770 * opcode/i386.h: Add multiple inclusion protection.
771 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
772 (EDI_REG_NUM): New macros.
773 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
774 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
775 (REX_PREFIX_P): New macro.
777 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
779 * ppc.h (struct powerpc_opcode): New field "deprecated".
780 (PPC_OPCODE_NOPOWER4): Delete.
782 2008-11-28 Joshua Kinard <kumba@gentoo.org>
784 * mips.h: Define CPU_R14000, CPU_R16000.
785 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
787 2008-11-18 Catherine Moore <clm@codesourcery.com>
789 * arm.h (FPU_NEON_FP16): New.
790 (FPU_ARCH_NEON_FP16): New.
792 2008-11-06 Chao-ying Fu <fu@mips.com>
794 * mips.h: Doucument '1' for 5-bit sync type.
796 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
798 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
801 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
803 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
805 2008-07-30 Michael J. Eager <eager@eagercon.com>
807 * ppc.h (PPC_OPCODE_405): Define.
808 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
810 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
812 * ppc.h (ppc_cpu_t): New typedef.
813 (struct powerpc_opcode <flags>): Use it.
814 (struct powerpc_operand <insert, extract>): Likewise.
815 (struct powerpc_macro <flags>): Likewise.
817 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
819 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
820 Update comment before MIPS16 field descriptors to mention MIPS16.
821 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
823 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
824 New bit masks and shift counts for cins and exts.
826 * mips.h: Document new field descriptors +Q.
827 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
829 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
831 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
832 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
834 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
836 * ppc.h: (PPC_OPCODE_E500MC): New.
838 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
840 * i386.h (MAX_OPERANDS): Set to 5.
841 (MAX_MNEM_SIZE): Changed to 20.
843 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
845 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
847 2008-03-09 Paul Brook <paul@codesourcery.com>
849 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
851 2008-03-04 Paul Brook <paul@codesourcery.com>
853 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
854 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
855 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
857 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
858 Nick Clifton <nickc@redhat.com>
861 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
862 with a 32-bit displacement but without the top bit of the 4th byte
865 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
867 * cr16.h (cr16_num_optab): Declared.
869 2008-02-14 Hakan Ardo <hakan@debian.org>
872 * avr.h (AVR_ISA_2xxe): Define.
874 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
876 * mips.h: Update copyright.
877 (INSN_CHIP_MASK): New macro.
878 (INSN_OCTEON): New macro.
879 (CPU_OCTEON): New macro.
880 (OPCODE_IS_MEMBER): Handle Octeon instructions.
882 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
884 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
886 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
888 * avr.h (AVR_ISA_USB162): Add new opcode set.
889 (AVR_ISA_AVR3): Likewise.
891 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
893 * mips.h (INSN_LOONGSON_2E): New.
894 (INSN_LOONGSON_2F): New.
895 (CPU_LOONGSON_2E): New.
896 (CPU_LOONGSON_2F): New.
897 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
899 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
901 * mips.h (INSN_ISA*): Redefine certain values as an
902 enumeration. Update comments.
903 (mips_isa_table): New.
904 (ISA_MIPS*): Redefine to match enumeration.
905 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
908 2007-08-08 Ben Elliston <bje@au.ibm.com>
910 * ppc.h (PPC_OPCODE_PPCPS): New.
912 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
914 * m68k.h: Document j K & E.
916 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
918 * cr16.h: New file for CR16 target.
920 2007-05-02 Alan Modra <amodra@bigpond.net.au>
922 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
924 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
926 * m68k.h (mcfisa_c): New.
927 (mcfusp, mcf_mask): Adjust.
929 2007-04-20 Alan Modra <amodra@bigpond.net.au>
931 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
932 (num_powerpc_operands): Declare.
933 (PPC_OPERAND_SIGNED et al): Redefine as hex.
934 (PPC_OPERAND_PLUS1): Define.
936 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
938 * i386.h (REX_MODE64): Renamed to ...
940 (REX_EXTX): Renamed to ...
942 (REX_EXTY): Renamed to ...
944 (REX_EXTZ): Renamed to ...
947 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
949 * i386.h: Add entries from config/tc-i386.h and move tables
950 to opcodes/i386-opc.h.
952 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
954 * i386.h (FloatDR): Removed.
955 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
957 2007-03-01 Alan Modra <amodra@bigpond.net.au>
959 * spu-insns.h: Add soma double-float insns.
961 2007-02-20 Thiemo Seufer <ths@mips.com>
962 Chao-Ying Fu <fu@mips.com>
964 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
965 (INSN_DSPR2): Add flag for DSP R2 instructions.
966 (M_BALIGN): New macro.
968 2007-02-14 Alan Modra <amodra@bigpond.net.au>
970 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
971 and Seg3ShortFrom with Shortform.
973 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
976 * i386.h (i386_optab): Put the real "test" before the pseudo
979 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
981 * m68k.h (m68010up): OR fido_a.
983 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
985 * m68k.h (fido_a): New.
987 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
989 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
990 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
993 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
995 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
997 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
999 * score-inst.h (enum score_insn_type): Add Insn_internal.
1001 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1002 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1003 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1004 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1005 Alan Modra <amodra@bigpond.net.au>
1007 * spu-insns.h: New file.
1010 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1012 * ppc.h (PPC_OPCODE_CELL): Define.
1014 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1016 * i386.h : Modify opcode to support for the change in POPCNT opcode
1017 in amdfam10 architecture.
1019 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1021 * i386.h: Replace CpuMNI with CpuSSSE3.
1023 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
1024 Joseph Myers <joseph@codesourcery.com>
1025 Ian Lance Taylor <ian@wasabisystems.com>
1026 Ben Elliston <bje@wasabisystems.com>
1028 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1030 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1032 * score-datadep.h: New file.
1033 * score-inst.h: New file.
1035 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1037 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1038 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1039 movdq2q and movq2dq.
1041 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1042 Michael Meissner <michael.meissner@amd.com>
1044 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1046 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1048 * i386.h (i386_optab): Add "nop" with memory reference.
1050 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1052 * i386.h (i386_optab): Update comment for 64bit NOP.
1054 2006-06-06 Ben Elliston <bje@au.ibm.com>
1055 Anton Blanchard <anton@samba.org>
1057 * ppc.h (PPC_OPCODE_POWER6): Define.
1060 2006-06-05 Thiemo Seufer <ths@mips.com>
1062 * mips.h: Improve description of MT flags.
1064 2006-05-25 Richard Sandiford <richard@codesourcery.com>
1066 * m68k.h (mcf_mask): Define.
1068 2006-05-05 Thiemo Seufer <ths@mips.com>
1069 David Ung <davidu@mips.com>
1071 * mips.h (enum): Add macro M_CACHE_AB.
1073 2006-05-04 Thiemo Seufer <ths@mips.com>
1074 Nigel Stephens <nigel@mips.com>
1075 David Ung <davidu@mips.com>
1077 * mips.h: Add INSN_SMARTMIPS define.
1079 2006-04-30 Thiemo Seufer <ths@mips.com>
1080 David Ung <davidu@mips.com>
1082 * mips.h: Defines udi bits and masks. Add description of
1083 characters which may appear in the args field of udi
1086 2006-04-26 Thiemo Seufer <ths@networkno.de>
1088 * mips.h: Improve comments describing the bitfield instruction
1091 2006-04-26 Julian Brown <julian@codesourcery.com>
1093 * arm.h (FPU_VFP_EXT_V3): Define constant.
1094 (FPU_NEON_EXT_V1): Likewise.
1095 (FPU_VFP_HARD): Update.
1096 (FPU_VFP_V3): Define macro.
1097 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1099 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
1101 * avr.h (AVR_ISA_PWMx): New.
1103 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1105 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1106 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1107 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1108 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1109 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1111 2006-03-10 Paul Brook <paul@codesourcery.com>
1113 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1115 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1117 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1118 first. Correct mask of bb "B" opcode.
1120 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1122 * i386.h (i386_optab): Support Intel Merom New Instructions.
1124 2006-02-24 Paul Brook <paul@codesourcery.com>
1126 * arm.h: Add V7 feature bits.
1128 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1130 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1132 2006-01-31 Paul Brook <paul@codesourcery.com>
1133 Richard Earnshaw <rearnsha@arm.com>
1135 * arm.h: Use ARM_CPU_FEATURE.
1136 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1137 (arm_feature_set): Change to a structure.
1138 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1139 ARM_FEATURE): New macros.
1141 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
1143 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1144 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1145 (ADD_PC_INCR_OPCODE): Don't define.
1147 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1150 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1152 2005-11-14 David Ung <davidu@mips.com>
1154 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1155 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1156 save/restore encoding of the args field.
1158 2005-10-28 Dave Brolley <brolley@redhat.com>
1160 Contribute the following changes:
1161 2005-02-16 Dave Brolley <brolley@redhat.com>
1163 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1164 cgen_isa_mask_* to cgen_bitset_*.
1167 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1169 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1170 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1171 (CGEN_CPU_TABLE): Make isas a ponter.
1173 2003-09-29 Dave Brolley <brolley@redhat.com>
1175 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1176 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1177 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1179 2002-12-13 Dave Brolley <brolley@redhat.com>
1181 * cgen.h (symcat.h): #include it.
1182 (cgen-bitset.h): #include it.
1183 (CGEN_ATTR_VALUE_TYPE): Now a union.
1184 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1185 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1186 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1187 * cgen-bitset.h: New file.
1189 2005-09-30 Catherine Moore <clm@cm00re.com>
1193 2005-10-24 Jan Beulich <jbeulich@novell.com>
1195 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1198 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1200 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1201 Add FLAG_STRICT to pa10 ftest opcode.
1203 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1205 * hppa.h (pa_opcodes): Remove lha entries.
1207 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1209 * hppa.h (FLAG_STRICT): Revise comment.
1210 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1211 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1214 2005-09-30 Catherine Moore <clm@cm00re.com>
1218 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1220 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1222 2005-09-06 Chao-ying Fu <fu@mips.com>
1224 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1225 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1227 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1228 (INSN_ASE_MASK): Update to include INSN_MT.
1229 (INSN_MT): New define for MT ASE.
1231 2005-08-25 Chao-ying Fu <fu@mips.com>
1233 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1234 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1235 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1236 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1237 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1238 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1240 (INSN_DSP): New define for DSP ASE.
1242 2005-08-18 Alan Modra <amodra@bigpond.net.au>
1246 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1248 * ppc.h (PPC_OPCODE_E300): Define.
1250 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1252 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1254 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1257 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1260 2005-07-27 Jan Beulich <jbeulich@novell.com>
1262 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1263 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1264 Add movq-s as 64-bit variants of movd-s.
1266 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1268 * hppa.h: Fix punctuation in comment.
1270 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1271 implicit space-register addressing. Set space-register bits on opcodes
1272 using implicit space-register addressing. Add various missing pa20
1273 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1274 space-register addressing. Use "fE" instead of "fe" in various
1277 2005-07-18 Jan Beulich <jbeulich@novell.com>
1279 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1281 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1283 * i386.h (i386_optab): Support Intel VMX Instructions.
1285 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1287 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1289 2005-07-05 Jan Beulich <jbeulich@novell.com>
1291 * i386.h (i386_optab): Add new insns.
1293 2005-07-01 Nick Clifton <nickc@redhat.com>
1295 * sparc.h: Add typedefs to structure declarations.
1297 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1300 * i386.h (i386_optab): Update comments for 64bit addressing on
1301 mov. Allow 64bit addressing for mov and movq.
1303 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1305 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1306 respectively, in various floating-point load and store patterns.
1308 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1310 * hppa.h (FLAG_STRICT): Correct comment.
1311 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1312 PA 2.0 mneumonics when equivalent. Entries with cache control
1313 completers now require PA 1.1. Adjust whitespace.
1315 2005-05-19 Anton Blanchard <anton@samba.org>
1317 * ppc.h (PPC_OPCODE_POWER5): Define.
1319 2005-05-10 Nick Clifton <nickc@redhat.com>
1321 * Update the address and phone number of the FSF organization in
1322 the GPL notices in the following files:
1323 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1324 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1325 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1326 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1327 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1328 tic54x.h, tic80.h, v850.h, vax.h
1330 2005-05-09 Jan Beulich <jbeulich@novell.com>
1332 * i386.h (i386_optab): Add ht and hnt.
1334 2005-04-18 Mark Kettenis <kettenis@gnu.org>
1336 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1337 Add xcrypt-ctr. Provide aliases without hyphens.
1339 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1341 Moved from ../ChangeLog
1343 2005-04-12 Paul Brook <paul@codesourcery.com>
1344 * m88k.h: Rename psr macros to avoid conflicts.
1346 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1347 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1348 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1349 and ARM_ARCH_V6ZKT2.
1351 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1352 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1353 Remove redundant instruction types.
1354 (struct argument): X_op - new field.
1355 (struct cst4_entry): Remove.
1356 (no_op_insn): Declare.
1358 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1359 * crx.h (enum argtype): Rename types, remove unused types.
1361 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1362 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1363 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1364 (enum operand_type): Rearrange operands, edit comments.
1365 replace us<N> with ui<N> for unsigned immediate.
1366 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1367 displacements (respectively).
1368 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1369 (instruction type): Add NO_TYPE_INS.
1370 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1371 (operand_entry): New field - 'flags'.
1372 (operand flags): New.
1374 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1375 * crx.h (operand_type): Remove redundant types i3, i4,
1377 Add new unsigned immediate types us3, us4, us5, us16.
1379 2005-04-12 Mark Kettenis <kettenis@gnu.org>
1381 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1382 adjust them accordingly.
1384 2005-04-01 Jan Beulich <jbeulich@novell.com>
1386 * i386.h (i386_optab): Add rdtscp.
1388 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1390 * i386.h (i386_optab): Don't allow the `l' suffix for moving
1391 between memory and segment register. Allow movq for moving between
1392 general-purpose register and segment register.
1394 2005-02-09 Jan Beulich <jbeulich@novell.com>
1397 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1398 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1401 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1403 * m68k.h (m68008, m68ec030, m68882): Remove.
1405 (cpu_m68k, cpu_cf): New.
1406 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1407 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1409 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
1411 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1412 * cgen.h (enum cgen_parse_operand_type): Add
1413 CGEN_PARSE_OPERAND_SYMBOLIC.
1415 2005-01-21 Fred Fish <fnf@specifixinc.com>
1417 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1418 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1419 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1421 2005-01-19 Fred Fish <fnf@specifixinc.com>
1423 * mips.h (struct mips_opcode): Add new pinfo2 member.
1424 (INSN_ALIAS): New define for opcode table entries that are
1425 specific instances of another entry, such as 'move' for an 'or'
1426 with a zero operand.
1427 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1428 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1430 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1432 * mips.h (CPU_RM9000): Define.
1433 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1435 2004-11-25 Jan Beulich <jbeulich@novell.com>
1437 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1438 to/from test registers are illegal in 64-bit mode. Add missing
1439 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1440 (previously one had to explicitly encode a rex64 prefix). Re-enable
1441 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1442 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1444 2004-11-23 Jan Beulich <jbeulich@novell.com>
1446 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1447 available only with SSE2. Change the MMX additions introduced by SSE
1448 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1449 instructions by their now designated identifier (since combining i686
1450 and 3DNow! does not really imply 3DNow!A).
1452 2004-11-19 Alan Modra <amodra@bigpond.net.au>
1454 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1455 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1457 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1458 Vineet Sharma <vineets@noida.hcltech.com>
1460 * maxq.h: New file: Disassembly information for the maxq port.
1462 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1464 * i386.h (i386_optab): Put back "movzb".
1466 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
1468 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1469 comments. Remove member cris_ver_sim. Add members
1470 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1471 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1472 (struct cris_support_reg, struct cris_cond15): New types.
1473 (cris_conds15): Declare.
1474 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1475 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1476 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1477 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1478 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1479 SIZE_FIELD_UNSIGNED.
1481 2004-11-04 Jan Beulich <jbeulich@novell.com>
1483 * i386.h (sldx_Suf): Remove.
1484 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1485 (q_FP): Define, implying no REX64.
1486 (x_FP, sl_FP): Imply FloatMF.
1487 (i386_optab): Split reg and mem forms of moving from segment registers
1488 so that the memory forms can ignore the 16-/32-bit operand size
1489 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1490 all non-floating-point instructions. Unite 32- and 64-bit forms of
1491 movsx, movzx, and movd. Adjust floating point operations for the above
1492 changes to the *FP macros. Add DefaultSize to floating point control
1493 insns operating on larger memory ranges. Remove left over comments
1494 hinting at certain insns being Intel-syntax ones where the ones
1495 actually meant are already gone.
1497 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1499 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1502 2004-09-30 Paul Brook <paul@codesourcery.com>
1504 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1505 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1507 2004-09-11 Theodore A. Roth <troth@openavr.org>
1509 * avr.h: Add support for
1510 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1512 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1514 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1516 2004-08-24 Dmitry Diky <diwil@spec.ru>
1518 * msp430.h (msp430_opc): Add new instructions.
1519 (msp430_rcodes): Declare new instructions.
1520 (msp430_hcodes): Likewise..
1522 2004-08-13 Nick Clifton <nickc@redhat.com>
1525 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1528 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1530 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1532 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1534 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1536 2004-07-21 Jan Beulich <jbeulich@novell.com>
1538 * i386.h: Adjust instruction descriptions to better match the
1541 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
1543 * arm.h: Remove all old content. Replace with architecture defines
1544 from gas/config/tc-arm.c.
1546 2004-07-09 Andreas Schwab <schwab@suse.de>
1548 * m68k.h: Fix comment.
1550 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1554 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1556 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1558 2004-05-24 Peter Barada <peter@the-baradas.com>
1560 * m68k.h: Add 'size' to m68k_opcode.
1562 2004-05-05 Peter Barada <peter@the-baradas.com>
1564 * m68k.h: Switch from ColdFire chip name to core variant.
1566 2004-04-22 Peter Barada <peter@the-baradas.com>
1568 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1569 descriptions for new EMAC cases.
1570 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1571 handle Motorola MAC syntax.
1572 Allow disassembly of ColdFire V4e object files.
1574 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1576 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1578 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1580 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1582 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1584 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1586 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1588 * i386.h (i386_optab): Added xstore/xcrypt insns.
1590 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1592 * h8300.h (32bit ldc/stc): Add relaxing support.
1594 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1596 * h8300.h (BITOP): Pass MEMRELAX flag.
1598 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1600 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1603 For older changes see ChangeLog-9103
1605 Copyright (C) 2004-2012 Free Software Foundation, Inc.
1607 Copying and distribution of this file, with or without modification,
1608 are permitted in any medium without royalty provided the copyright
1609 notice and this notice are preserved.
1615 version-control: never