1 2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
3 * m68hc11.h: Add XGate definitions.
4 (struct m68hc11_opcode): Add xg_mask field.
6 2012-05-14 Catherine Moore <clm@codesourcery.com>
7 Maciej W. Rozycki <macro@codesourcery.com>
8 Rhonda Wittels <rhonda@codesourcery.com>
10 * ppc.h (PPC_OPCODE_VLE): New definition.
11 (PPC_OP_SA): New macro.
12 (PPC_OP_SE_VLE): New macro.
13 (PPC_OP): Use a variable shift amount.
14 (powerpc_operand): Update comments.
15 (PPC_OPSHIFT_INV): New macro.
16 (PPC_OPERAND_CR): Replace with...
17 (PPC_OPERAND_CR_BIT): ...this and
18 (PPC_OPERAND_CR_REG): ...this.
21 2012-05-03 Sean Keys <skeys@ipdatasys.com>
23 * xgate.h: Header file for XGATE assembler.
25 2012-04-27 David S. Miller <davem@davemloft.net>
27 * sparc.h: Document new arg code' )' for crypto RS3
30 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
31 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
32 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
33 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
34 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
35 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
36 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
37 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
38 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
39 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
40 HWCAP_CBCOND, HWCAP_CRC32): New defines.
42 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
44 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
46 2012-02-27 Alan Modra <amodra@gmail.com>
48 * crx.h (cst4_map): Update declaration.
50 2012-02-25 Walter Lee <walt@tilera.com>
52 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
54 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
55 TILEPRO_OPC_LW_TLS_SN.
57 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
59 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
60 (XRELEASE_PREFIX_OPCODE): Likewise.
62 2011-12-08 Andrew Pinski <apinski@cavium.com>
63 Adam Nemet <anemet@caviumnetworks.com>
65 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
66 (INSN_OCTEON2): New macro.
67 (CPU_OCTEON2): New macro.
68 (OPCODE_IS_MEMBER): Add Octeon2.
70 2011-11-29 Andrew Pinski <apinski@cavium.com>
72 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
73 (INSN_OCTEONP): New macro.
74 (CPU_OCTEONP): New macro.
75 (OPCODE_IS_MEMBER): Add Octeon+.
76 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
78 2011-11-01 DJ Delorie <dj@redhat.com>
82 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
84 * mips.h: Fix a typo in description.
86 2011-09-21 David S. Miller <davem@davemloft.net>
88 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
89 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
90 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
91 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
93 2011-08-09 Chao-ying Fu <fu@mips.com>
94 Maciej W. Rozycki <macro@codesourcery.com>
96 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
97 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
98 (INSN_ASE_MASK): Add the MCU bit.
99 (INSN_MCU): New macro.
100 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
101 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
103 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
105 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
106 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
107 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
108 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
109 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
110 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
111 (INSN2_READ_GPR_MMN): Likewise.
112 (INSN2_READ_FPR_D): Change the bit used.
113 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
114 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
115 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
116 (INSN2_COND_BRANCH): Likewise.
117 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
118 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
119 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
120 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
121 (INSN2_MOD_GPR_MN): Likewise.
123 2011-08-05 David S. Miller <davem@davemloft.net>
125 * sparc.h: Document new format codes '4', '5', and '('.
126 (OPF_LOW4, RS3): New macros.
128 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
130 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
131 order of flags documented.
133 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
135 * mips.h: Clarify the description of microMIPS instruction
137 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
139 2011-07-24 Chao-ying Fu <fu@mips.com>
140 Maciej W. Rozycki <macro@codesourcery.com>
142 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
143 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
144 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
145 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
146 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
147 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
148 (OP_MASK_RS3, OP_SH_RS3): Likewise.
149 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
150 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
151 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
152 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
153 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
154 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
155 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
156 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
157 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
158 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
159 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
160 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
161 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
162 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
163 (INSN_WRITE_GPR_S): New macro.
164 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
165 (INSN2_READ_FPR_D): Likewise.
166 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
167 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
168 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
169 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
170 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
171 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
172 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
173 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
174 (CPU_MICROMIPS): New macro.
175 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
176 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
177 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
178 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
179 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
180 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
181 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
182 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
183 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
184 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
185 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
186 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
187 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
188 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
189 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
190 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
191 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
192 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
193 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
194 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
195 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
196 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
197 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
198 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
199 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
200 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
201 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
202 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
203 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
204 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
205 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
206 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
207 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
208 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
209 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
210 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
211 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
212 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
213 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
214 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
215 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
216 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
217 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
218 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
219 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
220 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
221 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
222 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
223 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
224 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
225 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
226 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
227 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
228 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
229 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
230 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
231 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
232 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
233 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
234 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
235 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
236 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
237 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
238 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
239 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
240 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
241 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
242 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
243 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
244 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
245 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
246 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
247 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
248 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
249 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
250 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
251 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
252 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
253 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
254 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
255 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
256 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
257 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
258 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
259 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
260 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
261 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
262 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
263 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
264 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
265 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
266 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
267 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
268 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
269 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
270 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
271 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
272 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
273 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
274 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
275 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
276 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
277 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
278 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
279 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
280 (micromips_opcodes): New declaration.
281 (bfd_micromips_num_opcodes): Likewise.
283 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
285 * mips.h (INSN_TRAP): Rename to...
286 (INSN_NO_DELAY_SLOT): ... this.
287 (INSN_SYNC): Remove macro.
289 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
291 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
292 a duplicate of AVR_ISA_SPM.
294 2011-07-01 Nick Clifton <nickc@redhat.com>
296 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
298 2011-06-18 Robin Getz <robin.getz@analog.com>
300 * bfin.h (is_macmod_signed): New func
302 2011-06-18 Mike Frysinger <vapier@gentoo.org>
304 * bfin.h (is_macmod_pmove): Add missing space before func args.
305 (is_macmod_hmove): Likewise.
307 2011-06-13 Walter Lee <walt@tilera.com>
309 * tilegx.h: New file.
310 * tilepro.h: New file.
312 2011-05-31 Paul Brook <paul@codesourcery.com>
314 * arm.h (ARM_ARCH_V7R_IDIV): Define.
316 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
318 * s390.h: Replace S390_OPERAND_REG_EVEN with
319 S390_OPERAND_REG_PAIR.
321 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
323 * s390.h: Add S390_OPCODE_REG_EVEN flag.
325 2011-04-18 Julian Brown <julian@codesourcery.com>
327 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
329 2011-04-11 Dan McDonald <dan@wellkeeper.com>
332 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
334 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
336 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
337 New instruction set flags.
338 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
340 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
342 * mips.h (M_PREF_AB): New enum value.
344 2011-02-12 Mike Frysinger <vapier@gentoo.org>
346 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
348 (is_macmod_pmove, is_macmod_hmove): New functions.
350 2011-02-11 Mike Frysinger <vapier@gentoo.org>
352 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
354 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
356 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
357 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
359 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
362 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
365 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
368 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
370 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
372 * mips.h: Update commentary after last commit.
374 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
376 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
377 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
378 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
380 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
382 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
384 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
386 * mips.h: Fix previous commit.
388 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
390 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
391 (INSN_LOONGSON_3A): Clear bit 31.
393 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
396 * arm.h (ARM_AEXT_V6M_ONLY): New define.
397 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
398 (ARM_ARCH_V6M_ONLY): New define.
400 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
402 * mips.h (INSN_LOONGSON_3A): Defined.
403 (CPU_LOONGSON_3A): Defined.
404 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
406 2010-10-09 Matt Rice <ratmice@gmail.com>
408 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
409 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
411 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
413 * arm.h (ARM_EXT_VIRT): New define.
414 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
415 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
418 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
420 * arm.h (ARM_AEXT_ADIV): New define.
421 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
423 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
425 * arm.h (ARM_EXT_OS): New define.
426 (ARM_AEXT_V6SM): Likewise.
427 (ARM_ARCH_V6SM): Likewise.
429 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
431 * arm.h (ARM_EXT_MP): Add.
432 (ARM_ARCH_V7A_MP): Likewise.
434 2010-09-22 Mike Frysinger <vapier@gentoo.org>
436 * bfin.h: Declare pseudoChr structs/defines.
438 2010-09-21 Mike Frysinger <vapier@gentoo.org>
440 * bfin.h: Strip trailing whitespace.
442 2010-07-29 DJ Delorie <dj@redhat.com>
444 * rx.h (RX_Operand_Type): Add TwoReg.
445 (RX_Opcode_ID): Remove ediv and ediv2.
447 2010-07-27 DJ Delorie <dj@redhat.com>
449 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
451 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
452 Ina Pandit <ina.pandit@kpitcummins.com>
454 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
455 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
456 PROCESSOR_V850E2_ALL.
457 Remove PROCESSOR_V850EA support.
458 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
459 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
460 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
461 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
462 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
463 V850_OPERAND_PERCENT.
464 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
466 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
469 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
471 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
472 (MIPS16_INSN_BRANCH): Rename to...
473 (MIPS16_INSN_COND_BRANCH): ... this.
475 2010-07-03 Alan Modra <amodra@gmail.com>
477 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
478 Renumber other PPC_OPCODE defines.
480 2010-07-03 Alan Modra <amodra@gmail.com>
482 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
484 2010-06-29 Alan Modra <amodra@gmail.com>
486 * maxq.h: Delete file.
488 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
490 * ppc.h (PPC_OPCODE_E500): Define.
492 2010-05-26 Catherine Moore <clm@codesourcery.com>
494 * opcode/mips.h (INSN_MIPS16): Remove.
496 2010-04-21 Joseph Myers <joseph@codesourcery.com>
498 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
500 2010-04-15 Nick Clifton <nickc@redhat.com>
502 * alpha.h: Update copyright notice to use GPLv3.
508 * convex.h: Likewise.
522 * m68hc11.h: Likewise.
528 * mn10200.h: Likewise.
529 * mn10300.h: Likewise.
530 * msp430.h: Likewise.
541 * score-datadep.h: Likewise.
542 * score-inst.h: Likewise.
544 * spu-insns.h: Likewise.
548 * tic54x.h: Likewise.
553 2010-03-25 Joseph Myers <joseph@codesourcery.com>
555 * tic6x-control-registers.h, tic6x-insn-formats.h,
556 tic6x-opcode-table.h, tic6x.h: New.
558 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
560 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
562 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
564 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
566 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
568 * ia64.h (ia64_find_opcode): Remove argument name.
569 (ia64_find_next_opcode): Likewise.
570 (ia64_dis_opcode): Likewise.
571 (ia64_free_opcode): Likewise.
572 (ia64_find_dependency): Likewise.
574 2009-11-22 Doug Evans <dje@sebabeach.org>
576 * cgen.h: Include bfd_stdint.h.
577 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
579 2009-11-18 Paul Brook <paul@codesourcery.com>
581 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
583 2009-11-17 Paul Brook <paul@codesourcery.com>
584 Daniel Jacobowitz <dan@codesourcery.com>
586 * arm.h (ARM_EXT_V6_DSP): Define.
587 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
588 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
590 2009-11-04 DJ Delorie <dj@redhat.com>
592 * rx.h (rx_decode_opcode) (mvtipl): Add.
593 (mvtcp, mvfcp, opecp): Remove.
595 2009-11-02 Paul Brook <paul@codesourcery.com>
597 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
598 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
599 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
600 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
601 FPU_ARCH_NEON_VFP_V4): Define.
603 2009-10-23 Doug Evans <dje@sebabeach.org>
605 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
606 * cgen.h: Update. Improve multi-inclusion macro name.
608 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
610 * ppc.h (PPC_OPCODE_476): Define.
612 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
614 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
616 2009-09-29 DJ Delorie <dj@redhat.com>
620 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
622 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
624 2009-09-21 Ben Elliston <bje@au.ibm.com>
626 * ppc.h (PPC_OPCODE_PPCA2): New.
628 2009-09-05 Martin Thuresson <martin@mtme.org>
630 * ia64.h (struct ia64_operand): Renamed member class to op_class.
632 2009-08-29 Martin Thuresson <martin@mtme.org>
634 * tic30.h (template): Rename type template to
635 insn_template. Updated code to use new name.
636 * tic54x.h (template): Rename type template to
639 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
641 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
643 2009-06-11 Anthony Green <green@moxielogic.com>
645 * moxie.h (MOXIE_F3_PCREL): Define.
646 (moxie_form3_opc_info): Grow.
648 2009-06-06 Anthony Green <green@moxielogic.com>
650 * moxie.h (MOXIE_F1_M): Define.
652 2009-04-15 Anthony Green <green@moxielogic.com>
656 2009-04-06 DJ Delorie <dj@redhat.com>
658 * h8300.h: Add relaxation attributes to MOVA opcodes.
660 2009-03-10 Alan Modra <amodra@bigpond.net.au>
662 * ppc.h (ppc_parse_cpu): Declare.
664 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
666 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
667 and _IMM11 for mbitclr and mbitset.
668 * score-datadep.h: Update dependency information.
670 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
672 * ppc.h (PPC_OPCODE_POWER7): New.
674 2009-02-06 Doug Evans <dje@google.com>
676 * i386.h: Add comment regarding sse* insns and prefixes.
678 2009-02-03 Sandip Matte <sandip@rmicorp.com>
680 * mips.h (INSN_XLR): Define.
681 (INSN_CHIP_MASK): Update.
683 (OPCODE_IS_MEMBER): Update.
684 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
686 2009-01-28 Doug Evans <dje@google.com>
688 * opcode/i386.h: Add multiple inclusion protection.
689 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
690 (EDI_REG_NUM): New macros.
691 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
692 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
693 (REX_PREFIX_P): New macro.
695 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
697 * ppc.h (struct powerpc_opcode): New field "deprecated".
698 (PPC_OPCODE_NOPOWER4): Delete.
700 2008-11-28 Joshua Kinard <kumba@gentoo.org>
702 * mips.h: Define CPU_R14000, CPU_R16000.
703 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
705 2008-11-18 Catherine Moore <clm@codesourcery.com>
707 * arm.h (FPU_NEON_FP16): New.
708 (FPU_ARCH_NEON_FP16): New.
710 2008-11-06 Chao-ying Fu <fu@mips.com>
712 * mips.h: Doucument '1' for 5-bit sync type.
714 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
716 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
719 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
721 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
723 2008-07-30 Michael J. Eager <eager@eagercon.com>
725 * ppc.h (PPC_OPCODE_405): Define.
726 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
728 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
730 * ppc.h (ppc_cpu_t): New typedef.
731 (struct powerpc_opcode <flags>): Use it.
732 (struct powerpc_operand <insert, extract>): Likewise.
733 (struct powerpc_macro <flags>): Likewise.
735 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
737 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
738 Update comment before MIPS16 field descriptors to mention MIPS16.
739 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
741 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
742 New bit masks and shift counts for cins and exts.
744 * mips.h: Document new field descriptors +Q.
745 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
747 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
749 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
750 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
752 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
754 * ppc.h: (PPC_OPCODE_E500MC): New.
756 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
758 * i386.h (MAX_OPERANDS): Set to 5.
759 (MAX_MNEM_SIZE): Changed to 20.
761 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
763 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
765 2008-03-09 Paul Brook <paul@codesourcery.com>
767 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
769 2008-03-04 Paul Brook <paul@codesourcery.com>
771 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
772 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
773 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
775 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
776 Nick Clifton <nickc@redhat.com>
779 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
780 with a 32-bit displacement but without the top bit of the 4th byte
783 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
785 * cr16.h (cr16_num_optab): Declared.
787 2008-02-14 Hakan Ardo <hakan@debian.org>
790 * avr.h (AVR_ISA_2xxe): Define.
792 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
794 * mips.h: Update copyright.
795 (INSN_CHIP_MASK): New macro.
796 (INSN_OCTEON): New macro.
797 (CPU_OCTEON): New macro.
798 (OPCODE_IS_MEMBER): Handle Octeon instructions.
800 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
802 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
804 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
806 * avr.h (AVR_ISA_USB162): Add new opcode set.
807 (AVR_ISA_AVR3): Likewise.
809 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
811 * mips.h (INSN_LOONGSON_2E): New.
812 (INSN_LOONGSON_2F): New.
813 (CPU_LOONGSON_2E): New.
814 (CPU_LOONGSON_2F): New.
815 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
817 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
819 * mips.h (INSN_ISA*): Redefine certain values as an
820 enumeration. Update comments.
821 (mips_isa_table): New.
822 (ISA_MIPS*): Redefine to match enumeration.
823 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
826 2007-08-08 Ben Elliston <bje@au.ibm.com>
828 * ppc.h (PPC_OPCODE_PPCPS): New.
830 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
832 * m68k.h: Document j K & E.
834 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
836 * cr16.h: New file for CR16 target.
838 2007-05-02 Alan Modra <amodra@bigpond.net.au>
840 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
842 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
844 * m68k.h (mcfisa_c): New.
845 (mcfusp, mcf_mask): Adjust.
847 2007-04-20 Alan Modra <amodra@bigpond.net.au>
849 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
850 (num_powerpc_operands): Declare.
851 (PPC_OPERAND_SIGNED et al): Redefine as hex.
852 (PPC_OPERAND_PLUS1): Define.
854 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
856 * i386.h (REX_MODE64): Renamed to ...
858 (REX_EXTX): Renamed to ...
860 (REX_EXTY): Renamed to ...
862 (REX_EXTZ): Renamed to ...
865 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
867 * i386.h: Add entries from config/tc-i386.h and move tables
868 to opcodes/i386-opc.h.
870 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
872 * i386.h (FloatDR): Removed.
873 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
875 2007-03-01 Alan Modra <amodra@bigpond.net.au>
877 * spu-insns.h: Add soma double-float insns.
879 2007-02-20 Thiemo Seufer <ths@mips.com>
880 Chao-Ying Fu <fu@mips.com>
882 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
883 (INSN_DSPR2): Add flag for DSP R2 instructions.
884 (M_BALIGN): New macro.
886 2007-02-14 Alan Modra <amodra@bigpond.net.au>
888 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
889 and Seg3ShortFrom with Shortform.
891 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
894 * i386.h (i386_optab): Put the real "test" before the pseudo
897 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
899 * m68k.h (m68010up): OR fido_a.
901 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
903 * m68k.h (fido_a): New.
905 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
907 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
908 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
911 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
913 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
915 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
917 * score-inst.h (enum score_insn_type): Add Insn_internal.
919 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
920 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
921 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
922 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
923 Alan Modra <amodra@bigpond.net.au>
925 * spu-insns.h: New file.
928 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
930 * ppc.h (PPC_OPCODE_CELL): Define.
932 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
934 * i386.h : Modify opcode to support for the change in POPCNT opcode
935 in amdfam10 architecture.
937 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
939 * i386.h: Replace CpuMNI with CpuSSSE3.
941 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
942 Joseph Myers <joseph@codesourcery.com>
943 Ian Lance Taylor <ian@wasabisystems.com>
944 Ben Elliston <bje@wasabisystems.com>
946 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
948 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
950 * score-datadep.h: New file.
951 * score-inst.h: New file.
953 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
955 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
956 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
959 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
960 Michael Meissner <michael.meissner@amd.com>
962 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
964 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
966 * i386.h (i386_optab): Add "nop" with memory reference.
968 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
970 * i386.h (i386_optab): Update comment for 64bit NOP.
972 2006-06-06 Ben Elliston <bje@au.ibm.com>
973 Anton Blanchard <anton@samba.org>
975 * ppc.h (PPC_OPCODE_POWER6): Define.
978 2006-06-05 Thiemo Seufer <ths@mips.com>
980 * mips.h: Improve description of MT flags.
982 2006-05-25 Richard Sandiford <richard@codesourcery.com>
984 * m68k.h (mcf_mask): Define.
986 2006-05-05 Thiemo Seufer <ths@mips.com>
987 David Ung <davidu@mips.com>
989 * mips.h (enum): Add macro M_CACHE_AB.
991 2006-05-04 Thiemo Seufer <ths@mips.com>
992 Nigel Stephens <nigel@mips.com>
993 David Ung <davidu@mips.com>
995 * mips.h: Add INSN_SMARTMIPS define.
997 2006-04-30 Thiemo Seufer <ths@mips.com>
998 David Ung <davidu@mips.com>
1000 * mips.h: Defines udi bits and masks. Add description of
1001 characters which may appear in the args field of udi
1004 2006-04-26 Thiemo Seufer <ths@networkno.de>
1006 * mips.h: Improve comments describing the bitfield instruction
1009 2006-04-26 Julian Brown <julian@codesourcery.com>
1011 * arm.h (FPU_VFP_EXT_V3): Define constant.
1012 (FPU_NEON_EXT_V1): Likewise.
1013 (FPU_VFP_HARD): Update.
1014 (FPU_VFP_V3): Define macro.
1015 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1017 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
1019 * avr.h (AVR_ISA_PWMx): New.
1021 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1023 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1024 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1025 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1026 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1027 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1029 2006-03-10 Paul Brook <paul@codesourcery.com>
1031 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1033 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1035 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1036 first. Correct mask of bb "B" opcode.
1038 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1040 * i386.h (i386_optab): Support Intel Merom New Instructions.
1042 2006-02-24 Paul Brook <paul@codesourcery.com>
1044 * arm.h: Add V7 feature bits.
1046 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1048 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1050 2006-01-31 Paul Brook <paul@codesourcery.com>
1051 Richard Earnshaw <rearnsha@arm.com>
1053 * arm.h: Use ARM_CPU_FEATURE.
1054 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1055 (arm_feature_set): Change to a structure.
1056 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1057 ARM_FEATURE): New macros.
1059 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
1061 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1062 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1063 (ADD_PC_INCR_OPCODE): Don't define.
1065 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1068 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1070 2005-11-14 David Ung <davidu@mips.com>
1072 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1073 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1074 save/restore encoding of the args field.
1076 2005-10-28 Dave Brolley <brolley@redhat.com>
1078 Contribute the following changes:
1079 2005-02-16 Dave Brolley <brolley@redhat.com>
1081 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1082 cgen_isa_mask_* to cgen_bitset_*.
1085 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1087 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1088 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1089 (CGEN_CPU_TABLE): Make isas a ponter.
1091 2003-09-29 Dave Brolley <brolley@redhat.com>
1093 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1094 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1095 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1097 2002-12-13 Dave Brolley <brolley@redhat.com>
1099 * cgen.h (symcat.h): #include it.
1100 (cgen-bitset.h): #include it.
1101 (CGEN_ATTR_VALUE_TYPE): Now a union.
1102 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1103 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1104 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1105 * cgen-bitset.h: New file.
1107 2005-09-30 Catherine Moore <clm@cm00re.com>
1111 2005-10-24 Jan Beulich <jbeulich@novell.com>
1113 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1116 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1118 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1119 Add FLAG_STRICT to pa10 ftest opcode.
1121 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1123 * hppa.h (pa_opcodes): Remove lha entries.
1125 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1127 * hppa.h (FLAG_STRICT): Revise comment.
1128 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1129 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1132 2005-09-30 Catherine Moore <clm@cm00re.com>
1136 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1138 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1140 2005-09-06 Chao-ying Fu <fu@mips.com>
1142 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1143 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1145 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1146 (INSN_ASE_MASK): Update to include INSN_MT.
1147 (INSN_MT): New define for MT ASE.
1149 2005-08-25 Chao-ying Fu <fu@mips.com>
1151 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1152 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1153 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1154 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1155 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1156 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1158 (INSN_DSP): New define for DSP ASE.
1160 2005-08-18 Alan Modra <amodra@bigpond.net.au>
1164 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1166 * ppc.h (PPC_OPCODE_E300): Define.
1168 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1170 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1172 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1175 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1178 2005-07-27 Jan Beulich <jbeulich@novell.com>
1180 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1181 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1182 Add movq-s as 64-bit variants of movd-s.
1184 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1186 * hppa.h: Fix punctuation in comment.
1188 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1189 implicit space-register addressing. Set space-register bits on opcodes
1190 using implicit space-register addressing. Add various missing pa20
1191 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1192 space-register addressing. Use "fE" instead of "fe" in various
1195 2005-07-18 Jan Beulich <jbeulich@novell.com>
1197 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1199 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1201 * i386.h (i386_optab): Support Intel VMX Instructions.
1203 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1205 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1207 2005-07-05 Jan Beulich <jbeulich@novell.com>
1209 * i386.h (i386_optab): Add new insns.
1211 2005-07-01 Nick Clifton <nickc@redhat.com>
1213 * sparc.h: Add typedefs to structure declarations.
1215 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1218 * i386.h (i386_optab): Update comments for 64bit addressing on
1219 mov. Allow 64bit addressing for mov and movq.
1221 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1223 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1224 respectively, in various floating-point load and store patterns.
1226 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1228 * hppa.h (FLAG_STRICT): Correct comment.
1229 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1230 PA 2.0 mneumonics when equivalent. Entries with cache control
1231 completers now require PA 1.1. Adjust whitespace.
1233 2005-05-19 Anton Blanchard <anton@samba.org>
1235 * ppc.h (PPC_OPCODE_POWER5): Define.
1237 2005-05-10 Nick Clifton <nickc@redhat.com>
1239 * Update the address and phone number of the FSF organization in
1240 the GPL notices in the following files:
1241 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1242 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1243 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1244 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1245 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1246 tic54x.h, tic80.h, v850.h, vax.h
1248 2005-05-09 Jan Beulich <jbeulich@novell.com>
1250 * i386.h (i386_optab): Add ht and hnt.
1252 2005-04-18 Mark Kettenis <kettenis@gnu.org>
1254 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1255 Add xcrypt-ctr. Provide aliases without hyphens.
1257 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1259 Moved from ../ChangeLog
1261 2005-04-12 Paul Brook <paul@codesourcery.com>
1262 * m88k.h: Rename psr macros to avoid conflicts.
1264 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1265 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1266 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1267 and ARM_ARCH_V6ZKT2.
1269 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1270 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1271 Remove redundant instruction types.
1272 (struct argument): X_op - new field.
1273 (struct cst4_entry): Remove.
1274 (no_op_insn): Declare.
1276 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1277 * crx.h (enum argtype): Rename types, remove unused types.
1279 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1280 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1281 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1282 (enum operand_type): Rearrange operands, edit comments.
1283 replace us<N> with ui<N> for unsigned immediate.
1284 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1285 displacements (respectively).
1286 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1287 (instruction type): Add NO_TYPE_INS.
1288 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1289 (operand_entry): New field - 'flags'.
1290 (operand flags): New.
1292 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1293 * crx.h (operand_type): Remove redundant types i3, i4,
1295 Add new unsigned immediate types us3, us4, us5, us16.
1297 2005-04-12 Mark Kettenis <kettenis@gnu.org>
1299 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1300 adjust them accordingly.
1302 2005-04-01 Jan Beulich <jbeulich@novell.com>
1304 * i386.h (i386_optab): Add rdtscp.
1306 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1308 * i386.h (i386_optab): Don't allow the `l' suffix for moving
1309 between memory and segment register. Allow movq for moving between
1310 general-purpose register and segment register.
1312 2005-02-09 Jan Beulich <jbeulich@novell.com>
1315 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1316 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1319 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1321 * m68k.h (m68008, m68ec030, m68882): Remove.
1323 (cpu_m68k, cpu_cf): New.
1324 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1325 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1327 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
1329 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1330 * cgen.h (enum cgen_parse_operand_type): Add
1331 CGEN_PARSE_OPERAND_SYMBOLIC.
1333 2005-01-21 Fred Fish <fnf@specifixinc.com>
1335 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1336 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1337 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1339 2005-01-19 Fred Fish <fnf@specifixinc.com>
1341 * mips.h (struct mips_opcode): Add new pinfo2 member.
1342 (INSN_ALIAS): New define for opcode table entries that are
1343 specific instances of another entry, such as 'move' for an 'or'
1344 with a zero operand.
1345 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1346 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1348 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1350 * mips.h (CPU_RM9000): Define.
1351 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1353 2004-11-25 Jan Beulich <jbeulich@novell.com>
1355 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1356 to/from test registers are illegal in 64-bit mode. Add missing
1357 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1358 (previously one had to explicitly encode a rex64 prefix). Re-enable
1359 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1360 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1362 2004-11-23 Jan Beulich <jbeulich@novell.com>
1364 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1365 available only with SSE2. Change the MMX additions introduced by SSE
1366 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1367 instructions by their now designated identifier (since combining i686
1368 and 3DNow! does not really imply 3DNow!A).
1370 2004-11-19 Alan Modra <amodra@bigpond.net.au>
1372 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1373 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1375 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1376 Vineet Sharma <vineets@noida.hcltech.com>
1378 * maxq.h: New file: Disassembly information for the maxq port.
1380 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1382 * i386.h (i386_optab): Put back "movzb".
1384 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
1386 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1387 comments. Remove member cris_ver_sim. Add members
1388 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1389 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1390 (struct cris_support_reg, struct cris_cond15): New types.
1391 (cris_conds15): Declare.
1392 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1393 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1394 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1395 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1396 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1397 SIZE_FIELD_UNSIGNED.
1399 2004-11-04 Jan Beulich <jbeulich@novell.com>
1401 * i386.h (sldx_Suf): Remove.
1402 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1403 (q_FP): Define, implying no REX64.
1404 (x_FP, sl_FP): Imply FloatMF.
1405 (i386_optab): Split reg and mem forms of moving from segment registers
1406 so that the memory forms can ignore the 16-/32-bit operand size
1407 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1408 all non-floating-point instructions. Unite 32- and 64-bit forms of
1409 movsx, movzx, and movd. Adjust floating point operations for the above
1410 changes to the *FP macros. Add DefaultSize to floating point control
1411 insns operating on larger memory ranges. Remove left over comments
1412 hinting at certain insns being Intel-syntax ones where the ones
1413 actually meant are already gone.
1415 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1417 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1420 2004-09-30 Paul Brook <paul@codesourcery.com>
1422 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1423 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1425 2004-09-11 Theodore A. Roth <troth@openavr.org>
1427 * avr.h: Add support for
1428 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1430 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1432 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1434 2004-08-24 Dmitry Diky <diwil@spec.ru>
1436 * msp430.h (msp430_opc): Add new instructions.
1437 (msp430_rcodes): Declare new instructions.
1438 (msp430_hcodes): Likewise..
1440 2004-08-13 Nick Clifton <nickc@redhat.com>
1443 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1446 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1448 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1450 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1452 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1454 2004-07-21 Jan Beulich <jbeulich@novell.com>
1456 * i386.h: Adjust instruction descriptions to better match the
1459 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
1461 * arm.h: Remove all old content. Replace with architecture defines
1462 from gas/config/tc-arm.c.
1464 2004-07-09 Andreas Schwab <schwab@suse.de>
1466 * m68k.h: Fix comment.
1468 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1472 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1474 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1476 2004-05-24 Peter Barada <peter@the-baradas.com>
1478 * m68k.h: Add 'size' to m68k_opcode.
1480 2004-05-05 Peter Barada <peter@the-baradas.com>
1482 * m68k.h: Switch from ColdFire chip name to core variant.
1484 2004-04-22 Peter Barada <peter@the-baradas.com>
1486 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1487 descriptions for new EMAC cases.
1488 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1489 handle Motorola MAC syntax.
1490 Allow disassembly of ColdFire V4e object files.
1492 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1494 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1496 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1498 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1500 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1502 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1504 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1506 * i386.h (i386_optab): Added xstore/xcrypt insns.
1508 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1510 * h8300.h (32bit ldc/stc): Add relaxing support.
1512 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1514 * h8300.h (BITOP): Pass MEMRELAX flag.
1516 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1518 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1521 For older changes see ChangeLog-9103
1527 version-control: never