1 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
3 * mips.h: Remove documentation of "[" and "]". Update documentation
4 of "k" and the MDMX formats.
6 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
8 * mips.h: Update documentation of "+s" and "+S".
10 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
12 * mips.h: Document "+i".
14 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
16 * mips.h: Remove "mi" documentation. Update "mh" documentation.
17 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
19 (INSN2_WRITE_GPR_MHI): Rename to...
20 (INSN2_WRITE_GPR_MH): ...this.
22 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
24 * mips.h: Remove documentation of "+D" and "+T".
26 2013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
28 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
29 Use "source" rather than "destination" for microMIPS "G".
31 2013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
33 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
36 2013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
38 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
40 2013-06-17 Catherine Moore <clm@codesourcery.com>
41 Maciej W. Rozycki <macro@codesourcery.com>
42 Chao-Ying Fu <fu@mips.com>
44 * mips.h (OP_SH_EVAOFFSET): Define.
45 (OP_MASK_EVAOFFSET): Define.
46 (INSN_ASE_MASK): Delete.
48 (M_CACHEE_AB, M_CACHEE_OB): New.
49 (M_LBE_OB, M_LBE_AB): New.
50 (M_LBUE_OB, M_LBUE_AB): New.
51 (M_LHE_OB, M_LHE_AB): New.
52 (M_LHUE_OB, M_LHUE_AB): New.
53 (M_LLE_AB, M_LLE_OB): New.
54 (M_LWE_OB, M_LWE_AB): New.
55 (M_LWLE_AB, M_LWLE_OB): New.
56 (M_LWRE_AB, M_LWRE_OB): New.
57 (M_PREFE_AB, M_PREFE_OB): New.
58 (M_SCE_AB, M_SCE_OB): New.
59 (M_SBE_OB, M_SBE_AB): New.
60 (M_SHE_OB, M_SHE_AB): New.
61 (M_SWE_OB, M_SWE_AB): New.
62 (M_SWLE_AB, M_SWLE_OB): New.
63 (M_SWRE_AB, M_SWRE_OB): New.
64 (MICROMIPSOP_SH_EVAOFFSET): Define.
65 (MICROMIPSOP_MASK_EVAOFFSET): Define.
67 2013-06-12 Sandra Loosemore <sandra@codesourcery.com>
69 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
71 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
73 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
75 2013-05-09 Andrew Pinski <apinski@cavium.com>
77 * mips.h (OP_MASK_CODE10): Correct definition.
78 (OP_SH_CODE10): Likewise.
79 Add a comment that "+J" is used now for OP_*CODE10.
80 (INSN_ASE_MASK): Update.
81 (INSN_VIRT): New macro.
82 (INSN_VIRT64): New macro
84 2013-05-02 Nick Clifton <nickc@redhat.com>
86 * msp430.h: Add patterns for MSP430X instructions.
88 2013-04-06 David S. Miller <davem@davemloft.net>
90 * sparc.h (F_PREFERRED): Define.
91 (F_PREF_ALIAS): Define.
93 2013-04-03 Nick Clifton <nickc@redhat.com>
95 * v850.h (V850_INVERSE_PCREL): Define.
97 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
100 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
102 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
105 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
107 * tic6xc-opcode-table.h: Add 16-bit insns.
108 * tic6x.h: Add support for 16-bit insns.
110 2013-03-21 Michael Schewe <michael.schewe@gmx.net>
112 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
113 and mov.b/w/l Rs,@(d:32,ERd).
115 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
118 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
119 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
120 tic6x_operand_xregpair operand coding type.
121 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
122 opcode field, usu ORXREGD1324 for the src2 operand and remove the
125 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
128 * tic6x.h (enum tic6x_coding_method): Add
129 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
130 separately the msb and lsb of a register pair. This is needed to
131 encode the opcodes in the same way as TI assembler does.
132 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
133 and rsqrdp opcodes to use the new field coding types.
135 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
137 * arm.h (CRC_EXT_ARMV8): New constant.
138 (ARCH_CRC_ARMV8): New macro.
140 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
142 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
144 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
145 Andrew Jenner <andrew@codesourcery.com>
147 Based on patches from Altera Corporation.
151 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
153 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
155 2013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
158 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
160 2013-01-24 Nick Clifton <nickc@redhat.com>
162 * v850.h: Add e3v5 support.
164 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
166 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
168 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
170 * ppc.h (PPC_OPCODE_POWER8): New define.
171 (PPC_OPCODE_HTM): Likewise.
173 2013-01-10 Will Newton <will.newton@imgtec.com>
177 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
179 * cr16.h (make_instruction): Rename to cr16_make_instruction.
180 (match_opcode): Rename to cr16_match_opcode.
182 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
184 * mips.h: Add support for r5900 instructions including lq and sq.
186 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
188 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
189 (make_instruction,match_opcode): Added function prototypes.
190 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
192 2012-11-23 Alan Modra <amodra@gmail.com>
194 * ppc.h (ppc_parse_cpu): Update prototype.
196 2012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
198 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
199 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
201 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
203 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
205 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
207 * ia64.h (ia64_opnd): Add new operand types.
209 2012-08-21 David S. Miller <davem@davemloft.net>
211 * sparc.h (F3F4): New macro.
213 2012-08-13 Ian Bolton <ian.bolton@arm.com>
214 Laurent Desnogues <laurent.desnogues@arm.com>
215 Jim MacArthur <jim.macarthur@arm.com>
216 Marcus Shawcroft <marcus.shawcroft@arm.com>
217 Nigel Stephens <nigel.stephens@arm.com>
218 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
219 Richard Earnshaw <rearnsha@arm.com>
220 Sofiane Naci <sofiane.naci@arm.com>
221 Tejas Belagod <tejas.belagod@arm.com>
222 Yufeng Zhang <yufeng.zhang@arm.com>
224 * aarch64.h: New file.
226 2012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
227 Maciej W. Rozycki <macro@codesourcery.com>
229 * mips.h (mips_opcode): Add the exclusions field.
230 (OPCODE_IS_MEMBER): Remove macro.
231 (cpu_is_member): New inline function.
232 (opcode_is_member): Likewise.
234 2012-07-31 Chao-Ying Fu <fu@mips.com>
235 Catherine Moore <clm@codesourcery.com>
236 Maciej W. Rozycki <macro@codesourcery.com>
238 * mips.h: Document microMIPS DSP ASE usage.
239 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
240 microMIPS DSP ASE support.
241 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
242 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
243 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
244 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
245 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
246 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
247 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
249 2012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
251 * mips.h: Fix a typo in description.
253 2012-06-07 Georg-Johann Lay <avr@gjlay.de>
255 * avr.h: (AVR_ISA_XCH): New define.
256 (AVR_ISA_XMEGA): Use it.
257 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
259 2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
261 * m68hc11.h: Add XGate definitions.
262 (struct m68hc11_opcode): Add xg_mask field.
264 2012-05-14 Catherine Moore <clm@codesourcery.com>
265 Maciej W. Rozycki <macro@codesourcery.com>
266 Rhonda Wittels <rhonda@codesourcery.com>
268 * ppc.h (PPC_OPCODE_VLE): New definition.
269 (PPC_OP_SA): New macro.
270 (PPC_OP_SE_VLE): New macro.
271 (PPC_OP): Use a variable shift amount.
272 (powerpc_operand): Update comments.
273 (PPC_OPSHIFT_INV): New macro.
274 (PPC_OPERAND_CR): Replace with...
275 (PPC_OPERAND_CR_BIT): ...this and
276 (PPC_OPERAND_CR_REG): ...this.
279 2012-05-03 Sean Keys <skeys@ipdatasys.com>
281 * xgate.h: Header file for XGATE assembler.
283 2012-04-27 David S. Miller <davem@davemloft.net>
285 * sparc.h: Document new arg code' )' for crypto RS3
288 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
289 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
290 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
291 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
292 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
293 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
294 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
295 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
296 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
297 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
298 HWCAP_CBCOND, HWCAP_CRC32): New defines.
300 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
302 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
304 2012-02-27 Alan Modra <amodra@gmail.com>
306 * crx.h (cst4_map): Update declaration.
308 2012-02-25 Walter Lee <walt@tilera.com>
310 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
312 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
313 TILEPRO_OPC_LW_TLS_SN.
315 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
317 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
318 (XRELEASE_PREFIX_OPCODE): Likewise.
320 2011-12-08 Andrew Pinski <apinski@cavium.com>
321 Adam Nemet <anemet@caviumnetworks.com>
323 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
324 (INSN_OCTEON2): New macro.
325 (CPU_OCTEON2): New macro.
326 (OPCODE_IS_MEMBER): Add Octeon2.
328 2011-11-29 Andrew Pinski <apinski@cavium.com>
330 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
331 (INSN_OCTEONP): New macro.
332 (CPU_OCTEONP): New macro.
333 (OPCODE_IS_MEMBER): Add Octeon+.
334 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
336 2011-11-01 DJ Delorie <dj@redhat.com>
340 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
342 * mips.h: Fix a typo in description.
344 2011-09-21 David S. Miller <davem@davemloft.net>
346 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
347 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
348 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
349 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
351 2011-08-09 Chao-ying Fu <fu@mips.com>
352 Maciej W. Rozycki <macro@codesourcery.com>
354 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
355 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
356 (INSN_ASE_MASK): Add the MCU bit.
357 (INSN_MCU): New macro.
358 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
359 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
361 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
363 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
364 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
365 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
366 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
367 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
368 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
369 (INSN2_READ_GPR_MMN): Likewise.
370 (INSN2_READ_FPR_D): Change the bit used.
371 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
372 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
373 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
374 (INSN2_COND_BRANCH): Likewise.
375 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
376 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
377 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
378 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
379 (INSN2_MOD_GPR_MN): Likewise.
381 2011-08-05 David S. Miller <davem@davemloft.net>
383 * sparc.h: Document new format codes '4', '5', and '('.
384 (OPF_LOW4, RS3): New macros.
386 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
388 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
389 order of flags documented.
391 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
393 * mips.h: Clarify the description of microMIPS instruction
395 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
397 2011-07-24 Chao-ying Fu <fu@mips.com>
398 Maciej W. Rozycki <macro@codesourcery.com>
400 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
401 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
402 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
403 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
404 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
405 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
406 (OP_MASK_RS3, OP_SH_RS3): Likewise.
407 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
408 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
409 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
410 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
411 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
412 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
413 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
414 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
415 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
416 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
417 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
418 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
419 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
420 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
421 (INSN_WRITE_GPR_S): New macro.
422 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
423 (INSN2_READ_FPR_D): Likewise.
424 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
425 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
426 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
427 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
428 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
429 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
430 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
431 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
432 (CPU_MICROMIPS): New macro.
433 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
434 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
435 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
436 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
437 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
438 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
439 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
440 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
441 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
442 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
443 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
444 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
445 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
446 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
447 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
448 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
449 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
450 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
451 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
452 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
453 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
454 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
455 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
456 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
457 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
458 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
459 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
460 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
461 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
462 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
463 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
464 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
465 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
466 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
467 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
468 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
469 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
470 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
471 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
472 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
473 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
474 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
475 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
476 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
477 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
478 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
479 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
480 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
481 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
482 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
483 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
484 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
485 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
486 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
487 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
488 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
489 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
490 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
491 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
492 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
493 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
494 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
495 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
496 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
497 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
498 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
499 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
500 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
501 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
502 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
503 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
504 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
505 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
506 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
507 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
508 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
509 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
510 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
511 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
512 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
513 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
514 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
515 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
516 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
517 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
518 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
519 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
520 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
521 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
522 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
523 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
524 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
525 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
526 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
527 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
528 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
529 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
530 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
531 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
532 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
533 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
534 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
535 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
536 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
537 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
538 (micromips_opcodes): New declaration.
539 (bfd_micromips_num_opcodes): Likewise.
541 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
543 * mips.h (INSN_TRAP): Rename to...
544 (INSN_NO_DELAY_SLOT): ... this.
545 (INSN_SYNC): Remove macro.
547 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
549 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
550 a duplicate of AVR_ISA_SPM.
552 2011-07-01 Nick Clifton <nickc@redhat.com>
554 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
556 2011-06-18 Robin Getz <robin.getz@analog.com>
558 * bfin.h (is_macmod_signed): New func
560 2011-06-18 Mike Frysinger <vapier@gentoo.org>
562 * bfin.h (is_macmod_pmove): Add missing space before func args.
563 (is_macmod_hmove): Likewise.
565 2011-06-13 Walter Lee <walt@tilera.com>
567 * tilegx.h: New file.
568 * tilepro.h: New file.
570 2011-05-31 Paul Brook <paul@codesourcery.com>
572 * arm.h (ARM_ARCH_V7R_IDIV): Define.
574 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
576 * s390.h: Replace S390_OPERAND_REG_EVEN with
577 S390_OPERAND_REG_PAIR.
579 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
581 * s390.h: Add S390_OPCODE_REG_EVEN flag.
583 2011-04-18 Julian Brown <julian@codesourcery.com>
585 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
587 2011-04-11 Dan McDonald <dan@wellkeeper.com>
590 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
592 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
594 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
595 New instruction set flags.
596 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
598 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
600 * mips.h (M_PREF_AB): New enum value.
602 2011-02-12 Mike Frysinger <vapier@gentoo.org>
604 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
606 (is_macmod_pmove, is_macmod_hmove): New functions.
608 2011-02-11 Mike Frysinger <vapier@gentoo.org>
610 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
612 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
614 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
615 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
617 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
620 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
623 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
626 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
628 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
630 * mips.h: Update commentary after last commit.
632 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
634 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
635 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
636 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
638 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
640 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
642 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
644 * mips.h: Fix previous commit.
646 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
648 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
649 (INSN_LOONGSON_3A): Clear bit 31.
651 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
654 * arm.h (ARM_AEXT_V6M_ONLY): New define.
655 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
656 (ARM_ARCH_V6M_ONLY): New define.
658 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
660 * mips.h (INSN_LOONGSON_3A): Defined.
661 (CPU_LOONGSON_3A): Defined.
662 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
664 2010-10-09 Matt Rice <ratmice@gmail.com>
666 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
667 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
669 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
671 * arm.h (ARM_EXT_VIRT): New define.
672 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
673 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
676 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
678 * arm.h (ARM_AEXT_ADIV): New define.
679 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
681 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
683 * arm.h (ARM_EXT_OS): New define.
684 (ARM_AEXT_V6SM): Likewise.
685 (ARM_ARCH_V6SM): Likewise.
687 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
689 * arm.h (ARM_EXT_MP): Add.
690 (ARM_ARCH_V7A_MP): Likewise.
692 2010-09-22 Mike Frysinger <vapier@gentoo.org>
694 * bfin.h: Declare pseudoChr structs/defines.
696 2010-09-21 Mike Frysinger <vapier@gentoo.org>
698 * bfin.h: Strip trailing whitespace.
700 2010-07-29 DJ Delorie <dj@redhat.com>
702 * rx.h (RX_Operand_Type): Add TwoReg.
703 (RX_Opcode_ID): Remove ediv and ediv2.
705 2010-07-27 DJ Delorie <dj@redhat.com>
707 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
709 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
710 Ina Pandit <ina.pandit@kpitcummins.com>
712 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
713 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
714 PROCESSOR_V850E2_ALL.
715 Remove PROCESSOR_V850EA support.
716 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
717 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
718 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
719 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
720 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
721 V850_OPERAND_PERCENT.
722 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
724 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
727 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
729 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
730 (MIPS16_INSN_BRANCH): Rename to...
731 (MIPS16_INSN_COND_BRANCH): ... this.
733 2010-07-03 Alan Modra <amodra@gmail.com>
735 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
736 Renumber other PPC_OPCODE defines.
738 2010-07-03 Alan Modra <amodra@gmail.com>
740 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
742 2010-06-29 Alan Modra <amodra@gmail.com>
744 * maxq.h: Delete file.
746 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
748 * ppc.h (PPC_OPCODE_E500): Define.
750 2010-05-26 Catherine Moore <clm@codesourcery.com>
752 * opcode/mips.h (INSN_MIPS16): Remove.
754 2010-04-21 Joseph Myers <joseph@codesourcery.com>
756 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
758 2010-04-15 Nick Clifton <nickc@redhat.com>
760 * alpha.h: Update copyright notice to use GPLv3.
766 * convex.h: Likewise.
780 * m68hc11.h: Likewise.
786 * mn10200.h: Likewise.
787 * mn10300.h: Likewise.
788 * msp430.h: Likewise.
799 * score-datadep.h: Likewise.
800 * score-inst.h: Likewise.
802 * spu-insns.h: Likewise.
806 * tic54x.h: Likewise.
811 2010-03-25 Joseph Myers <joseph@codesourcery.com>
813 * tic6x-control-registers.h, tic6x-insn-formats.h,
814 tic6x-opcode-table.h, tic6x.h: New.
816 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
818 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
820 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
822 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
824 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
826 * ia64.h (ia64_find_opcode): Remove argument name.
827 (ia64_find_next_opcode): Likewise.
828 (ia64_dis_opcode): Likewise.
829 (ia64_free_opcode): Likewise.
830 (ia64_find_dependency): Likewise.
832 2009-11-22 Doug Evans <dje@sebabeach.org>
834 * cgen.h: Include bfd_stdint.h.
835 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
837 2009-11-18 Paul Brook <paul@codesourcery.com>
839 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
841 2009-11-17 Paul Brook <paul@codesourcery.com>
842 Daniel Jacobowitz <dan@codesourcery.com>
844 * arm.h (ARM_EXT_V6_DSP): Define.
845 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
846 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
848 2009-11-04 DJ Delorie <dj@redhat.com>
850 * rx.h (rx_decode_opcode) (mvtipl): Add.
851 (mvtcp, mvfcp, opecp): Remove.
853 2009-11-02 Paul Brook <paul@codesourcery.com>
855 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
856 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
857 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
858 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
859 FPU_ARCH_NEON_VFP_V4): Define.
861 2009-10-23 Doug Evans <dje@sebabeach.org>
863 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
864 * cgen.h: Update. Improve multi-inclusion macro name.
866 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
868 * ppc.h (PPC_OPCODE_476): Define.
870 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
872 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
874 2009-09-29 DJ Delorie <dj@redhat.com>
878 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
880 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
882 2009-09-21 Ben Elliston <bje@au.ibm.com>
884 * ppc.h (PPC_OPCODE_PPCA2): New.
886 2009-09-05 Martin Thuresson <martin@mtme.org>
888 * ia64.h (struct ia64_operand): Renamed member class to op_class.
890 2009-08-29 Martin Thuresson <martin@mtme.org>
892 * tic30.h (template): Rename type template to
893 insn_template. Updated code to use new name.
894 * tic54x.h (template): Rename type template to
897 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
899 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
901 2009-06-11 Anthony Green <green@moxielogic.com>
903 * moxie.h (MOXIE_F3_PCREL): Define.
904 (moxie_form3_opc_info): Grow.
906 2009-06-06 Anthony Green <green@moxielogic.com>
908 * moxie.h (MOXIE_F1_M): Define.
910 2009-04-15 Anthony Green <green@moxielogic.com>
914 2009-04-06 DJ Delorie <dj@redhat.com>
916 * h8300.h: Add relaxation attributes to MOVA opcodes.
918 2009-03-10 Alan Modra <amodra@bigpond.net.au>
920 * ppc.h (ppc_parse_cpu): Declare.
922 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
924 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
925 and _IMM11 for mbitclr and mbitset.
926 * score-datadep.h: Update dependency information.
928 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
930 * ppc.h (PPC_OPCODE_POWER7): New.
932 2009-02-06 Doug Evans <dje@google.com>
934 * i386.h: Add comment regarding sse* insns and prefixes.
936 2009-02-03 Sandip Matte <sandip@rmicorp.com>
938 * mips.h (INSN_XLR): Define.
939 (INSN_CHIP_MASK): Update.
941 (OPCODE_IS_MEMBER): Update.
942 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
944 2009-01-28 Doug Evans <dje@google.com>
946 * opcode/i386.h: Add multiple inclusion protection.
947 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
948 (EDI_REG_NUM): New macros.
949 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
950 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
951 (REX_PREFIX_P): New macro.
953 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
955 * ppc.h (struct powerpc_opcode): New field "deprecated".
956 (PPC_OPCODE_NOPOWER4): Delete.
958 2008-11-28 Joshua Kinard <kumba@gentoo.org>
960 * mips.h: Define CPU_R14000, CPU_R16000.
961 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
963 2008-11-18 Catherine Moore <clm@codesourcery.com>
965 * arm.h (FPU_NEON_FP16): New.
966 (FPU_ARCH_NEON_FP16): New.
968 2008-11-06 Chao-ying Fu <fu@mips.com>
970 * mips.h: Doucument '1' for 5-bit sync type.
972 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
974 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
977 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
979 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
981 2008-07-30 Michael J. Eager <eager@eagercon.com>
983 * ppc.h (PPC_OPCODE_405): Define.
984 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
986 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
988 * ppc.h (ppc_cpu_t): New typedef.
989 (struct powerpc_opcode <flags>): Use it.
990 (struct powerpc_operand <insert, extract>): Likewise.
991 (struct powerpc_macro <flags>): Likewise.
993 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
995 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
996 Update comment before MIPS16 field descriptors to mention MIPS16.
997 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
999 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1000 New bit masks and shift counts for cins and exts.
1002 * mips.h: Document new field descriptors +Q.
1003 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1005 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1007 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
1008 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1010 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
1012 * ppc.h: (PPC_OPCODE_E500MC): New.
1014 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1016 * i386.h (MAX_OPERANDS): Set to 5.
1017 (MAX_MNEM_SIZE): Changed to 20.
1019 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1021 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1023 2008-03-09 Paul Brook <paul@codesourcery.com>
1025 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1027 2008-03-04 Paul Brook <paul@codesourcery.com>
1029 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1030 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1031 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1033 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
1034 Nick Clifton <nickc@redhat.com>
1037 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1038 with a 32-bit displacement but without the top bit of the 4th byte
1041 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1043 * cr16.h (cr16_num_optab): Declared.
1045 2008-02-14 Hakan Ardo <hakan@debian.org>
1048 * avr.h (AVR_ISA_2xxe): Define.
1050 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1052 * mips.h: Update copyright.
1053 (INSN_CHIP_MASK): New macro.
1054 (INSN_OCTEON): New macro.
1055 (CPU_OCTEON): New macro.
1056 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1058 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1060 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1062 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1064 * avr.h (AVR_ISA_USB162): Add new opcode set.
1065 (AVR_ISA_AVR3): Likewise.
1067 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1069 * mips.h (INSN_LOONGSON_2E): New.
1070 (INSN_LOONGSON_2F): New.
1071 (CPU_LOONGSON_2E): New.
1072 (CPU_LOONGSON_2F): New.
1073 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1075 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1077 * mips.h (INSN_ISA*): Redefine certain values as an
1078 enumeration. Update comments.
1079 (mips_isa_table): New.
1080 (ISA_MIPS*): Redefine to match enumeration.
1081 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1084 2007-08-08 Ben Elliston <bje@au.ibm.com>
1086 * ppc.h (PPC_OPCODE_PPCPS): New.
1088 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1090 * m68k.h: Document j K & E.
1092 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1094 * cr16.h: New file for CR16 target.
1096 2007-05-02 Alan Modra <amodra@bigpond.net.au>
1098 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1100 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1102 * m68k.h (mcfisa_c): New.
1103 (mcfusp, mcf_mask): Adjust.
1105 2007-04-20 Alan Modra <amodra@bigpond.net.au>
1107 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1108 (num_powerpc_operands): Declare.
1109 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1110 (PPC_OPERAND_PLUS1): Define.
1112 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
1114 * i386.h (REX_MODE64): Renamed to ...
1116 (REX_EXTX): Renamed to ...
1118 (REX_EXTY): Renamed to ...
1120 (REX_EXTZ): Renamed to ...
1123 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1125 * i386.h: Add entries from config/tc-i386.h and move tables
1126 to opcodes/i386-opc.h.
1128 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1130 * i386.h (FloatDR): Removed.
1131 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1133 2007-03-01 Alan Modra <amodra@bigpond.net.au>
1135 * spu-insns.h: Add soma double-float insns.
1137 2007-02-20 Thiemo Seufer <ths@mips.com>
1138 Chao-Ying Fu <fu@mips.com>
1140 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1141 (INSN_DSPR2): Add flag for DSP R2 instructions.
1142 (M_BALIGN): New macro.
1144 2007-02-14 Alan Modra <amodra@bigpond.net.au>
1146 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1147 and Seg3ShortFrom with Shortform.
1149 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1152 * i386.h (i386_optab): Put the real "test" before the pseudo
1155 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
1157 * m68k.h (m68010up): OR fido_a.
1159 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
1161 * m68k.h (fido_a): New.
1163 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
1165 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1166 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1169 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1171 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1173 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1175 * score-inst.h (enum score_insn_type): Add Insn_internal.
1177 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1178 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1179 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1180 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1181 Alan Modra <amodra@bigpond.net.au>
1183 * spu-insns.h: New file.
1186 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1188 * ppc.h (PPC_OPCODE_CELL): Define.
1190 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1192 * i386.h : Modify opcode to support for the change in POPCNT opcode
1193 in amdfam10 architecture.
1195 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1197 * i386.h: Replace CpuMNI with CpuSSSE3.
1199 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
1200 Joseph Myers <joseph@codesourcery.com>
1201 Ian Lance Taylor <ian@wasabisystems.com>
1202 Ben Elliston <bje@wasabisystems.com>
1204 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1206 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1208 * score-datadep.h: New file.
1209 * score-inst.h: New file.
1211 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1213 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1214 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1215 movdq2q and movq2dq.
1217 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1218 Michael Meissner <michael.meissner@amd.com>
1220 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1222 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1224 * i386.h (i386_optab): Add "nop" with memory reference.
1226 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1228 * i386.h (i386_optab): Update comment for 64bit NOP.
1230 2006-06-06 Ben Elliston <bje@au.ibm.com>
1231 Anton Blanchard <anton@samba.org>
1233 * ppc.h (PPC_OPCODE_POWER6): Define.
1236 2006-06-05 Thiemo Seufer <ths@mips.com>
1238 * mips.h: Improve description of MT flags.
1240 2006-05-25 Richard Sandiford <richard@codesourcery.com>
1242 * m68k.h (mcf_mask): Define.
1244 2006-05-05 Thiemo Seufer <ths@mips.com>
1245 David Ung <davidu@mips.com>
1247 * mips.h (enum): Add macro M_CACHE_AB.
1249 2006-05-04 Thiemo Seufer <ths@mips.com>
1250 Nigel Stephens <nigel@mips.com>
1251 David Ung <davidu@mips.com>
1253 * mips.h: Add INSN_SMARTMIPS define.
1255 2006-04-30 Thiemo Seufer <ths@mips.com>
1256 David Ung <davidu@mips.com>
1258 * mips.h: Defines udi bits and masks. Add description of
1259 characters which may appear in the args field of udi
1262 2006-04-26 Thiemo Seufer <ths@networkno.de>
1264 * mips.h: Improve comments describing the bitfield instruction
1267 2006-04-26 Julian Brown <julian@codesourcery.com>
1269 * arm.h (FPU_VFP_EXT_V3): Define constant.
1270 (FPU_NEON_EXT_V1): Likewise.
1271 (FPU_VFP_HARD): Update.
1272 (FPU_VFP_V3): Define macro.
1273 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1275 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
1277 * avr.h (AVR_ISA_PWMx): New.
1279 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1281 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1282 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1283 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1284 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1285 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1287 2006-03-10 Paul Brook <paul@codesourcery.com>
1289 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1291 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1293 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1294 first. Correct mask of bb "B" opcode.
1296 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1298 * i386.h (i386_optab): Support Intel Merom New Instructions.
1300 2006-02-24 Paul Brook <paul@codesourcery.com>
1302 * arm.h: Add V7 feature bits.
1304 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1306 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1308 2006-01-31 Paul Brook <paul@codesourcery.com>
1309 Richard Earnshaw <rearnsha@arm.com>
1311 * arm.h: Use ARM_CPU_FEATURE.
1312 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1313 (arm_feature_set): Change to a structure.
1314 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1315 ARM_FEATURE): New macros.
1317 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
1319 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1320 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1321 (ADD_PC_INCR_OPCODE): Don't define.
1323 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1326 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1328 2005-11-14 David Ung <davidu@mips.com>
1330 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1331 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1332 save/restore encoding of the args field.
1334 2005-10-28 Dave Brolley <brolley@redhat.com>
1336 Contribute the following changes:
1337 2005-02-16 Dave Brolley <brolley@redhat.com>
1339 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1340 cgen_isa_mask_* to cgen_bitset_*.
1343 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1345 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1346 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1347 (CGEN_CPU_TABLE): Make isas a ponter.
1349 2003-09-29 Dave Brolley <brolley@redhat.com>
1351 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1352 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1353 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1355 2002-12-13 Dave Brolley <brolley@redhat.com>
1357 * cgen.h (symcat.h): #include it.
1358 (cgen-bitset.h): #include it.
1359 (CGEN_ATTR_VALUE_TYPE): Now a union.
1360 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1361 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1362 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1363 * cgen-bitset.h: New file.
1365 2005-09-30 Catherine Moore <clm@cm00re.com>
1369 2005-10-24 Jan Beulich <jbeulich@novell.com>
1371 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1374 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1376 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1377 Add FLAG_STRICT to pa10 ftest opcode.
1379 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1381 * hppa.h (pa_opcodes): Remove lha entries.
1383 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1385 * hppa.h (FLAG_STRICT): Revise comment.
1386 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1387 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1390 2005-09-30 Catherine Moore <clm@cm00re.com>
1394 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1396 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1398 2005-09-06 Chao-ying Fu <fu@mips.com>
1400 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1401 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1403 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1404 (INSN_ASE_MASK): Update to include INSN_MT.
1405 (INSN_MT): New define for MT ASE.
1407 2005-08-25 Chao-ying Fu <fu@mips.com>
1409 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1410 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1411 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1412 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1413 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1414 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1416 (INSN_DSP): New define for DSP ASE.
1418 2005-08-18 Alan Modra <amodra@bigpond.net.au>
1422 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1424 * ppc.h (PPC_OPCODE_E300): Define.
1426 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1428 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1430 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1433 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1436 2005-07-27 Jan Beulich <jbeulich@novell.com>
1438 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1439 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1440 Add movq-s as 64-bit variants of movd-s.
1442 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1444 * hppa.h: Fix punctuation in comment.
1446 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1447 implicit space-register addressing. Set space-register bits on opcodes
1448 using implicit space-register addressing. Add various missing pa20
1449 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1450 space-register addressing. Use "fE" instead of "fe" in various
1453 2005-07-18 Jan Beulich <jbeulich@novell.com>
1455 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1457 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1459 * i386.h (i386_optab): Support Intel VMX Instructions.
1461 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1463 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1465 2005-07-05 Jan Beulich <jbeulich@novell.com>
1467 * i386.h (i386_optab): Add new insns.
1469 2005-07-01 Nick Clifton <nickc@redhat.com>
1471 * sparc.h: Add typedefs to structure declarations.
1473 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1476 * i386.h (i386_optab): Update comments for 64bit addressing on
1477 mov. Allow 64bit addressing for mov and movq.
1479 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1481 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1482 respectively, in various floating-point load and store patterns.
1484 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1486 * hppa.h (FLAG_STRICT): Correct comment.
1487 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1488 PA 2.0 mneumonics when equivalent. Entries with cache control
1489 completers now require PA 1.1. Adjust whitespace.
1491 2005-05-19 Anton Blanchard <anton@samba.org>
1493 * ppc.h (PPC_OPCODE_POWER5): Define.
1495 2005-05-10 Nick Clifton <nickc@redhat.com>
1497 * Update the address and phone number of the FSF organization in
1498 the GPL notices in the following files:
1499 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1500 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1501 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1502 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1503 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1504 tic54x.h, tic80.h, v850.h, vax.h
1506 2005-05-09 Jan Beulich <jbeulich@novell.com>
1508 * i386.h (i386_optab): Add ht and hnt.
1510 2005-04-18 Mark Kettenis <kettenis@gnu.org>
1512 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1513 Add xcrypt-ctr. Provide aliases without hyphens.
1515 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1517 Moved from ../ChangeLog
1519 2005-04-12 Paul Brook <paul@codesourcery.com>
1520 * m88k.h: Rename psr macros to avoid conflicts.
1522 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1523 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1524 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1525 and ARM_ARCH_V6ZKT2.
1527 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1528 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1529 Remove redundant instruction types.
1530 (struct argument): X_op - new field.
1531 (struct cst4_entry): Remove.
1532 (no_op_insn): Declare.
1534 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1535 * crx.h (enum argtype): Rename types, remove unused types.
1537 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1538 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1539 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1540 (enum operand_type): Rearrange operands, edit comments.
1541 replace us<N> with ui<N> for unsigned immediate.
1542 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1543 displacements (respectively).
1544 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1545 (instruction type): Add NO_TYPE_INS.
1546 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1547 (operand_entry): New field - 'flags'.
1548 (operand flags): New.
1550 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1551 * crx.h (operand_type): Remove redundant types i3, i4,
1553 Add new unsigned immediate types us3, us4, us5, us16.
1555 2005-04-12 Mark Kettenis <kettenis@gnu.org>
1557 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1558 adjust them accordingly.
1560 2005-04-01 Jan Beulich <jbeulich@novell.com>
1562 * i386.h (i386_optab): Add rdtscp.
1564 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1566 * i386.h (i386_optab): Don't allow the `l' suffix for moving
1567 between memory and segment register. Allow movq for moving between
1568 general-purpose register and segment register.
1570 2005-02-09 Jan Beulich <jbeulich@novell.com>
1573 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1574 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1577 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1579 * m68k.h (m68008, m68ec030, m68882): Remove.
1581 (cpu_m68k, cpu_cf): New.
1582 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1583 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1585 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
1587 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1588 * cgen.h (enum cgen_parse_operand_type): Add
1589 CGEN_PARSE_OPERAND_SYMBOLIC.
1591 2005-01-21 Fred Fish <fnf@specifixinc.com>
1593 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1594 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1595 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1597 2005-01-19 Fred Fish <fnf@specifixinc.com>
1599 * mips.h (struct mips_opcode): Add new pinfo2 member.
1600 (INSN_ALIAS): New define for opcode table entries that are
1601 specific instances of another entry, such as 'move' for an 'or'
1602 with a zero operand.
1603 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1604 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1606 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1608 * mips.h (CPU_RM9000): Define.
1609 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1611 2004-11-25 Jan Beulich <jbeulich@novell.com>
1613 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1614 to/from test registers are illegal in 64-bit mode. Add missing
1615 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1616 (previously one had to explicitly encode a rex64 prefix). Re-enable
1617 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1618 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1620 2004-11-23 Jan Beulich <jbeulich@novell.com>
1622 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1623 available only with SSE2. Change the MMX additions introduced by SSE
1624 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1625 instructions by their now designated identifier (since combining i686
1626 and 3DNow! does not really imply 3DNow!A).
1628 2004-11-19 Alan Modra <amodra@bigpond.net.au>
1630 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1631 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1633 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1634 Vineet Sharma <vineets@noida.hcltech.com>
1636 * maxq.h: New file: Disassembly information for the maxq port.
1638 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1640 * i386.h (i386_optab): Put back "movzb".
1642 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
1644 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1645 comments. Remove member cris_ver_sim. Add members
1646 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1647 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1648 (struct cris_support_reg, struct cris_cond15): New types.
1649 (cris_conds15): Declare.
1650 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1651 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1652 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1653 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1654 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1655 SIZE_FIELD_UNSIGNED.
1657 2004-11-04 Jan Beulich <jbeulich@novell.com>
1659 * i386.h (sldx_Suf): Remove.
1660 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1661 (q_FP): Define, implying no REX64.
1662 (x_FP, sl_FP): Imply FloatMF.
1663 (i386_optab): Split reg and mem forms of moving from segment registers
1664 so that the memory forms can ignore the 16-/32-bit operand size
1665 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1666 all non-floating-point instructions. Unite 32- and 64-bit forms of
1667 movsx, movzx, and movd. Adjust floating point operations for the above
1668 changes to the *FP macros. Add DefaultSize to floating point control
1669 insns operating on larger memory ranges. Remove left over comments
1670 hinting at certain insns being Intel-syntax ones where the ones
1671 actually meant are already gone.
1673 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1675 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1678 2004-09-30 Paul Brook <paul@codesourcery.com>
1680 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1681 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1683 2004-09-11 Theodore A. Roth <troth@openavr.org>
1685 * avr.h: Add support for
1686 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1688 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1690 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1692 2004-08-24 Dmitry Diky <diwil@spec.ru>
1694 * msp430.h (msp430_opc): Add new instructions.
1695 (msp430_rcodes): Declare new instructions.
1696 (msp430_hcodes): Likewise..
1698 2004-08-13 Nick Clifton <nickc@redhat.com>
1701 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1704 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1706 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1708 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1710 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1712 2004-07-21 Jan Beulich <jbeulich@novell.com>
1714 * i386.h: Adjust instruction descriptions to better match the
1717 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
1719 * arm.h: Remove all old content. Replace with architecture defines
1720 from gas/config/tc-arm.c.
1722 2004-07-09 Andreas Schwab <schwab@suse.de>
1724 * m68k.h: Fix comment.
1726 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1730 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1732 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1734 2004-05-24 Peter Barada <peter@the-baradas.com>
1736 * m68k.h: Add 'size' to m68k_opcode.
1738 2004-05-05 Peter Barada <peter@the-baradas.com>
1740 * m68k.h: Switch from ColdFire chip name to core variant.
1742 2004-04-22 Peter Barada <peter@the-baradas.com>
1744 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1745 descriptions for new EMAC cases.
1746 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1747 handle Motorola MAC syntax.
1748 Allow disassembly of ColdFire V4e object files.
1750 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1752 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1754 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1756 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1758 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1760 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1762 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1764 * i386.h (i386_optab): Added xstore/xcrypt insns.
1766 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1768 * h8300.h (32bit ldc/stc): Add relaxing support.
1770 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1772 * h8300.h (BITOP): Pass MEMRELAX flag.
1774 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1776 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1779 For older changes see ChangeLog-9103
1781 Copyright (C) 2004-2012 Free Software Foundation, Inc.
1783 Copying and distribution of this file, with or without modification,
1784 are permitted in any medium without royalty provided the copyright
1785 notice and this notice are preserved.
1791 version-control: never