1 2010-10-09 Matt Rice <ratmice@gmail.com>
3 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
4 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
6 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
8 * arm.h (ARM_EXT_VIRT): New define.
9 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
10 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
13 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
15 * arm.h (ARM_AEXT_ADIV): New define.
16 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
18 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
20 * arm.h (ARM_EXT_OS): New define.
21 (ARM_AEXT_V6SM): Likewise.
22 (ARM_ARCH_V6SM): Likewise.
24 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
26 * arm.h (ARM_EXT_MP): Add.
27 (ARM_ARCH_V7A_MP): Likewise.
29 2010-09-22 Mike Frysinger <vapier@gentoo.org>
31 * bfin.h: Declare pseudoChr structs/defines.
33 2010-09-21 Mike Frysinger <vapier@gentoo.org>
35 * bfin.h: Strip trailing whitespace.
37 2010-07-29 DJ Delorie <dj@redhat.com>
39 * rx.h (RX_Operand_Type): Add TwoReg.
40 (RX_Opcode_ID): Remove ediv and ediv2.
42 2010-07-27 DJ Delorie <dj@redhat.com>
44 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
46 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
47 Ina Pandit <ina.pandit@kpitcummins.com>
49 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
50 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
52 Remove PROCESSOR_V850EA support.
53 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
54 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
55 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
56 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
57 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
59 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
61 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
64 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
66 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
67 (MIPS16_INSN_BRANCH): Rename to...
68 (MIPS16_INSN_COND_BRANCH): ... this.
70 2010-07-03 Alan Modra <amodra@gmail.com>
72 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
73 Renumber other PPC_OPCODE defines.
75 2010-07-03 Alan Modra <amodra@gmail.com>
77 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
79 2010-06-29 Alan Modra <amodra@gmail.com>
81 * maxq.h: Delete file.
83 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
85 * ppc.h (PPC_OPCODE_E500): Define.
87 2010-05-26 Catherine Moore <clm@codesourcery.com>
89 * opcode/mips.h (INSN_MIPS16): Remove.
91 2010-04-21 Joseph Myers <joseph@codesourcery.com>
93 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
95 2010-04-15 Nick Clifton <nickc@redhat.com>
97 * alpha.h: Update copyright notice to use GPLv3.
103 * convex.h: Likewise.
117 * m68hc11.h: Likewise.
123 * mn10200.h: Likewise.
124 * mn10300.h: Likewise.
125 * msp430.h: Likewise.
136 * score-datadep.h: Likewise.
137 * score-inst.h: Likewise.
139 * spu-insns.h: Likewise.
143 * tic54x.h: Likewise.
148 2010-03-25 Joseph Myers <joseph@codesourcery.com>
150 * tic6x-control-registers.h, tic6x-insn-formats.h,
151 tic6x-opcode-table.h, tic6x.h: New.
153 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
155 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
157 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
159 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
161 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
163 * ia64.h (ia64_find_opcode): Remove argument name.
164 (ia64_find_next_opcode): Likewise.
165 (ia64_dis_opcode): Likewise.
166 (ia64_free_opcode): Likewise.
167 (ia64_find_dependency): Likewise.
169 2009-11-22 Doug Evans <dje@sebabeach.org>
171 * cgen.h: Include bfd_stdint.h.
172 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
174 2009-11-18 Paul Brook <paul@codesourcery.com>
176 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
178 2009-11-17 Paul Brook <paul@codesourcery.com>
179 Daniel Jacobowitz <dan@codesourcery.com>
181 * arm.h (ARM_EXT_V6_DSP): Define.
182 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
183 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
185 2009-11-04 DJ Delorie <dj@redhat.com>
187 * rx.h (rx_decode_opcode) (mvtipl): Add.
188 (mvtcp, mvfcp, opecp): Remove.
190 2009-11-02 Paul Brook <paul@codesourcery.com>
192 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
193 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
194 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
195 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
196 FPU_ARCH_NEON_VFP_V4): Define.
198 2009-10-23 Doug Evans <dje@sebabeach.org>
200 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
201 * cgen.h: Update. Improve multi-inclusion macro name.
203 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
205 * ppc.h (PPC_OPCODE_476): Define.
207 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
209 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
211 2009-09-29 DJ Delorie <dj@redhat.com>
215 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
217 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
219 2009-09-21 Ben Elliston <bje@au.ibm.com>
221 * ppc.h (PPC_OPCODE_PPCA2): New.
223 2009-09-05 Martin Thuresson <martin@mtme.org>
225 * ia64.h (struct ia64_operand): Renamed member class to op_class.
227 2009-08-29 Martin Thuresson <martin@mtme.org>
229 * tic30.h (template): Rename type template to
230 insn_template. Updated code to use new name.
231 * tic54x.h (template): Rename type template to
234 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
236 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
238 2009-06-11 Anthony Green <green@moxielogic.com>
240 * moxie.h (MOXIE_F3_PCREL): Define.
241 (moxie_form3_opc_info): Grow.
243 2009-06-06 Anthony Green <green@moxielogic.com>
245 * moxie.h (MOXIE_F1_M): Define.
247 2009-04-15 Anthony Green <green@moxielogic.com>
251 2009-04-06 DJ Delorie <dj@redhat.com>
253 * h8300.h: Add relaxation attributes to MOVA opcodes.
255 2009-03-10 Alan Modra <amodra@bigpond.net.au>
257 * ppc.h (ppc_parse_cpu): Declare.
259 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
261 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
262 and _IMM11 for mbitclr and mbitset.
263 * score-datadep.h: Update dependency information.
265 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
267 * ppc.h (PPC_OPCODE_POWER7): New.
269 2009-02-06 Doug Evans <dje@google.com>
271 * i386.h: Add comment regarding sse* insns and prefixes.
273 2009-02-03 Sandip Matte <sandip@rmicorp.com>
275 * mips.h (INSN_XLR): Define.
276 (INSN_CHIP_MASK): Update.
278 (OPCODE_IS_MEMBER): Update.
279 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
281 2009-01-28 Doug Evans <dje@google.com>
283 * opcode/i386.h: Add multiple inclusion protection.
284 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
285 (EDI_REG_NUM): New macros.
286 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
287 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
288 (REX_PREFIX_P): New macro.
290 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
292 * ppc.h (struct powerpc_opcode): New field "deprecated".
293 (PPC_OPCODE_NOPOWER4): Delete.
295 2008-11-28 Joshua Kinard <kumba@gentoo.org>
297 * mips.h: Define CPU_R14000, CPU_R16000.
298 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
300 2008-11-18 Catherine Moore <clm@codesourcery.com>
302 * arm.h (FPU_NEON_FP16): New.
303 (FPU_ARCH_NEON_FP16): New.
305 2008-11-06 Chao-ying Fu <fu@mips.com>
307 * mips.h: Doucument '1' for 5-bit sync type.
309 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
311 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
314 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
316 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
318 2008-07-30 Michael J. Eager <eager@eagercon.com>
320 * ppc.h (PPC_OPCODE_405): Define.
321 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
323 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
325 * ppc.h (ppc_cpu_t): New typedef.
326 (struct powerpc_opcode <flags>): Use it.
327 (struct powerpc_operand <insert, extract>): Likewise.
328 (struct powerpc_macro <flags>): Likewise.
330 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
332 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
333 Update comment before MIPS16 field descriptors to mention MIPS16.
334 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
336 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
337 New bit masks and shift counts for cins and exts.
339 * mips.h: Document new field descriptors +Q.
340 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
342 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
344 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
345 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
347 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
349 * ppc.h: (PPC_OPCODE_E500MC): New.
351 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
353 * i386.h (MAX_OPERANDS): Set to 5.
354 (MAX_MNEM_SIZE): Changed to 20.
356 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
358 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
360 2008-03-09 Paul Brook <paul@codesourcery.com>
362 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
364 2008-03-04 Paul Brook <paul@codesourcery.com>
366 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
367 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
368 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
370 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
371 Nick Clifton <nickc@redhat.com>
374 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
375 with a 32-bit displacement but without the top bit of the 4th byte
378 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
380 * cr16.h (cr16_num_optab): Declared.
382 2008-02-14 Hakan Ardo <hakan@debian.org>
385 * avr.h (AVR_ISA_2xxe): Define.
387 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
389 * mips.h: Update copyright.
390 (INSN_CHIP_MASK): New macro.
391 (INSN_OCTEON): New macro.
392 (CPU_OCTEON): New macro.
393 (OPCODE_IS_MEMBER): Handle Octeon instructions.
395 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
397 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
399 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
401 * avr.h (AVR_ISA_USB162): Add new opcode set.
402 (AVR_ISA_AVR3): Likewise.
404 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
406 * mips.h (INSN_LOONGSON_2E): New.
407 (INSN_LOONGSON_2F): New.
408 (CPU_LOONGSON_2E): New.
409 (CPU_LOONGSON_2F): New.
410 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
412 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
414 * mips.h (INSN_ISA*): Redefine certain values as an
415 enumeration. Update comments.
416 (mips_isa_table): New.
417 (ISA_MIPS*): Redefine to match enumeration.
418 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
421 2007-08-08 Ben Elliston <bje@au.ibm.com>
423 * ppc.h (PPC_OPCODE_PPCPS): New.
425 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
427 * m68k.h: Document j K & E.
429 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
431 * cr16.h: New file for CR16 target.
433 2007-05-02 Alan Modra <amodra@bigpond.net.au>
435 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
437 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
439 * m68k.h (mcfisa_c): New.
440 (mcfusp, mcf_mask): Adjust.
442 2007-04-20 Alan Modra <amodra@bigpond.net.au>
444 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
445 (num_powerpc_operands): Declare.
446 (PPC_OPERAND_SIGNED et al): Redefine as hex.
447 (PPC_OPERAND_PLUS1): Define.
449 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
451 * i386.h (REX_MODE64): Renamed to ...
453 (REX_EXTX): Renamed to ...
455 (REX_EXTY): Renamed to ...
457 (REX_EXTZ): Renamed to ...
460 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
462 * i386.h: Add entries from config/tc-i386.h and move tables
463 to opcodes/i386-opc.h.
465 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
467 * i386.h (FloatDR): Removed.
468 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
470 2007-03-01 Alan Modra <amodra@bigpond.net.au>
472 * spu-insns.h: Add soma double-float insns.
474 2007-02-20 Thiemo Seufer <ths@mips.com>
475 Chao-Ying Fu <fu@mips.com>
477 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
478 (INSN_DSPR2): Add flag for DSP R2 instructions.
479 (M_BALIGN): New macro.
481 2007-02-14 Alan Modra <amodra@bigpond.net.au>
483 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
484 and Seg3ShortFrom with Shortform.
486 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
489 * i386.h (i386_optab): Put the real "test" before the pseudo
492 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
494 * m68k.h (m68010up): OR fido_a.
496 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
498 * m68k.h (fido_a): New.
500 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
502 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
503 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
506 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
508 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
510 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
512 * score-inst.h (enum score_insn_type): Add Insn_internal.
514 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
515 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
516 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
517 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
518 Alan Modra <amodra@bigpond.net.au>
520 * spu-insns.h: New file.
523 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
525 * ppc.h (PPC_OPCODE_CELL): Define.
527 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
529 * i386.h : Modify opcode to support for the change in POPCNT opcode
530 in amdfam10 architecture.
532 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
534 * i386.h: Replace CpuMNI with CpuSSSE3.
536 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
537 Joseph Myers <joseph@codesourcery.com>
538 Ian Lance Taylor <ian@wasabisystems.com>
539 Ben Elliston <bje@wasabisystems.com>
541 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
543 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
545 * score-datadep.h: New file.
546 * score-inst.h: New file.
548 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
550 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
551 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
554 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
555 Michael Meissner <michael.meissner@amd.com>
557 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
559 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
561 * i386.h (i386_optab): Add "nop" with memory reference.
563 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
565 * i386.h (i386_optab): Update comment for 64bit NOP.
567 2006-06-06 Ben Elliston <bje@au.ibm.com>
568 Anton Blanchard <anton@samba.org>
570 * ppc.h (PPC_OPCODE_POWER6): Define.
573 2006-06-05 Thiemo Seufer <ths@mips.com>
575 * mips.h: Improve description of MT flags.
577 2006-05-25 Richard Sandiford <richard@codesourcery.com>
579 * m68k.h (mcf_mask): Define.
581 2006-05-05 Thiemo Seufer <ths@mips.com>
582 David Ung <davidu@mips.com>
584 * mips.h (enum): Add macro M_CACHE_AB.
586 2006-05-04 Thiemo Seufer <ths@mips.com>
587 Nigel Stephens <nigel@mips.com>
588 David Ung <davidu@mips.com>
590 * mips.h: Add INSN_SMARTMIPS define.
592 2006-04-30 Thiemo Seufer <ths@mips.com>
593 David Ung <davidu@mips.com>
595 * mips.h: Defines udi bits and masks. Add description of
596 characters which may appear in the args field of udi
599 2006-04-26 Thiemo Seufer <ths@networkno.de>
601 * mips.h: Improve comments describing the bitfield instruction
604 2006-04-26 Julian Brown <julian@codesourcery.com>
606 * arm.h (FPU_VFP_EXT_V3): Define constant.
607 (FPU_NEON_EXT_V1): Likewise.
608 (FPU_VFP_HARD): Update.
609 (FPU_VFP_V3): Define macro.
610 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
612 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
614 * avr.h (AVR_ISA_PWMx): New.
616 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
618 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
619 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
620 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
621 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
622 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
624 2006-03-10 Paul Brook <paul@codesourcery.com>
626 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
628 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
630 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
631 first. Correct mask of bb "B" opcode.
633 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
635 * i386.h (i386_optab): Support Intel Merom New Instructions.
637 2006-02-24 Paul Brook <paul@codesourcery.com>
639 * arm.h: Add V7 feature bits.
641 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
643 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
645 2006-01-31 Paul Brook <paul@codesourcery.com>
646 Richard Earnshaw <rearnsha@arm.com>
648 * arm.h: Use ARM_CPU_FEATURE.
649 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
650 (arm_feature_set): Change to a structure.
651 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
652 ARM_FEATURE): New macros.
654 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
656 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
657 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
658 (ADD_PC_INCR_OPCODE): Don't define.
660 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
663 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
665 2005-11-14 David Ung <davidu@mips.com>
667 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
668 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
669 save/restore encoding of the args field.
671 2005-10-28 Dave Brolley <brolley@redhat.com>
673 Contribute the following changes:
674 2005-02-16 Dave Brolley <brolley@redhat.com>
676 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
677 cgen_isa_mask_* to cgen_bitset_*.
680 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
682 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
683 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
684 (CGEN_CPU_TABLE): Make isas a ponter.
686 2003-09-29 Dave Brolley <brolley@redhat.com>
688 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
689 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
690 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
692 2002-12-13 Dave Brolley <brolley@redhat.com>
694 * cgen.h (symcat.h): #include it.
695 (cgen-bitset.h): #include it.
696 (CGEN_ATTR_VALUE_TYPE): Now a union.
697 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
698 (CGEN_ATTR_ENTRY): 'value' now unsigned.
699 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
700 * cgen-bitset.h: New file.
702 2005-09-30 Catherine Moore <clm@cm00re.com>
706 2005-10-24 Jan Beulich <jbeulich@novell.com>
708 * ia64.h (enum ia64_opnd): Move memory operand out of set of
711 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
713 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
714 Add FLAG_STRICT to pa10 ftest opcode.
716 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
718 * hppa.h (pa_opcodes): Remove lha entries.
720 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
722 * hppa.h (FLAG_STRICT): Revise comment.
723 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
724 before corresponding pa11 opcodes. Add strict pa10 register-immediate
727 2005-09-30 Catherine Moore <clm@cm00re.com>
731 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
733 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
735 2005-09-06 Chao-ying Fu <fu@mips.com>
737 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
738 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
740 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
741 (INSN_ASE_MASK): Update to include INSN_MT.
742 (INSN_MT): New define for MT ASE.
744 2005-08-25 Chao-ying Fu <fu@mips.com>
746 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
747 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
748 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
749 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
750 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
751 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
753 (INSN_DSP): New define for DSP ASE.
755 2005-08-18 Alan Modra <amodra@bigpond.net.au>
759 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
761 * ppc.h (PPC_OPCODE_E300): Define.
763 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
765 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
767 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
770 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
773 2005-07-27 Jan Beulich <jbeulich@novell.com>
775 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
776 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
777 Add movq-s as 64-bit variants of movd-s.
779 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
781 * hppa.h: Fix punctuation in comment.
783 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
784 implicit space-register addressing. Set space-register bits on opcodes
785 using implicit space-register addressing. Add various missing pa20
786 long-immediate opcodes. Remove various opcodes using implicit 3-bit
787 space-register addressing. Use "fE" instead of "fe" in various
790 2005-07-18 Jan Beulich <jbeulich@novell.com>
792 * i386.h (i386_optab): Operands of aam and aad are unsigned.
794 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
796 * i386.h (i386_optab): Support Intel VMX Instructions.
798 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
800 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
802 2005-07-05 Jan Beulich <jbeulich@novell.com>
804 * i386.h (i386_optab): Add new insns.
806 2005-07-01 Nick Clifton <nickc@redhat.com>
808 * sparc.h: Add typedefs to structure declarations.
810 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
813 * i386.h (i386_optab): Update comments for 64bit addressing on
814 mov. Allow 64bit addressing for mov and movq.
816 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
818 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
819 respectively, in various floating-point load and store patterns.
821 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
823 * hppa.h (FLAG_STRICT): Correct comment.
824 (pa_opcodes): Update load and store entries to allow both PA 1.X and
825 PA 2.0 mneumonics when equivalent. Entries with cache control
826 completers now require PA 1.1. Adjust whitespace.
828 2005-05-19 Anton Blanchard <anton@samba.org>
830 * ppc.h (PPC_OPCODE_POWER5): Define.
832 2005-05-10 Nick Clifton <nickc@redhat.com>
834 * Update the address and phone number of the FSF organization in
835 the GPL notices in the following files:
836 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
837 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
838 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
839 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
840 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
841 tic54x.h, tic80.h, v850.h, vax.h
843 2005-05-09 Jan Beulich <jbeulich@novell.com>
845 * i386.h (i386_optab): Add ht and hnt.
847 2005-04-18 Mark Kettenis <kettenis@gnu.org>
849 * i386.h: Insert hyphens into selected VIA PadLock extensions.
850 Add xcrypt-ctr. Provide aliases without hyphens.
852 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
854 Moved from ../ChangeLog
856 2005-04-12 Paul Brook <paul@codesourcery.com>
857 * m88k.h: Rename psr macros to avoid conflicts.
859 2005-03-12 Zack Weinberg <zack@codesourcery.com>
860 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
861 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
864 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
865 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
866 Remove redundant instruction types.
867 (struct argument): X_op - new field.
868 (struct cst4_entry): Remove.
869 (no_op_insn): Declare.
871 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
872 * crx.h (enum argtype): Rename types, remove unused types.
874 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
875 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
876 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
877 (enum operand_type): Rearrange operands, edit comments.
878 replace us<N> with ui<N> for unsigned immediate.
879 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
880 displacements (respectively).
881 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
882 (instruction type): Add NO_TYPE_INS.
883 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
884 (operand_entry): New field - 'flags'.
885 (operand flags): New.
887 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
888 * crx.h (operand_type): Remove redundant types i3, i4,
890 Add new unsigned immediate types us3, us4, us5, us16.
892 2005-04-12 Mark Kettenis <kettenis@gnu.org>
894 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
895 adjust them accordingly.
897 2005-04-01 Jan Beulich <jbeulich@novell.com>
899 * i386.h (i386_optab): Add rdtscp.
901 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
903 * i386.h (i386_optab): Don't allow the `l' suffix for moving
904 between memory and segment register. Allow movq for moving between
905 general-purpose register and segment register.
907 2005-02-09 Jan Beulich <jbeulich@novell.com>
910 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
911 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
914 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
916 * m68k.h (m68008, m68ec030, m68882): Remove.
918 (cpu_m68k, cpu_cf): New.
919 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
920 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
922 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
924 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
925 * cgen.h (enum cgen_parse_operand_type): Add
926 CGEN_PARSE_OPERAND_SYMBOLIC.
928 2005-01-21 Fred Fish <fnf@specifixinc.com>
930 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
931 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
932 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
934 2005-01-19 Fred Fish <fnf@specifixinc.com>
936 * mips.h (struct mips_opcode): Add new pinfo2 member.
937 (INSN_ALIAS): New define for opcode table entries that are
938 specific instances of another entry, such as 'move' for an 'or'
940 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
941 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
943 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
945 * mips.h (CPU_RM9000): Define.
946 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
948 2004-11-25 Jan Beulich <jbeulich@novell.com>
950 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
951 to/from test registers are illegal in 64-bit mode. Add missing
952 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
953 (previously one had to explicitly encode a rex64 prefix). Re-enable
954 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
955 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
957 2004-11-23 Jan Beulich <jbeulich@novell.com>
959 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
960 available only with SSE2. Change the MMX additions introduced by SSE
961 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
962 instructions by their now designated identifier (since combining i686
963 and 3DNow! does not really imply 3DNow!A).
965 2004-11-19 Alan Modra <amodra@bigpond.net.au>
967 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
968 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
970 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
971 Vineet Sharma <vineets@noida.hcltech.com>
973 * maxq.h: New file: Disassembly information for the maxq port.
975 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
977 * i386.h (i386_optab): Put back "movzb".
979 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
981 * cris.h (enum cris_insn_version_usage): Tweak formatting and
982 comments. Remove member cris_ver_sim. Add members
983 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
984 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
985 (struct cris_support_reg, struct cris_cond15): New types.
986 (cris_conds15): Declare.
987 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
988 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
989 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
990 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
991 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
994 2004-11-04 Jan Beulich <jbeulich@novell.com>
996 * i386.h (sldx_Suf): Remove.
997 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
998 (q_FP): Define, implying no REX64.
999 (x_FP, sl_FP): Imply FloatMF.
1000 (i386_optab): Split reg and mem forms of moving from segment registers
1001 so that the memory forms can ignore the 16-/32-bit operand size
1002 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1003 all non-floating-point instructions. Unite 32- and 64-bit forms of
1004 movsx, movzx, and movd. Adjust floating point operations for the above
1005 changes to the *FP macros. Add DefaultSize to floating point control
1006 insns operating on larger memory ranges. Remove left over comments
1007 hinting at certain insns being Intel-syntax ones where the ones
1008 actually meant are already gone.
1010 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1012 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1015 2004-09-30 Paul Brook <paul@codesourcery.com>
1017 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1018 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1020 2004-09-11 Theodore A. Roth <troth@openavr.org>
1022 * avr.h: Add support for
1023 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1025 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1027 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1029 2004-08-24 Dmitry Diky <diwil@spec.ru>
1031 * msp430.h (msp430_opc): Add new instructions.
1032 (msp430_rcodes): Declare new instructions.
1033 (msp430_hcodes): Likewise..
1035 2004-08-13 Nick Clifton <nickc@redhat.com>
1038 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1041 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1043 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1045 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1047 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1049 2004-07-21 Jan Beulich <jbeulich@novell.com>
1051 * i386.h: Adjust instruction descriptions to better match the
1054 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
1056 * arm.h: Remove all old content. Replace with architecture defines
1057 from gas/config/tc-arm.c.
1059 2004-07-09 Andreas Schwab <schwab@suse.de>
1061 * m68k.h: Fix comment.
1063 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1067 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1069 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1071 2004-05-24 Peter Barada <peter@the-baradas.com>
1073 * m68k.h: Add 'size' to m68k_opcode.
1075 2004-05-05 Peter Barada <peter@the-baradas.com>
1077 * m68k.h: Switch from ColdFire chip name to core variant.
1079 2004-04-22 Peter Barada <peter@the-baradas.com>
1081 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1082 descriptions for new EMAC cases.
1083 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1084 handle Motorola MAC syntax.
1085 Allow disassembly of ColdFire V4e object files.
1087 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1089 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1091 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1093 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1095 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1097 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1099 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1101 * i386.h (i386_optab): Added xstore/xcrypt insns.
1103 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1105 * h8300.h (32bit ldc/stc): Add relaxing support.
1107 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1109 * h8300.h (BITOP): Pass MEMRELAX flag.
1111 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1113 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1116 For older changes see ChangeLog-9103
1122 version-control: never