1 2011-12-08 Andrew Pinski <apinski@cavium.com>
2 Adam Nemet <anemet@caviumnetworks.com>
4 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
5 (INSN_OCTEON2): New macro.
6 (CPU_OCTEON2): New macro.
7 (OPCODE_IS_MEMBER): Add Octeon2.
9 2011-11-29 Andrew Pinski <apinski@cavium.com>
11 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
12 (INSN_OCTEONP): New macro.
13 (CPU_OCTEONP): New macro.
14 (OPCODE_IS_MEMBER): Add Octeon+.
15 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
17 2011-11-01 DJ Delorie <dj@redhat.com>
21 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
23 * mips.h: Fix a typo in description.
25 2011-09-21 David S. Miller <davem@davemloft.net>
27 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
28 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
29 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
30 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
32 2011-08-09 Chao-ying Fu <fu@mips.com>
33 Maciej W. Rozycki <macro@codesourcery.com>
35 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
36 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
37 (INSN_ASE_MASK): Add the MCU bit.
38 (INSN_MCU): New macro.
39 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
40 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
42 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
44 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
45 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
46 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
47 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
48 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
49 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
50 (INSN2_READ_GPR_MMN): Likewise.
51 (INSN2_READ_FPR_D): Change the bit used.
52 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
53 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
54 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
55 (INSN2_COND_BRANCH): Likewise.
56 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
57 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
58 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
59 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
60 (INSN2_MOD_GPR_MN): Likewise.
62 2011-08-05 David S. Miller <davem@davemloft.net>
64 * sparc.h: Document new format codes '4', '5', and '('.
65 (OPF_LOW4, RS3): New macros.
67 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
69 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
70 order of flags documented.
72 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
74 * mips.h: Clarify the description of microMIPS instruction
76 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
78 2011-07-24 Chao-ying Fu <fu@mips.com>
79 Maciej W. Rozycki <macro@codesourcery.com>
81 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
82 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
83 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
84 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
85 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
86 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
87 (OP_MASK_RS3, OP_SH_RS3): Likewise.
88 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
89 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
90 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
91 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
92 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
93 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
94 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
95 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
96 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
97 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
98 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
99 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
100 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
101 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
102 (INSN_WRITE_GPR_S): New macro.
103 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
104 (INSN2_READ_FPR_D): Likewise.
105 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
106 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
107 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
108 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
109 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
110 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
111 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
112 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
113 (CPU_MICROMIPS): New macro.
114 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
115 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
116 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
117 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
118 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
119 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
120 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
121 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
122 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
123 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
124 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
125 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
126 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
127 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
128 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
129 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
130 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
131 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
132 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
133 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
134 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
135 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
136 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
137 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
138 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
139 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
140 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
141 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
142 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
143 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
144 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
145 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
146 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
147 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
148 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
149 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
150 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
151 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
152 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
153 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
154 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
155 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
156 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
157 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
158 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
159 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
160 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
161 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
162 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
163 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
164 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
165 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
166 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
167 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
168 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
169 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
170 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
171 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
172 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
173 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
174 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
175 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
176 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
177 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
178 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
179 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
180 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
181 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
182 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
183 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
184 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
185 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
186 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
187 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
188 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
189 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
190 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
191 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
192 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
193 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
194 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
195 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
196 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
197 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
198 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
199 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
200 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
201 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
202 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
203 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
204 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
205 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
206 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
207 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
208 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
209 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
210 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
211 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
212 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
213 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
214 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
215 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
216 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
217 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
218 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
219 (micromips_opcodes): New declaration.
220 (bfd_micromips_num_opcodes): Likewise.
222 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
224 * mips.h (INSN_TRAP): Rename to...
225 (INSN_NO_DELAY_SLOT): ... this.
226 (INSN_SYNC): Remove macro.
228 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
230 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
231 a duplicate of AVR_ISA_SPM.
233 2011-07-01 Nick Clifton <nickc@redhat.com>
235 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
237 2011-06-18 Robin Getz <robin.getz@analog.com>
239 * bfin.h (is_macmod_signed): New func
241 2011-06-18 Mike Frysinger <vapier@gentoo.org>
243 * bfin.h (is_macmod_pmove): Add missing space before func args.
244 (is_macmod_hmove): Likewise.
246 2011-06-13 Walter Lee <walt@tilera.com>
248 * tilegx.h: New file.
249 * tilepro.h: New file.
251 2011-05-31 Paul Brook <paul@codesourcery.com>
253 * arm.h (ARM_ARCH_V7R_IDIV): Define.
255 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
257 * s390.h: Replace S390_OPERAND_REG_EVEN with
258 S390_OPERAND_REG_PAIR.
260 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
262 * s390.h: Add S390_OPCODE_REG_EVEN flag.
264 2011-04-18 Julian Brown <julian@codesourcery.com>
266 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
268 2011-04-11 Dan McDonald <dan@wellkeeper.com>
271 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
273 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
275 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
276 New instruction set flags.
277 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
279 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
281 * mips.h (M_PREF_AB): New enum value.
283 2011-02-12 Mike Frysinger <vapier@gentoo.org>
285 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
287 (is_macmod_pmove, is_macmod_hmove): New functions.
289 2011-02-11 Mike Frysinger <vapier@gentoo.org>
291 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
293 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
295 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
296 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
298 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
301 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
304 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
307 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
309 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
311 * mips.h: Update commentary after last commit.
313 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
315 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
316 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
317 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
319 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
321 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
323 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
325 * mips.h: Fix previous commit.
327 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
329 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
330 (INSN_LOONGSON_3A): Clear bit 31.
332 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
335 * arm.h (ARM_AEXT_V6M_ONLY): New define.
336 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
337 (ARM_ARCH_V6M_ONLY): New define.
339 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
341 * mips.h (INSN_LOONGSON_3A): Defined.
342 (CPU_LOONGSON_3A): Defined.
343 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
345 2010-10-09 Matt Rice <ratmice@gmail.com>
347 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
348 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
350 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
352 * arm.h (ARM_EXT_VIRT): New define.
353 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
354 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
357 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
359 * arm.h (ARM_AEXT_ADIV): New define.
360 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
362 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
364 * arm.h (ARM_EXT_OS): New define.
365 (ARM_AEXT_V6SM): Likewise.
366 (ARM_ARCH_V6SM): Likewise.
368 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
370 * arm.h (ARM_EXT_MP): Add.
371 (ARM_ARCH_V7A_MP): Likewise.
373 2010-09-22 Mike Frysinger <vapier@gentoo.org>
375 * bfin.h: Declare pseudoChr structs/defines.
377 2010-09-21 Mike Frysinger <vapier@gentoo.org>
379 * bfin.h: Strip trailing whitespace.
381 2010-07-29 DJ Delorie <dj@redhat.com>
383 * rx.h (RX_Operand_Type): Add TwoReg.
384 (RX_Opcode_ID): Remove ediv and ediv2.
386 2010-07-27 DJ Delorie <dj@redhat.com>
388 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
390 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
391 Ina Pandit <ina.pandit@kpitcummins.com>
393 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
394 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
395 PROCESSOR_V850E2_ALL.
396 Remove PROCESSOR_V850EA support.
397 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
398 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
399 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
400 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
401 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
402 V850_OPERAND_PERCENT.
403 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
405 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
408 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
410 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
411 (MIPS16_INSN_BRANCH): Rename to...
412 (MIPS16_INSN_COND_BRANCH): ... this.
414 2010-07-03 Alan Modra <amodra@gmail.com>
416 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
417 Renumber other PPC_OPCODE defines.
419 2010-07-03 Alan Modra <amodra@gmail.com>
421 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
423 2010-06-29 Alan Modra <amodra@gmail.com>
425 * maxq.h: Delete file.
427 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
429 * ppc.h (PPC_OPCODE_E500): Define.
431 2010-05-26 Catherine Moore <clm@codesourcery.com>
433 * opcode/mips.h (INSN_MIPS16): Remove.
435 2010-04-21 Joseph Myers <joseph@codesourcery.com>
437 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
439 2010-04-15 Nick Clifton <nickc@redhat.com>
441 * alpha.h: Update copyright notice to use GPLv3.
447 * convex.h: Likewise.
461 * m68hc11.h: Likewise.
467 * mn10200.h: Likewise.
468 * mn10300.h: Likewise.
469 * msp430.h: Likewise.
480 * score-datadep.h: Likewise.
481 * score-inst.h: Likewise.
483 * spu-insns.h: Likewise.
487 * tic54x.h: Likewise.
492 2010-03-25 Joseph Myers <joseph@codesourcery.com>
494 * tic6x-control-registers.h, tic6x-insn-formats.h,
495 tic6x-opcode-table.h, tic6x.h: New.
497 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
499 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
501 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
503 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
505 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
507 * ia64.h (ia64_find_opcode): Remove argument name.
508 (ia64_find_next_opcode): Likewise.
509 (ia64_dis_opcode): Likewise.
510 (ia64_free_opcode): Likewise.
511 (ia64_find_dependency): Likewise.
513 2009-11-22 Doug Evans <dje@sebabeach.org>
515 * cgen.h: Include bfd_stdint.h.
516 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
518 2009-11-18 Paul Brook <paul@codesourcery.com>
520 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
522 2009-11-17 Paul Brook <paul@codesourcery.com>
523 Daniel Jacobowitz <dan@codesourcery.com>
525 * arm.h (ARM_EXT_V6_DSP): Define.
526 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
527 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
529 2009-11-04 DJ Delorie <dj@redhat.com>
531 * rx.h (rx_decode_opcode) (mvtipl): Add.
532 (mvtcp, mvfcp, opecp): Remove.
534 2009-11-02 Paul Brook <paul@codesourcery.com>
536 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
537 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
538 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
539 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
540 FPU_ARCH_NEON_VFP_V4): Define.
542 2009-10-23 Doug Evans <dje@sebabeach.org>
544 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
545 * cgen.h: Update. Improve multi-inclusion macro name.
547 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
549 * ppc.h (PPC_OPCODE_476): Define.
551 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
553 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
555 2009-09-29 DJ Delorie <dj@redhat.com>
559 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
561 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
563 2009-09-21 Ben Elliston <bje@au.ibm.com>
565 * ppc.h (PPC_OPCODE_PPCA2): New.
567 2009-09-05 Martin Thuresson <martin@mtme.org>
569 * ia64.h (struct ia64_operand): Renamed member class to op_class.
571 2009-08-29 Martin Thuresson <martin@mtme.org>
573 * tic30.h (template): Rename type template to
574 insn_template. Updated code to use new name.
575 * tic54x.h (template): Rename type template to
578 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
580 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
582 2009-06-11 Anthony Green <green@moxielogic.com>
584 * moxie.h (MOXIE_F3_PCREL): Define.
585 (moxie_form3_opc_info): Grow.
587 2009-06-06 Anthony Green <green@moxielogic.com>
589 * moxie.h (MOXIE_F1_M): Define.
591 2009-04-15 Anthony Green <green@moxielogic.com>
595 2009-04-06 DJ Delorie <dj@redhat.com>
597 * h8300.h: Add relaxation attributes to MOVA opcodes.
599 2009-03-10 Alan Modra <amodra@bigpond.net.au>
601 * ppc.h (ppc_parse_cpu): Declare.
603 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
605 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
606 and _IMM11 for mbitclr and mbitset.
607 * score-datadep.h: Update dependency information.
609 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
611 * ppc.h (PPC_OPCODE_POWER7): New.
613 2009-02-06 Doug Evans <dje@google.com>
615 * i386.h: Add comment regarding sse* insns and prefixes.
617 2009-02-03 Sandip Matte <sandip@rmicorp.com>
619 * mips.h (INSN_XLR): Define.
620 (INSN_CHIP_MASK): Update.
622 (OPCODE_IS_MEMBER): Update.
623 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
625 2009-01-28 Doug Evans <dje@google.com>
627 * opcode/i386.h: Add multiple inclusion protection.
628 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
629 (EDI_REG_NUM): New macros.
630 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
631 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
632 (REX_PREFIX_P): New macro.
634 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
636 * ppc.h (struct powerpc_opcode): New field "deprecated".
637 (PPC_OPCODE_NOPOWER4): Delete.
639 2008-11-28 Joshua Kinard <kumba@gentoo.org>
641 * mips.h: Define CPU_R14000, CPU_R16000.
642 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
644 2008-11-18 Catherine Moore <clm@codesourcery.com>
646 * arm.h (FPU_NEON_FP16): New.
647 (FPU_ARCH_NEON_FP16): New.
649 2008-11-06 Chao-ying Fu <fu@mips.com>
651 * mips.h: Doucument '1' for 5-bit sync type.
653 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
655 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
658 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
660 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
662 2008-07-30 Michael J. Eager <eager@eagercon.com>
664 * ppc.h (PPC_OPCODE_405): Define.
665 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
667 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
669 * ppc.h (ppc_cpu_t): New typedef.
670 (struct powerpc_opcode <flags>): Use it.
671 (struct powerpc_operand <insert, extract>): Likewise.
672 (struct powerpc_macro <flags>): Likewise.
674 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
676 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
677 Update comment before MIPS16 field descriptors to mention MIPS16.
678 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
680 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
681 New bit masks and shift counts for cins and exts.
683 * mips.h: Document new field descriptors +Q.
684 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
686 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
688 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
689 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
691 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
693 * ppc.h: (PPC_OPCODE_E500MC): New.
695 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
697 * i386.h (MAX_OPERANDS): Set to 5.
698 (MAX_MNEM_SIZE): Changed to 20.
700 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
702 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
704 2008-03-09 Paul Brook <paul@codesourcery.com>
706 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
708 2008-03-04 Paul Brook <paul@codesourcery.com>
710 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
711 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
712 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
714 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
715 Nick Clifton <nickc@redhat.com>
718 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
719 with a 32-bit displacement but without the top bit of the 4th byte
722 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
724 * cr16.h (cr16_num_optab): Declared.
726 2008-02-14 Hakan Ardo <hakan@debian.org>
729 * avr.h (AVR_ISA_2xxe): Define.
731 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
733 * mips.h: Update copyright.
734 (INSN_CHIP_MASK): New macro.
735 (INSN_OCTEON): New macro.
736 (CPU_OCTEON): New macro.
737 (OPCODE_IS_MEMBER): Handle Octeon instructions.
739 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
741 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
743 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
745 * avr.h (AVR_ISA_USB162): Add new opcode set.
746 (AVR_ISA_AVR3): Likewise.
748 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
750 * mips.h (INSN_LOONGSON_2E): New.
751 (INSN_LOONGSON_2F): New.
752 (CPU_LOONGSON_2E): New.
753 (CPU_LOONGSON_2F): New.
754 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
756 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
758 * mips.h (INSN_ISA*): Redefine certain values as an
759 enumeration. Update comments.
760 (mips_isa_table): New.
761 (ISA_MIPS*): Redefine to match enumeration.
762 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
765 2007-08-08 Ben Elliston <bje@au.ibm.com>
767 * ppc.h (PPC_OPCODE_PPCPS): New.
769 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
771 * m68k.h: Document j K & E.
773 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
775 * cr16.h: New file for CR16 target.
777 2007-05-02 Alan Modra <amodra@bigpond.net.au>
779 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
781 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
783 * m68k.h (mcfisa_c): New.
784 (mcfusp, mcf_mask): Adjust.
786 2007-04-20 Alan Modra <amodra@bigpond.net.au>
788 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
789 (num_powerpc_operands): Declare.
790 (PPC_OPERAND_SIGNED et al): Redefine as hex.
791 (PPC_OPERAND_PLUS1): Define.
793 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
795 * i386.h (REX_MODE64): Renamed to ...
797 (REX_EXTX): Renamed to ...
799 (REX_EXTY): Renamed to ...
801 (REX_EXTZ): Renamed to ...
804 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
806 * i386.h: Add entries from config/tc-i386.h and move tables
807 to opcodes/i386-opc.h.
809 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
811 * i386.h (FloatDR): Removed.
812 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
814 2007-03-01 Alan Modra <amodra@bigpond.net.au>
816 * spu-insns.h: Add soma double-float insns.
818 2007-02-20 Thiemo Seufer <ths@mips.com>
819 Chao-Ying Fu <fu@mips.com>
821 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
822 (INSN_DSPR2): Add flag for DSP R2 instructions.
823 (M_BALIGN): New macro.
825 2007-02-14 Alan Modra <amodra@bigpond.net.au>
827 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
828 and Seg3ShortFrom with Shortform.
830 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
833 * i386.h (i386_optab): Put the real "test" before the pseudo
836 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
838 * m68k.h (m68010up): OR fido_a.
840 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
842 * m68k.h (fido_a): New.
844 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
846 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
847 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
850 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
852 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
854 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
856 * score-inst.h (enum score_insn_type): Add Insn_internal.
858 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
859 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
860 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
861 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
862 Alan Modra <amodra@bigpond.net.au>
864 * spu-insns.h: New file.
867 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
869 * ppc.h (PPC_OPCODE_CELL): Define.
871 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
873 * i386.h : Modify opcode to support for the change in POPCNT opcode
874 in amdfam10 architecture.
876 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
878 * i386.h: Replace CpuMNI with CpuSSSE3.
880 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
881 Joseph Myers <joseph@codesourcery.com>
882 Ian Lance Taylor <ian@wasabisystems.com>
883 Ben Elliston <bje@wasabisystems.com>
885 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
887 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
889 * score-datadep.h: New file.
890 * score-inst.h: New file.
892 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
894 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
895 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
898 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
899 Michael Meissner <michael.meissner@amd.com>
901 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
903 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
905 * i386.h (i386_optab): Add "nop" with memory reference.
907 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
909 * i386.h (i386_optab): Update comment for 64bit NOP.
911 2006-06-06 Ben Elliston <bje@au.ibm.com>
912 Anton Blanchard <anton@samba.org>
914 * ppc.h (PPC_OPCODE_POWER6): Define.
917 2006-06-05 Thiemo Seufer <ths@mips.com>
919 * mips.h: Improve description of MT flags.
921 2006-05-25 Richard Sandiford <richard@codesourcery.com>
923 * m68k.h (mcf_mask): Define.
925 2006-05-05 Thiemo Seufer <ths@mips.com>
926 David Ung <davidu@mips.com>
928 * mips.h (enum): Add macro M_CACHE_AB.
930 2006-05-04 Thiemo Seufer <ths@mips.com>
931 Nigel Stephens <nigel@mips.com>
932 David Ung <davidu@mips.com>
934 * mips.h: Add INSN_SMARTMIPS define.
936 2006-04-30 Thiemo Seufer <ths@mips.com>
937 David Ung <davidu@mips.com>
939 * mips.h: Defines udi bits and masks. Add description of
940 characters which may appear in the args field of udi
943 2006-04-26 Thiemo Seufer <ths@networkno.de>
945 * mips.h: Improve comments describing the bitfield instruction
948 2006-04-26 Julian Brown <julian@codesourcery.com>
950 * arm.h (FPU_VFP_EXT_V3): Define constant.
951 (FPU_NEON_EXT_V1): Likewise.
952 (FPU_VFP_HARD): Update.
953 (FPU_VFP_V3): Define macro.
954 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
956 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
958 * avr.h (AVR_ISA_PWMx): New.
960 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
962 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
963 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
964 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
965 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
966 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
968 2006-03-10 Paul Brook <paul@codesourcery.com>
970 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
972 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
974 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
975 first. Correct mask of bb "B" opcode.
977 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
979 * i386.h (i386_optab): Support Intel Merom New Instructions.
981 2006-02-24 Paul Brook <paul@codesourcery.com>
983 * arm.h: Add V7 feature bits.
985 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
987 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
989 2006-01-31 Paul Brook <paul@codesourcery.com>
990 Richard Earnshaw <rearnsha@arm.com>
992 * arm.h: Use ARM_CPU_FEATURE.
993 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
994 (arm_feature_set): Change to a structure.
995 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
996 ARM_FEATURE): New macros.
998 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
1000 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1001 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1002 (ADD_PC_INCR_OPCODE): Don't define.
1004 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1007 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1009 2005-11-14 David Ung <davidu@mips.com>
1011 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1012 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1013 save/restore encoding of the args field.
1015 2005-10-28 Dave Brolley <brolley@redhat.com>
1017 Contribute the following changes:
1018 2005-02-16 Dave Brolley <brolley@redhat.com>
1020 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1021 cgen_isa_mask_* to cgen_bitset_*.
1024 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1026 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1027 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1028 (CGEN_CPU_TABLE): Make isas a ponter.
1030 2003-09-29 Dave Brolley <brolley@redhat.com>
1032 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1033 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1034 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1036 2002-12-13 Dave Brolley <brolley@redhat.com>
1038 * cgen.h (symcat.h): #include it.
1039 (cgen-bitset.h): #include it.
1040 (CGEN_ATTR_VALUE_TYPE): Now a union.
1041 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1042 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1043 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1044 * cgen-bitset.h: New file.
1046 2005-09-30 Catherine Moore <clm@cm00re.com>
1050 2005-10-24 Jan Beulich <jbeulich@novell.com>
1052 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1055 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1057 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1058 Add FLAG_STRICT to pa10 ftest opcode.
1060 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1062 * hppa.h (pa_opcodes): Remove lha entries.
1064 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1066 * hppa.h (FLAG_STRICT): Revise comment.
1067 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1068 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1071 2005-09-30 Catherine Moore <clm@cm00re.com>
1075 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1077 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1079 2005-09-06 Chao-ying Fu <fu@mips.com>
1081 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1082 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1084 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1085 (INSN_ASE_MASK): Update to include INSN_MT.
1086 (INSN_MT): New define for MT ASE.
1088 2005-08-25 Chao-ying Fu <fu@mips.com>
1090 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1091 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1092 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1093 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1094 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1095 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1097 (INSN_DSP): New define for DSP ASE.
1099 2005-08-18 Alan Modra <amodra@bigpond.net.au>
1103 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1105 * ppc.h (PPC_OPCODE_E300): Define.
1107 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1109 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1111 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1114 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1117 2005-07-27 Jan Beulich <jbeulich@novell.com>
1119 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1120 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1121 Add movq-s as 64-bit variants of movd-s.
1123 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1125 * hppa.h: Fix punctuation in comment.
1127 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1128 implicit space-register addressing. Set space-register bits on opcodes
1129 using implicit space-register addressing. Add various missing pa20
1130 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1131 space-register addressing. Use "fE" instead of "fe" in various
1134 2005-07-18 Jan Beulich <jbeulich@novell.com>
1136 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1138 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1140 * i386.h (i386_optab): Support Intel VMX Instructions.
1142 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1144 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1146 2005-07-05 Jan Beulich <jbeulich@novell.com>
1148 * i386.h (i386_optab): Add new insns.
1150 2005-07-01 Nick Clifton <nickc@redhat.com>
1152 * sparc.h: Add typedefs to structure declarations.
1154 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1157 * i386.h (i386_optab): Update comments for 64bit addressing on
1158 mov. Allow 64bit addressing for mov and movq.
1160 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1162 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1163 respectively, in various floating-point load and store patterns.
1165 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1167 * hppa.h (FLAG_STRICT): Correct comment.
1168 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1169 PA 2.0 mneumonics when equivalent. Entries with cache control
1170 completers now require PA 1.1. Adjust whitespace.
1172 2005-05-19 Anton Blanchard <anton@samba.org>
1174 * ppc.h (PPC_OPCODE_POWER5): Define.
1176 2005-05-10 Nick Clifton <nickc@redhat.com>
1178 * Update the address and phone number of the FSF organization in
1179 the GPL notices in the following files:
1180 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1181 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1182 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1183 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1184 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1185 tic54x.h, tic80.h, v850.h, vax.h
1187 2005-05-09 Jan Beulich <jbeulich@novell.com>
1189 * i386.h (i386_optab): Add ht and hnt.
1191 2005-04-18 Mark Kettenis <kettenis@gnu.org>
1193 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1194 Add xcrypt-ctr. Provide aliases without hyphens.
1196 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1198 Moved from ../ChangeLog
1200 2005-04-12 Paul Brook <paul@codesourcery.com>
1201 * m88k.h: Rename psr macros to avoid conflicts.
1203 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1204 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1205 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1206 and ARM_ARCH_V6ZKT2.
1208 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1209 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1210 Remove redundant instruction types.
1211 (struct argument): X_op - new field.
1212 (struct cst4_entry): Remove.
1213 (no_op_insn): Declare.
1215 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1216 * crx.h (enum argtype): Rename types, remove unused types.
1218 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1219 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1220 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1221 (enum operand_type): Rearrange operands, edit comments.
1222 replace us<N> with ui<N> for unsigned immediate.
1223 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1224 displacements (respectively).
1225 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1226 (instruction type): Add NO_TYPE_INS.
1227 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1228 (operand_entry): New field - 'flags'.
1229 (operand flags): New.
1231 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1232 * crx.h (operand_type): Remove redundant types i3, i4,
1234 Add new unsigned immediate types us3, us4, us5, us16.
1236 2005-04-12 Mark Kettenis <kettenis@gnu.org>
1238 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1239 adjust them accordingly.
1241 2005-04-01 Jan Beulich <jbeulich@novell.com>
1243 * i386.h (i386_optab): Add rdtscp.
1245 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1247 * i386.h (i386_optab): Don't allow the `l' suffix for moving
1248 between memory and segment register. Allow movq for moving between
1249 general-purpose register and segment register.
1251 2005-02-09 Jan Beulich <jbeulich@novell.com>
1254 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1255 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1258 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1260 * m68k.h (m68008, m68ec030, m68882): Remove.
1262 (cpu_m68k, cpu_cf): New.
1263 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1264 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1266 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
1268 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1269 * cgen.h (enum cgen_parse_operand_type): Add
1270 CGEN_PARSE_OPERAND_SYMBOLIC.
1272 2005-01-21 Fred Fish <fnf@specifixinc.com>
1274 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1275 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1276 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1278 2005-01-19 Fred Fish <fnf@specifixinc.com>
1280 * mips.h (struct mips_opcode): Add new pinfo2 member.
1281 (INSN_ALIAS): New define for opcode table entries that are
1282 specific instances of another entry, such as 'move' for an 'or'
1283 with a zero operand.
1284 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1285 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1287 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1289 * mips.h (CPU_RM9000): Define.
1290 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1292 2004-11-25 Jan Beulich <jbeulich@novell.com>
1294 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1295 to/from test registers are illegal in 64-bit mode. Add missing
1296 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1297 (previously one had to explicitly encode a rex64 prefix). Re-enable
1298 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1299 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1301 2004-11-23 Jan Beulich <jbeulich@novell.com>
1303 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1304 available only with SSE2. Change the MMX additions introduced by SSE
1305 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1306 instructions by their now designated identifier (since combining i686
1307 and 3DNow! does not really imply 3DNow!A).
1309 2004-11-19 Alan Modra <amodra@bigpond.net.au>
1311 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1312 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1314 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1315 Vineet Sharma <vineets@noida.hcltech.com>
1317 * maxq.h: New file: Disassembly information for the maxq port.
1319 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1321 * i386.h (i386_optab): Put back "movzb".
1323 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
1325 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1326 comments. Remove member cris_ver_sim. Add members
1327 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1328 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1329 (struct cris_support_reg, struct cris_cond15): New types.
1330 (cris_conds15): Declare.
1331 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1332 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1333 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1334 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1335 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1336 SIZE_FIELD_UNSIGNED.
1338 2004-11-04 Jan Beulich <jbeulich@novell.com>
1340 * i386.h (sldx_Suf): Remove.
1341 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1342 (q_FP): Define, implying no REX64.
1343 (x_FP, sl_FP): Imply FloatMF.
1344 (i386_optab): Split reg and mem forms of moving from segment registers
1345 so that the memory forms can ignore the 16-/32-bit operand size
1346 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1347 all non-floating-point instructions. Unite 32- and 64-bit forms of
1348 movsx, movzx, and movd. Adjust floating point operations for the above
1349 changes to the *FP macros. Add DefaultSize to floating point control
1350 insns operating on larger memory ranges. Remove left over comments
1351 hinting at certain insns being Intel-syntax ones where the ones
1352 actually meant are already gone.
1354 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1356 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1359 2004-09-30 Paul Brook <paul@codesourcery.com>
1361 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1362 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1364 2004-09-11 Theodore A. Roth <troth@openavr.org>
1366 * avr.h: Add support for
1367 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1369 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1371 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1373 2004-08-24 Dmitry Diky <diwil@spec.ru>
1375 * msp430.h (msp430_opc): Add new instructions.
1376 (msp430_rcodes): Declare new instructions.
1377 (msp430_hcodes): Likewise..
1379 2004-08-13 Nick Clifton <nickc@redhat.com>
1382 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1385 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1387 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1389 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1391 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1393 2004-07-21 Jan Beulich <jbeulich@novell.com>
1395 * i386.h: Adjust instruction descriptions to better match the
1398 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
1400 * arm.h: Remove all old content. Replace with architecture defines
1401 from gas/config/tc-arm.c.
1403 2004-07-09 Andreas Schwab <schwab@suse.de>
1405 * m68k.h: Fix comment.
1407 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1411 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1413 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1415 2004-05-24 Peter Barada <peter@the-baradas.com>
1417 * m68k.h: Add 'size' to m68k_opcode.
1419 2004-05-05 Peter Barada <peter@the-baradas.com>
1421 * m68k.h: Switch from ColdFire chip name to core variant.
1423 2004-04-22 Peter Barada <peter@the-baradas.com>
1425 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1426 descriptions for new EMAC cases.
1427 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1428 handle Motorola MAC syntax.
1429 Allow disassembly of ColdFire V4e object files.
1431 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1433 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1435 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1437 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1439 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1441 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1443 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1445 * i386.h (i386_optab): Added xstore/xcrypt insns.
1447 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1449 * h8300.h (32bit ldc/stc): Add relaxing support.
1451 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1453 * h8300.h (BITOP): Pass MEMRELAX flag.
1455 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1457 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1460 For older changes see ChangeLog-9103
1466 version-control: never