1 2012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
2 Maciej W. Rozycki <macro@codesourcery.com>
4 * mips.h (mips_opcode): Add the exclusions field.
5 (OPCODE_IS_MEMBER): Remove macro.
6 (cpu_is_member): New inline function.
7 (opcode_is_member): Likewise.
9 2012-07-31 Chao-Ying Fu <fu@mips.com>
10 Catherine Moore <clm@codesourcery.com>
11 Maciej W. Rozycki <macro@codesourcery.com>
13 * mips.h: Document microMIPS DSP ASE usage.
14 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
15 microMIPS DSP ASE support.
16 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
17 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
18 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
19 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
20 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
21 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
22 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
24 2012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
26 * mips.h: Fix a typo in description.
28 2012-06-07 Georg-Johann Lay <avr@gjlay.de>
30 * avr.h: (AVR_ISA_XCH): New define.
31 (AVR_ISA_XMEGA): Use it.
32 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
34 2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
36 * m68hc11.h: Add XGate definitions.
37 (struct m68hc11_opcode): Add xg_mask field.
39 2012-05-14 Catherine Moore <clm@codesourcery.com>
40 Maciej W. Rozycki <macro@codesourcery.com>
41 Rhonda Wittels <rhonda@codesourcery.com>
43 * ppc.h (PPC_OPCODE_VLE): New definition.
44 (PPC_OP_SA): New macro.
45 (PPC_OP_SE_VLE): New macro.
46 (PPC_OP): Use a variable shift amount.
47 (powerpc_operand): Update comments.
48 (PPC_OPSHIFT_INV): New macro.
49 (PPC_OPERAND_CR): Replace with...
50 (PPC_OPERAND_CR_BIT): ...this and
51 (PPC_OPERAND_CR_REG): ...this.
54 2012-05-03 Sean Keys <skeys@ipdatasys.com>
56 * xgate.h: Header file for XGATE assembler.
58 2012-04-27 David S. Miller <davem@davemloft.net>
60 * sparc.h: Document new arg code' )' for crypto RS3
63 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
64 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
65 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
66 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
67 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
68 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
69 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
70 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
71 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
72 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
73 HWCAP_CBCOND, HWCAP_CRC32): New defines.
75 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
77 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
79 2012-02-27 Alan Modra <amodra@gmail.com>
81 * crx.h (cst4_map): Update declaration.
83 2012-02-25 Walter Lee <walt@tilera.com>
85 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
87 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
88 TILEPRO_OPC_LW_TLS_SN.
90 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
92 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
93 (XRELEASE_PREFIX_OPCODE): Likewise.
95 2011-12-08 Andrew Pinski <apinski@cavium.com>
96 Adam Nemet <anemet@caviumnetworks.com>
98 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
99 (INSN_OCTEON2): New macro.
100 (CPU_OCTEON2): New macro.
101 (OPCODE_IS_MEMBER): Add Octeon2.
103 2011-11-29 Andrew Pinski <apinski@cavium.com>
105 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
106 (INSN_OCTEONP): New macro.
107 (CPU_OCTEONP): New macro.
108 (OPCODE_IS_MEMBER): Add Octeon+.
109 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
111 2011-11-01 DJ Delorie <dj@redhat.com>
115 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
117 * mips.h: Fix a typo in description.
119 2011-09-21 David S. Miller <davem@davemloft.net>
121 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
122 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
123 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
124 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
126 2011-08-09 Chao-ying Fu <fu@mips.com>
127 Maciej W. Rozycki <macro@codesourcery.com>
129 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
130 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
131 (INSN_ASE_MASK): Add the MCU bit.
132 (INSN_MCU): New macro.
133 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
134 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
136 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
138 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
139 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
140 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
141 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
142 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
143 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
144 (INSN2_READ_GPR_MMN): Likewise.
145 (INSN2_READ_FPR_D): Change the bit used.
146 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
147 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
148 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
149 (INSN2_COND_BRANCH): Likewise.
150 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
151 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
152 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
153 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
154 (INSN2_MOD_GPR_MN): Likewise.
156 2011-08-05 David S. Miller <davem@davemloft.net>
158 * sparc.h: Document new format codes '4', '5', and '('.
159 (OPF_LOW4, RS3): New macros.
161 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
163 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
164 order of flags documented.
166 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
168 * mips.h: Clarify the description of microMIPS instruction
170 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
172 2011-07-24 Chao-ying Fu <fu@mips.com>
173 Maciej W. Rozycki <macro@codesourcery.com>
175 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
176 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
177 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
178 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
179 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
180 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
181 (OP_MASK_RS3, OP_SH_RS3): Likewise.
182 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
183 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
184 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
185 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
186 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
187 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
188 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
189 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
190 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
191 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
192 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
193 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
194 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
195 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
196 (INSN_WRITE_GPR_S): New macro.
197 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
198 (INSN2_READ_FPR_D): Likewise.
199 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
200 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
201 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
202 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
203 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
204 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
205 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
206 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
207 (CPU_MICROMIPS): New macro.
208 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
209 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
210 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
211 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
212 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
213 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
214 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
215 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
216 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
217 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
218 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
219 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
220 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
221 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
222 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
223 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
224 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
225 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
226 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
227 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
228 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
229 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
230 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
231 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
232 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
233 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
234 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
235 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
236 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
237 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
238 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
239 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
240 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
241 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
242 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
243 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
244 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
245 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
246 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
247 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
248 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
249 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
250 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
251 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
252 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
253 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
254 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
255 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
256 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
257 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
258 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
259 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
260 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
261 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
262 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
263 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
264 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
265 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
266 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
267 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
268 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
269 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
270 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
271 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
272 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
273 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
274 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
275 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
276 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
277 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
278 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
279 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
280 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
281 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
282 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
283 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
284 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
285 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
286 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
287 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
288 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
289 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
290 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
291 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
292 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
293 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
294 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
295 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
296 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
297 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
298 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
299 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
300 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
301 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
302 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
303 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
304 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
305 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
306 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
307 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
308 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
309 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
310 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
311 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
312 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
313 (micromips_opcodes): New declaration.
314 (bfd_micromips_num_opcodes): Likewise.
316 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
318 * mips.h (INSN_TRAP): Rename to...
319 (INSN_NO_DELAY_SLOT): ... this.
320 (INSN_SYNC): Remove macro.
322 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
324 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
325 a duplicate of AVR_ISA_SPM.
327 2011-07-01 Nick Clifton <nickc@redhat.com>
329 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
331 2011-06-18 Robin Getz <robin.getz@analog.com>
333 * bfin.h (is_macmod_signed): New func
335 2011-06-18 Mike Frysinger <vapier@gentoo.org>
337 * bfin.h (is_macmod_pmove): Add missing space before func args.
338 (is_macmod_hmove): Likewise.
340 2011-06-13 Walter Lee <walt@tilera.com>
342 * tilegx.h: New file.
343 * tilepro.h: New file.
345 2011-05-31 Paul Brook <paul@codesourcery.com>
347 * arm.h (ARM_ARCH_V7R_IDIV): Define.
349 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
351 * s390.h: Replace S390_OPERAND_REG_EVEN with
352 S390_OPERAND_REG_PAIR.
354 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
356 * s390.h: Add S390_OPCODE_REG_EVEN flag.
358 2011-04-18 Julian Brown <julian@codesourcery.com>
360 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
362 2011-04-11 Dan McDonald <dan@wellkeeper.com>
365 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
367 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
369 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
370 New instruction set flags.
371 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
373 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
375 * mips.h (M_PREF_AB): New enum value.
377 2011-02-12 Mike Frysinger <vapier@gentoo.org>
379 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
381 (is_macmod_pmove, is_macmod_hmove): New functions.
383 2011-02-11 Mike Frysinger <vapier@gentoo.org>
385 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
387 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
389 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
390 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
392 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
395 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
398 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
401 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
403 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
405 * mips.h: Update commentary after last commit.
407 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
409 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
410 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
411 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
413 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
415 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
417 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
419 * mips.h: Fix previous commit.
421 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
423 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
424 (INSN_LOONGSON_3A): Clear bit 31.
426 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
429 * arm.h (ARM_AEXT_V6M_ONLY): New define.
430 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
431 (ARM_ARCH_V6M_ONLY): New define.
433 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
435 * mips.h (INSN_LOONGSON_3A): Defined.
436 (CPU_LOONGSON_3A): Defined.
437 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
439 2010-10-09 Matt Rice <ratmice@gmail.com>
441 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
442 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
444 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
446 * arm.h (ARM_EXT_VIRT): New define.
447 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
448 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
451 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
453 * arm.h (ARM_AEXT_ADIV): New define.
454 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
456 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
458 * arm.h (ARM_EXT_OS): New define.
459 (ARM_AEXT_V6SM): Likewise.
460 (ARM_ARCH_V6SM): Likewise.
462 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
464 * arm.h (ARM_EXT_MP): Add.
465 (ARM_ARCH_V7A_MP): Likewise.
467 2010-09-22 Mike Frysinger <vapier@gentoo.org>
469 * bfin.h: Declare pseudoChr structs/defines.
471 2010-09-21 Mike Frysinger <vapier@gentoo.org>
473 * bfin.h: Strip trailing whitespace.
475 2010-07-29 DJ Delorie <dj@redhat.com>
477 * rx.h (RX_Operand_Type): Add TwoReg.
478 (RX_Opcode_ID): Remove ediv and ediv2.
480 2010-07-27 DJ Delorie <dj@redhat.com>
482 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
484 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
485 Ina Pandit <ina.pandit@kpitcummins.com>
487 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
488 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
489 PROCESSOR_V850E2_ALL.
490 Remove PROCESSOR_V850EA support.
491 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
492 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
493 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
494 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
495 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
496 V850_OPERAND_PERCENT.
497 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
499 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
502 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
504 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
505 (MIPS16_INSN_BRANCH): Rename to...
506 (MIPS16_INSN_COND_BRANCH): ... this.
508 2010-07-03 Alan Modra <amodra@gmail.com>
510 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
511 Renumber other PPC_OPCODE defines.
513 2010-07-03 Alan Modra <amodra@gmail.com>
515 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
517 2010-06-29 Alan Modra <amodra@gmail.com>
519 * maxq.h: Delete file.
521 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
523 * ppc.h (PPC_OPCODE_E500): Define.
525 2010-05-26 Catherine Moore <clm@codesourcery.com>
527 * opcode/mips.h (INSN_MIPS16): Remove.
529 2010-04-21 Joseph Myers <joseph@codesourcery.com>
531 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
533 2010-04-15 Nick Clifton <nickc@redhat.com>
535 * alpha.h: Update copyright notice to use GPLv3.
541 * convex.h: Likewise.
555 * m68hc11.h: Likewise.
561 * mn10200.h: Likewise.
562 * mn10300.h: Likewise.
563 * msp430.h: Likewise.
574 * score-datadep.h: Likewise.
575 * score-inst.h: Likewise.
577 * spu-insns.h: Likewise.
581 * tic54x.h: Likewise.
586 2010-03-25 Joseph Myers <joseph@codesourcery.com>
588 * tic6x-control-registers.h, tic6x-insn-formats.h,
589 tic6x-opcode-table.h, tic6x.h: New.
591 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
593 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
595 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
597 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
599 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
601 * ia64.h (ia64_find_opcode): Remove argument name.
602 (ia64_find_next_opcode): Likewise.
603 (ia64_dis_opcode): Likewise.
604 (ia64_free_opcode): Likewise.
605 (ia64_find_dependency): Likewise.
607 2009-11-22 Doug Evans <dje@sebabeach.org>
609 * cgen.h: Include bfd_stdint.h.
610 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
612 2009-11-18 Paul Brook <paul@codesourcery.com>
614 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
616 2009-11-17 Paul Brook <paul@codesourcery.com>
617 Daniel Jacobowitz <dan@codesourcery.com>
619 * arm.h (ARM_EXT_V6_DSP): Define.
620 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
621 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
623 2009-11-04 DJ Delorie <dj@redhat.com>
625 * rx.h (rx_decode_opcode) (mvtipl): Add.
626 (mvtcp, mvfcp, opecp): Remove.
628 2009-11-02 Paul Brook <paul@codesourcery.com>
630 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
631 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
632 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
633 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
634 FPU_ARCH_NEON_VFP_V4): Define.
636 2009-10-23 Doug Evans <dje@sebabeach.org>
638 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
639 * cgen.h: Update. Improve multi-inclusion macro name.
641 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
643 * ppc.h (PPC_OPCODE_476): Define.
645 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
647 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
649 2009-09-29 DJ Delorie <dj@redhat.com>
653 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
655 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
657 2009-09-21 Ben Elliston <bje@au.ibm.com>
659 * ppc.h (PPC_OPCODE_PPCA2): New.
661 2009-09-05 Martin Thuresson <martin@mtme.org>
663 * ia64.h (struct ia64_operand): Renamed member class to op_class.
665 2009-08-29 Martin Thuresson <martin@mtme.org>
667 * tic30.h (template): Rename type template to
668 insn_template. Updated code to use new name.
669 * tic54x.h (template): Rename type template to
672 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
674 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
676 2009-06-11 Anthony Green <green@moxielogic.com>
678 * moxie.h (MOXIE_F3_PCREL): Define.
679 (moxie_form3_opc_info): Grow.
681 2009-06-06 Anthony Green <green@moxielogic.com>
683 * moxie.h (MOXIE_F1_M): Define.
685 2009-04-15 Anthony Green <green@moxielogic.com>
689 2009-04-06 DJ Delorie <dj@redhat.com>
691 * h8300.h: Add relaxation attributes to MOVA opcodes.
693 2009-03-10 Alan Modra <amodra@bigpond.net.au>
695 * ppc.h (ppc_parse_cpu): Declare.
697 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
699 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
700 and _IMM11 for mbitclr and mbitset.
701 * score-datadep.h: Update dependency information.
703 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
705 * ppc.h (PPC_OPCODE_POWER7): New.
707 2009-02-06 Doug Evans <dje@google.com>
709 * i386.h: Add comment regarding sse* insns and prefixes.
711 2009-02-03 Sandip Matte <sandip@rmicorp.com>
713 * mips.h (INSN_XLR): Define.
714 (INSN_CHIP_MASK): Update.
716 (OPCODE_IS_MEMBER): Update.
717 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
719 2009-01-28 Doug Evans <dje@google.com>
721 * opcode/i386.h: Add multiple inclusion protection.
722 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
723 (EDI_REG_NUM): New macros.
724 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
725 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
726 (REX_PREFIX_P): New macro.
728 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
730 * ppc.h (struct powerpc_opcode): New field "deprecated".
731 (PPC_OPCODE_NOPOWER4): Delete.
733 2008-11-28 Joshua Kinard <kumba@gentoo.org>
735 * mips.h: Define CPU_R14000, CPU_R16000.
736 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
738 2008-11-18 Catherine Moore <clm@codesourcery.com>
740 * arm.h (FPU_NEON_FP16): New.
741 (FPU_ARCH_NEON_FP16): New.
743 2008-11-06 Chao-ying Fu <fu@mips.com>
745 * mips.h: Doucument '1' for 5-bit sync type.
747 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
749 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
752 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
754 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
756 2008-07-30 Michael J. Eager <eager@eagercon.com>
758 * ppc.h (PPC_OPCODE_405): Define.
759 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
761 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
763 * ppc.h (ppc_cpu_t): New typedef.
764 (struct powerpc_opcode <flags>): Use it.
765 (struct powerpc_operand <insert, extract>): Likewise.
766 (struct powerpc_macro <flags>): Likewise.
768 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
770 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
771 Update comment before MIPS16 field descriptors to mention MIPS16.
772 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
774 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
775 New bit masks and shift counts for cins and exts.
777 * mips.h: Document new field descriptors +Q.
778 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
780 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
782 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
783 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
785 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
787 * ppc.h: (PPC_OPCODE_E500MC): New.
789 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
791 * i386.h (MAX_OPERANDS): Set to 5.
792 (MAX_MNEM_SIZE): Changed to 20.
794 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
796 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
798 2008-03-09 Paul Brook <paul@codesourcery.com>
800 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
802 2008-03-04 Paul Brook <paul@codesourcery.com>
804 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
805 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
806 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
808 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
809 Nick Clifton <nickc@redhat.com>
812 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
813 with a 32-bit displacement but without the top bit of the 4th byte
816 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
818 * cr16.h (cr16_num_optab): Declared.
820 2008-02-14 Hakan Ardo <hakan@debian.org>
823 * avr.h (AVR_ISA_2xxe): Define.
825 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
827 * mips.h: Update copyright.
828 (INSN_CHIP_MASK): New macro.
829 (INSN_OCTEON): New macro.
830 (CPU_OCTEON): New macro.
831 (OPCODE_IS_MEMBER): Handle Octeon instructions.
833 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
835 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
837 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
839 * avr.h (AVR_ISA_USB162): Add new opcode set.
840 (AVR_ISA_AVR3): Likewise.
842 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
844 * mips.h (INSN_LOONGSON_2E): New.
845 (INSN_LOONGSON_2F): New.
846 (CPU_LOONGSON_2E): New.
847 (CPU_LOONGSON_2F): New.
848 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
850 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
852 * mips.h (INSN_ISA*): Redefine certain values as an
853 enumeration. Update comments.
854 (mips_isa_table): New.
855 (ISA_MIPS*): Redefine to match enumeration.
856 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
859 2007-08-08 Ben Elliston <bje@au.ibm.com>
861 * ppc.h (PPC_OPCODE_PPCPS): New.
863 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
865 * m68k.h: Document j K & E.
867 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
869 * cr16.h: New file for CR16 target.
871 2007-05-02 Alan Modra <amodra@bigpond.net.au>
873 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
875 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
877 * m68k.h (mcfisa_c): New.
878 (mcfusp, mcf_mask): Adjust.
880 2007-04-20 Alan Modra <amodra@bigpond.net.au>
882 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
883 (num_powerpc_operands): Declare.
884 (PPC_OPERAND_SIGNED et al): Redefine as hex.
885 (PPC_OPERAND_PLUS1): Define.
887 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
889 * i386.h (REX_MODE64): Renamed to ...
891 (REX_EXTX): Renamed to ...
893 (REX_EXTY): Renamed to ...
895 (REX_EXTZ): Renamed to ...
898 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
900 * i386.h: Add entries from config/tc-i386.h and move tables
901 to opcodes/i386-opc.h.
903 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
905 * i386.h (FloatDR): Removed.
906 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
908 2007-03-01 Alan Modra <amodra@bigpond.net.au>
910 * spu-insns.h: Add soma double-float insns.
912 2007-02-20 Thiemo Seufer <ths@mips.com>
913 Chao-Ying Fu <fu@mips.com>
915 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
916 (INSN_DSPR2): Add flag for DSP R2 instructions.
917 (M_BALIGN): New macro.
919 2007-02-14 Alan Modra <amodra@bigpond.net.au>
921 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
922 and Seg3ShortFrom with Shortform.
924 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
927 * i386.h (i386_optab): Put the real "test" before the pseudo
930 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
932 * m68k.h (m68010up): OR fido_a.
934 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
936 * m68k.h (fido_a): New.
938 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
940 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
941 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
944 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
946 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
948 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
950 * score-inst.h (enum score_insn_type): Add Insn_internal.
952 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
953 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
954 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
955 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
956 Alan Modra <amodra@bigpond.net.au>
958 * spu-insns.h: New file.
961 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
963 * ppc.h (PPC_OPCODE_CELL): Define.
965 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
967 * i386.h : Modify opcode to support for the change in POPCNT opcode
968 in amdfam10 architecture.
970 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
972 * i386.h: Replace CpuMNI with CpuSSSE3.
974 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
975 Joseph Myers <joseph@codesourcery.com>
976 Ian Lance Taylor <ian@wasabisystems.com>
977 Ben Elliston <bje@wasabisystems.com>
979 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
981 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
983 * score-datadep.h: New file.
984 * score-inst.h: New file.
986 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
988 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
989 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
992 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
993 Michael Meissner <michael.meissner@amd.com>
995 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
997 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
999 * i386.h (i386_optab): Add "nop" with memory reference.
1001 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1003 * i386.h (i386_optab): Update comment for 64bit NOP.
1005 2006-06-06 Ben Elliston <bje@au.ibm.com>
1006 Anton Blanchard <anton@samba.org>
1008 * ppc.h (PPC_OPCODE_POWER6): Define.
1011 2006-06-05 Thiemo Seufer <ths@mips.com>
1013 * mips.h: Improve description of MT flags.
1015 2006-05-25 Richard Sandiford <richard@codesourcery.com>
1017 * m68k.h (mcf_mask): Define.
1019 2006-05-05 Thiemo Seufer <ths@mips.com>
1020 David Ung <davidu@mips.com>
1022 * mips.h (enum): Add macro M_CACHE_AB.
1024 2006-05-04 Thiemo Seufer <ths@mips.com>
1025 Nigel Stephens <nigel@mips.com>
1026 David Ung <davidu@mips.com>
1028 * mips.h: Add INSN_SMARTMIPS define.
1030 2006-04-30 Thiemo Seufer <ths@mips.com>
1031 David Ung <davidu@mips.com>
1033 * mips.h: Defines udi bits and masks. Add description of
1034 characters which may appear in the args field of udi
1037 2006-04-26 Thiemo Seufer <ths@networkno.de>
1039 * mips.h: Improve comments describing the bitfield instruction
1042 2006-04-26 Julian Brown <julian@codesourcery.com>
1044 * arm.h (FPU_VFP_EXT_V3): Define constant.
1045 (FPU_NEON_EXT_V1): Likewise.
1046 (FPU_VFP_HARD): Update.
1047 (FPU_VFP_V3): Define macro.
1048 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1050 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
1052 * avr.h (AVR_ISA_PWMx): New.
1054 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1056 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1057 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1058 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1059 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1060 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1062 2006-03-10 Paul Brook <paul@codesourcery.com>
1064 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1066 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1068 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1069 first. Correct mask of bb "B" opcode.
1071 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1073 * i386.h (i386_optab): Support Intel Merom New Instructions.
1075 2006-02-24 Paul Brook <paul@codesourcery.com>
1077 * arm.h: Add V7 feature bits.
1079 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1081 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1083 2006-01-31 Paul Brook <paul@codesourcery.com>
1084 Richard Earnshaw <rearnsha@arm.com>
1086 * arm.h: Use ARM_CPU_FEATURE.
1087 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1088 (arm_feature_set): Change to a structure.
1089 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1090 ARM_FEATURE): New macros.
1092 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
1094 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1095 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1096 (ADD_PC_INCR_OPCODE): Don't define.
1098 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1101 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1103 2005-11-14 David Ung <davidu@mips.com>
1105 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1106 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1107 save/restore encoding of the args field.
1109 2005-10-28 Dave Brolley <brolley@redhat.com>
1111 Contribute the following changes:
1112 2005-02-16 Dave Brolley <brolley@redhat.com>
1114 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1115 cgen_isa_mask_* to cgen_bitset_*.
1118 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1120 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1121 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1122 (CGEN_CPU_TABLE): Make isas a ponter.
1124 2003-09-29 Dave Brolley <brolley@redhat.com>
1126 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1127 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1128 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1130 2002-12-13 Dave Brolley <brolley@redhat.com>
1132 * cgen.h (symcat.h): #include it.
1133 (cgen-bitset.h): #include it.
1134 (CGEN_ATTR_VALUE_TYPE): Now a union.
1135 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1136 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1137 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1138 * cgen-bitset.h: New file.
1140 2005-09-30 Catherine Moore <clm@cm00re.com>
1144 2005-10-24 Jan Beulich <jbeulich@novell.com>
1146 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1149 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1151 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1152 Add FLAG_STRICT to pa10 ftest opcode.
1154 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1156 * hppa.h (pa_opcodes): Remove lha entries.
1158 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1160 * hppa.h (FLAG_STRICT): Revise comment.
1161 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1162 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1165 2005-09-30 Catherine Moore <clm@cm00re.com>
1169 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1171 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1173 2005-09-06 Chao-ying Fu <fu@mips.com>
1175 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1176 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1178 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1179 (INSN_ASE_MASK): Update to include INSN_MT.
1180 (INSN_MT): New define for MT ASE.
1182 2005-08-25 Chao-ying Fu <fu@mips.com>
1184 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1185 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1186 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1187 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1188 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1189 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1191 (INSN_DSP): New define for DSP ASE.
1193 2005-08-18 Alan Modra <amodra@bigpond.net.au>
1197 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1199 * ppc.h (PPC_OPCODE_E300): Define.
1201 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1203 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1205 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1208 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1211 2005-07-27 Jan Beulich <jbeulich@novell.com>
1213 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1214 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1215 Add movq-s as 64-bit variants of movd-s.
1217 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1219 * hppa.h: Fix punctuation in comment.
1221 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1222 implicit space-register addressing. Set space-register bits on opcodes
1223 using implicit space-register addressing. Add various missing pa20
1224 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1225 space-register addressing. Use "fE" instead of "fe" in various
1228 2005-07-18 Jan Beulich <jbeulich@novell.com>
1230 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1232 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1234 * i386.h (i386_optab): Support Intel VMX Instructions.
1236 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1238 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1240 2005-07-05 Jan Beulich <jbeulich@novell.com>
1242 * i386.h (i386_optab): Add new insns.
1244 2005-07-01 Nick Clifton <nickc@redhat.com>
1246 * sparc.h: Add typedefs to structure declarations.
1248 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1251 * i386.h (i386_optab): Update comments for 64bit addressing on
1252 mov. Allow 64bit addressing for mov and movq.
1254 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1256 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1257 respectively, in various floating-point load and store patterns.
1259 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1261 * hppa.h (FLAG_STRICT): Correct comment.
1262 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1263 PA 2.0 mneumonics when equivalent. Entries with cache control
1264 completers now require PA 1.1. Adjust whitespace.
1266 2005-05-19 Anton Blanchard <anton@samba.org>
1268 * ppc.h (PPC_OPCODE_POWER5): Define.
1270 2005-05-10 Nick Clifton <nickc@redhat.com>
1272 * Update the address and phone number of the FSF organization in
1273 the GPL notices in the following files:
1274 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1275 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1276 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1277 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1278 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1279 tic54x.h, tic80.h, v850.h, vax.h
1281 2005-05-09 Jan Beulich <jbeulich@novell.com>
1283 * i386.h (i386_optab): Add ht and hnt.
1285 2005-04-18 Mark Kettenis <kettenis@gnu.org>
1287 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1288 Add xcrypt-ctr. Provide aliases without hyphens.
1290 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1292 Moved from ../ChangeLog
1294 2005-04-12 Paul Brook <paul@codesourcery.com>
1295 * m88k.h: Rename psr macros to avoid conflicts.
1297 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1298 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1299 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1300 and ARM_ARCH_V6ZKT2.
1302 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1303 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1304 Remove redundant instruction types.
1305 (struct argument): X_op - new field.
1306 (struct cst4_entry): Remove.
1307 (no_op_insn): Declare.
1309 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1310 * crx.h (enum argtype): Rename types, remove unused types.
1312 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1313 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1314 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1315 (enum operand_type): Rearrange operands, edit comments.
1316 replace us<N> with ui<N> for unsigned immediate.
1317 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1318 displacements (respectively).
1319 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1320 (instruction type): Add NO_TYPE_INS.
1321 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1322 (operand_entry): New field - 'flags'.
1323 (operand flags): New.
1325 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1326 * crx.h (operand_type): Remove redundant types i3, i4,
1328 Add new unsigned immediate types us3, us4, us5, us16.
1330 2005-04-12 Mark Kettenis <kettenis@gnu.org>
1332 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1333 adjust them accordingly.
1335 2005-04-01 Jan Beulich <jbeulich@novell.com>
1337 * i386.h (i386_optab): Add rdtscp.
1339 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1341 * i386.h (i386_optab): Don't allow the `l' suffix for moving
1342 between memory and segment register. Allow movq for moving between
1343 general-purpose register and segment register.
1345 2005-02-09 Jan Beulich <jbeulich@novell.com>
1348 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1349 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1352 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1354 * m68k.h (m68008, m68ec030, m68882): Remove.
1356 (cpu_m68k, cpu_cf): New.
1357 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1358 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1360 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
1362 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1363 * cgen.h (enum cgen_parse_operand_type): Add
1364 CGEN_PARSE_OPERAND_SYMBOLIC.
1366 2005-01-21 Fred Fish <fnf@specifixinc.com>
1368 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1369 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1370 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1372 2005-01-19 Fred Fish <fnf@specifixinc.com>
1374 * mips.h (struct mips_opcode): Add new pinfo2 member.
1375 (INSN_ALIAS): New define for opcode table entries that are
1376 specific instances of another entry, such as 'move' for an 'or'
1377 with a zero operand.
1378 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1379 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1381 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1383 * mips.h (CPU_RM9000): Define.
1384 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1386 2004-11-25 Jan Beulich <jbeulich@novell.com>
1388 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1389 to/from test registers are illegal in 64-bit mode. Add missing
1390 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1391 (previously one had to explicitly encode a rex64 prefix). Re-enable
1392 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1393 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1395 2004-11-23 Jan Beulich <jbeulich@novell.com>
1397 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1398 available only with SSE2. Change the MMX additions introduced by SSE
1399 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1400 instructions by their now designated identifier (since combining i686
1401 and 3DNow! does not really imply 3DNow!A).
1403 2004-11-19 Alan Modra <amodra@bigpond.net.au>
1405 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1406 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1408 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1409 Vineet Sharma <vineets@noida.hcltech.com>
1411 * maxq.h: New file: Disassembly information for the maxq port.
1413 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1415 * i386.h (i386_optab): Put back "movzb".
1417 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
1419 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1420 comments. Remove member cris_ver_sim. Add members
1421 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1422 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1423 (struct cris_support_reg, struct cris_cond15): New types.
1424 (cris_conds15): Declare.
1425 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1426 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1427 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1428 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1429 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1430 SIZE_FIELD_UNSIGNED.
1432 2004-11-04 Jan Beulich <jbeulich@novell.com>
1434 * i386.h (sldx_Suf): Remove.
1435 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1436 (q_FP): Define, implying no REX64.
1437 (x_FP, sl_FP): Imply FloatMF.
1438 (i386_optab): Split reg and mem forms of moving from segment registers
1439 so that the memory forms can ignore the 16-/32-bit operand size
1440 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1441 all non-floating-point instructions. Unite 32- and 64-bit forms of
1442 movsx, movzx, and movd. Adjust floating point operations for the above
1443 changes to the *FP macros. Add DefaultSize to floating point control
1444 insns operating on larger memory ranges. Remove left over comments
1445 hinting at certain insns being Intel-syntax ones where the ones
1446 actually meant are already gone.
1448 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1450 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1453 2004-09-30 Paul Brook <paul@codesourcery.com>
1455 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1456 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1458 2004-09-11 Theodore A. Roth <troth@openavr.org>
1460 * avr.h: Add support for
1461 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1463 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1465 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1467 2004-08-24 Dmitry Diky <diwil@spec.ru>
1469 * msp430.h (msp430_opc): Add new instructions.
1470 (msp430_rcodes): Declare new instructions.
1471 (msp430_hcodes): Likewise..
1473 2004-08-13 Nick Clifton <nickc@redhat.com>
1476 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1479 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1481 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1483 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1485 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1487 2004-07-21 Jan Beulich <jbeulich@novell.com>
1489 * i386.h: Adjust instruction descriptions to better match the
1492 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
1494 * arm.h: Remove all old content. Replace with architecture defines
1495 from gas/config/tc-arm.c.
1497 2004-07-09 Andreas Schwab <schwab@suse.de>
1499 * m68k.h: Fix comment.
1501 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1505 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1507 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1509 2004-05-24 Peter Barada <peter@the-baradas.com>
1511 * m68k.h: Add 'size' to m68k_opcode.
1513 2004-05-05 Peter Barada <peter@the-baradas.com>
1515 * m68k.h: Switch from ColdFire chip name to core variant.
1517 2004-04-22 Peter Barada <peter@the-baradas.com>
1519 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1520 descriptions for new EMAC cases.
1521 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1522 handle Motorola MAC syntax.
1523 Allow disassembly of ColdFire V4e object files.
1525 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1527 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1529 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1531 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1533 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1535 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1537 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1539 * i386.h (i386_optab): Added xstore/xcrypt insns.
1541 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1543 * h8300.h (32bit ldc/stc): Add relaxing support.
1545 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1547 * h8300.h (BITOP): Pass MEMRELAX flag.
1549 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1551 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1554 For older changes see ChangeLog-9103
1560 version-control: never