1 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
3 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
4 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
5 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
6 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
7 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
8 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
9 (INSN2_READ_GPR_MMN): Likewise.
10 (INSN2_READ_FPR_D): Change the bit used.
11 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
12 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
13 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
14 (INSN2_COND_BRANCH): Likewise.
15 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
16 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
17 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
18 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
19 (INSN2_MOD_GPR_MN): Likewise.
21 2011-08-05 David S. Miller <davem@davemloft.net>
23 * sparc.h: Document new format codes '4', '5', and '('.
24 (OPF_LOW4, RS3): New macros.
26 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
28 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
29 order of flags documented.
31 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
33 * mips.h: Clarify the description of microMIPS instruction
35 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
37 2011-07-24 Chao-ying Fu <fu@mips.com>
38 Maciej W. Rozycki <macro@codesourcery.com>
40 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
41 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
42 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
43 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
44 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
45 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
46 (OP_MASK_RS3, OP_SH_RS3): Likewise.
47 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
48 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
49 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
50 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
51 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
52 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
53 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
54 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
55 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
56 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
57 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
58 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
59 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
60 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
61 (INSN_WRITE_GPR_S): New macro.
62 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
63 (INSN2_READ_FPR_D): Likewise.
64 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
65 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
66 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
67 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
68 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
69 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
70 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
71 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
72 (CPU_MICROMIPS): New macro.
73 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
74 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
75 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
76 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
77 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
78 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
79 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
80 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
81 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
82 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
83 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
84 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
85 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
86 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
87 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
88 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
89 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
90 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
91 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
92 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
93 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
94 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
95 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
96 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
97 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
98 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
99 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
100 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
101 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
102 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
103 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
104 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
105 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
106 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
107 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
108 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
109 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
110 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
111 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
112 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
113 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
114 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
115 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
116 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
117 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
118 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
119 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
120 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
121 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
122 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
123 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
124 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
125 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
126 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
127 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
128 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
129 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
130 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
131 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
132 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
133 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
134 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
135 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
136 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
137 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
138 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
139 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
140 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
141 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
142 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
143 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
144 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
145 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
146 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
147 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
148 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
149 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
150 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
151 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
152 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
153 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
154 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
155 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
156 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
157 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
158 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
159 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
160 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
161 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
162 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
163 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
164 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
165 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
166 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
167 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
168 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
169 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
170 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
171 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
172 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
173 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
174 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
175 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
176 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
177 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
178 (micromips_opcodes): New declaration.
179 (bfd_micromips_num_opcodes): Likewise.
181 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
183 * mips.h (INSN_TRAP): Rename to...
184 (INSN_NO_DELAY_SLOT): ... this.
185 (INSN_SYNC): Remove macro.
187 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
189 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
190 a duplicate of AVR_ISA_SPM.
192 2011-07-01 Nick Clifton <nickc@redhat.com>
194 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
196 2011-06-18 Robin Getz <robin.getz@analog.com>
198 * bfin.h (is_macmod_signed): New func
200 2011-06-18 Mike Frysinger <vapier@gentoo.org>
202 * bfin.h (is_macmod_pmove): Add missing space before func args.
203 (is_macmod_hmove): Likewise.
205 2011-06-13 Walter Lee <walt@tilera.com>
207 * tilegx.h: New file.
208 * tilepro.h: New file.
210 2011-05-31 Paul Brook <paul@codesourcery.com>
212 * arm.h (ARM_ARCH_V7R_IDIV): Define.
214 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
216 * s390.h: Replace S390_OPERAND_REG_EVEN with
217 S390_OPERAND_REG_PAIR.
219 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
221 * s390.h: Add S390_OPCODE_REG_EVEN flag.
223 2011-04-18 Julian Brown <julian@codesourcery.com>
225 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
227 2011-04-11 Dan McDonald <dan@wellkeeper.com>
230 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
232 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
234 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
235 New instruction set flags.
236 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
238 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
240 * mips.h (M_PREF_AB): New enum value.
242 2011-02-12 Mike Frysinger <vapier@gentoo.org>
244 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
246 (is_macmod_pmove, is_macmod_hmove): New functions.
248 2011-02-11 Mike Frysinger <vapier@gentoo.org>
250 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
252 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
254 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
255 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
257 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
260 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
263 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
266 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
268 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
270 * mips.h: Update commentary after last commit.
272 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
274 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
275 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
276 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
278 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
280 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
282 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
284 * mips.h: Fix previous commit.
286 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
288 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
289 (INSN_LOONGSON_3A): Clear bit 31.
291 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
294 * arm.h (ARM_AEXT_V6M_ONLY): New define.
295 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
296 (ARM_ARCH_V6M_ONLY): New define.
298 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
300 * mips.h (INSN_LOONGSON_3A): Defined.
301 (CPU_LOONGSON_3A): Defined.
302 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
304 2010-10-09 Matt Rice <ratmice@gmail.com>
306 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
307 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
309 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
311 * arm.h (ARM_EXT_VIRT): New define.
312 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
313 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
316 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
318 * arm.h (ARM_AEXT_ADIV): New define.
319 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
321 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
323 * arm.h (ARM_EXT_OS): New define.
324 (ARM_AEXT_V6SM): Likewise.
325 (ARM_ARCH_V6SM): Likewise.
327 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
329 * arm.h (ARM_EXT_MP): Add.
330 (ARM_ARCH_V7A_MP): Likewise.
332 2010-09-22 Mike Frysinger <vapier@gentoo.org>
334 * bfin.h: Declare pseudoChr structs/defines.
336 2010-09-21 Mike Frysinger <vapier@gentoo.org>
338 * bfin.h: Strip trailing whitespace.
340 2010-07-29 DJ Delorie <dj@redhat.com>
342 * rx.h (RX_Operand_Type): Add TwoReg.
343 (RX_Opcode_ID): Remove ediv and ediv2.
345 2010-07-27 DJ Delorie <dj@redhat.com>
347 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
349 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
350 Ina Pandit <ina.pandit@kpitcummins.com>
352 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
353 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
354 PROCESSOR_V850E2_ALL.
355 Remove PROCESSOR_V850EA support.
356 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
357 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
358 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
359 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
360 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
361 V850_OPERAND_PERCENT.
362 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
364 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
367 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
369 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
370 (MIPS16_INSN_BRANCH): Rename to...
371 (MIPS16_INSN_COND_BRANCH): ... this.
373 2010-07-03 Alan Modra <amodra@gmail.com>
375 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
376 Renumber other PPC_OPCODE defines.
378 2010-07-03 Alan Modra <amodra@gmail.com>
380 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
382 2010-06-29 Alan Modra <amodra@gmail.com>
384 * maxq.h: Delete file.
386 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
388 * ppc.h (PPC_OPCODE_E500): Define.
390 2010-05-26 Catherine Moore <clm@codesourcery.com>
392 * opcode/mips.h (INSN_MIPS16): Remove.
394 2010-04-21 Joseph Myers <joseph@codesourcery.com>
396 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
398 2010-04-15 Nick Clifton <nickc@redhat.com>
400 * alpha.h: Update copyright notice to use GPLv3.
406 * convex.h: Likewise.
420 * m68hc11.h: Likewise.
426 * mn10200.h: Likewise.
427 * mn10300.h: Likewise.
428 * msp430.h: Likewise.
439 * score-datadep.h: Likewise.
440 * score-inst.h: Likewise.
442 * spu-insns.h: Likewise.
446 * tic54x.h: Likewise.
451 2010-03-25 Joseph Myers <joseph@codesourcery.com>
453 * tic6x-control-registers.h, tic6x-insn-formats.h,
454 tic6x-opcode-table.h, tic6x.h: New.
456 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
458 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
460 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
462 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
464 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
466 * ia64.h (ia64_find_opcode): Remove argument name.
467 (ia64_find_next_opcode): Likewise.
468 (ia64_dis_opcode): Likewise.
469 (ia64_free_opcode): Likewise.
470 (ia64_find_dependency): Likewise.
472 2009-11-22 Doug Evans <dje@sebabeach.org>
474 * cgen.h: Include bfd_stdint.h.
475 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
477 2009-11-18 Paul Brook <paul@codesourcery.com>
479 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
481 2009-11-17 Paul Brook <paul@codesourcery.com>
482 Daniel Jacobowitz <dan@codesourcery.com>
484 * arm.h (ARM_EXT_V6_DSP): Define.
485 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
486 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
488 2009-11-04 DJ Delorie <dj@redhat.com>
490 * rx.h (rx_decode_opcode) (mvtipl): Add.
491 (mvtcp, mvfcp, opecp): Remove.
493 2009-11-02 Paul Brook <paul@codesourcery.com>
495 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
496 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
497 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
498 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
499 FPU_ARCH_NEON_VFP_V4): Define.
501 2009-10-23 Doug Evans <dje@sebabeach.org>
503 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
504 * cgen.h: Update. Improve multi-inclusion macro name.
506 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
508 * ppc.h (PPC_OPCODE_476): Define.
510 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
512 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
514 2009-09-29 DJ Delorie <dj@redhat.com>
518 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
520 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
522 2009-09-21 Ben Elliston <bje@au.ibm.com>
524 * ppc.h (PPC_OPCODE_PPCA2): New.
526 2009-09-05 Martin Thuresson <martin@mtme.org>
528 * ia64.h (struct ia64_operand): Renamed member class to op_class.
530 2009-08-29 Martin Thuresson <martin@mtme.org>
532 * tic30.h (template): Rename type template to
533 insn_template. Updated code to use new name.
534 * tic54x.h (template): Rename type template to
537 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
539 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
541 2009-06-11 Anthony Green <green@moxielogic.com>
543 * moxie.h (MOXIE_F3_PCREL): Define.
544 (moxie_form3_opc_info): Grow.
546 2009-06-06 Anthony Green <green@moxielogic.com>
548 * moxie.h (MOXIE_F1_M): Define.
550 2009-04-15 Anthony Green <green@moxielogic.com>
554 2009-04-06 DJ Delorie <dj@redhat.com>
556 * h8300.h: Add relaxation attributes to MOVA opcodes.
558 2009-03-10 Alan Modra <amodra@bigpond.net.au>
560 * ppc.h (ppc_parse_cpu): Declare.
562 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
564 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
565 and _IMM11 for mbitclr and mbitset.
566 * score-datadep.h: Update dependency information.
568 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
570 * ppc.h (PPC_OPCODE_POWER7): New.
572 2009-02-06 Doug Evans <dje@google.com>
574 * i386.h: Add comment regarding sse* insns and prefixes.
576 2009-02-03 Sandip Matte <sandip@rmicorp.com>
578 * mips.h (INSN_XLR): Define.
579 (INSN_CHIP_MASK): Update.
581 (OPCODE_IS_MEMBER): Update.
582 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
584 2009-01-28 Doug Evans <dje@google.com>
586 * opcode/i386.h: Add multiple inclusion protection.
587 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
588 (EDI_REG_NUM): New macros.
589 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
590 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
591 (REX_PREFIX_P): New macro.
593 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
595 * ppc.h (struct powerpc_opcode): New field "deprecated".
596 (PPC_OPCODE_NOPOWER4): Delete.
598 2008-11-28 Joshua Kinard <kumba@gentoo.org>
600 * mips.h: Define CPU_R14000, CPU_R16000.
601 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
603 2008-11-18 Catherine Moore <clm@codesourcery.com>
605 * arm.h (FPU_NEON_FP16): New.
606 (FPU_ARCH_NEON_FP16): New.
608 2008-11-06 Chao-ying Fu <fu@mips.com>
610 * mips.h: Doucument '1' for 5-bit sync type.
612 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
614 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
617 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
619 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
621 2008-07-30 Michael J. Eager <eager@eagercon.com>
623 * ppc.h (PPC_OPCODE_405): Define.
624 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
626 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
628 * ppc.h (ppc_cpu_t): New typedef.
629 (struct powerpc_opcode <flags>): Use it.
630 (struct powerpc_operand <insert, extract>): Likewise.
631 (struct powerpc_macro <flags>): Likewise.
633 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
635 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
636 Update comment before MIPS16 field descriptors to mention MIPS16.
637 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
639 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
640 New bit masks and shift counts for cins and exts.
642 * mips.h: Document new field descriptors +Q.
643 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
645 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
647 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
648 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
650 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
652 * ppc.h: (PPC_OPCODE_E500MC): New.
654 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
656 * i386.h (MAX_OPERANDS): Set to 5.
657 (MAX_MNEM_SIZE): Changed to 20.
659 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
661 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
663 2008-03-09 Paul Brook <paul@codesourcery.com>
665 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
667 2008-03-04 Paul Brook <paul@codesourcery.com>
669 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
670 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
671 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
673 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
674 Nick Clifton <nickc@redhat.com>
677 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
678 with a 32-bit displacement but without the top bit of the 4th byte
681 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
683 * cr16.h (cr16_num_optab): Declared.
685 2008-02-14 Hakan Ardo <hakan@debian.org>
688 * avr.h (AVR_ISA_2xxe): Define.
690 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
692 * mips.h: Update copyright.
693 (INSN_CHIP_MASK): New macro.
694 (INSN_OCTEON): New macro.
695 (CPU_OCTEON): New macro.
696 (OPCODE_IS_MEMBER): Handle Octeon instructions.
698 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
700 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
702 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
704 * avr.h (AVR_ISA_USB162): Add new opcode set.
705 (AVR_ISA_AVR3): Likewise.
707 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
709 * mips.h (INSN_LOONGSON_2E): New.
710 (INSN_LOONGSON_2F): New.
711 (CPU_LOONGSON_2E): New.
712 (CPU_LOONGSON_2F): New.
713 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
715 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
717 * mips.h (INSN_ISA*): Redefine certain values as an
718 enumeration. Update comments.
719 (mips_isa_table): New.
720 (ISA_MIPS*): Redefine to match enumeration.
721 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
724 2007-08-08 Ben Elliston <bje@au.ibm.com>
726 * ppc.h (PPC_OPCODE_PPCPS): New.
728 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
730 * m68k.h: Document j K & E.
732 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
734 * cr16.h: New file for CR16 target.
736 2007-05-02 Alan Modra <amodra@bigpond.net.au>
738 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
740 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
742 * m68k.h (mcfisa_c): New.
743 (mcfusp, mcf_mask): Adjust.
745 2007-04-20 Alan Modra <amodra@bigpond.net.au>
747 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
748 (num_powerpc_operands): Declare.
749 (PPC_OPERAND_SIGNED et al): Redefine as hex.
750 (PPC_OPERAND_PLUS1): Define.
752 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
754 * i386.h (REX_MODE64): Renamed to ...
756 (REX_EXTX): Renamed to ...
758 (REX_EXTY): Renamed to ...
760 (REX_EXTZ): Renamed to ...
763 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
765 * i386.h: Add entries from config/tc-i386.h and move tables
766 to opcodes/i386-opc.h.
768 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
770 * i386.h (FloatDR): Removed.
771 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
773 2007-03-01 Alan Modra <amodra@bigpond.net.au>
775 * spu-insns.h: Add soma double-float insns.
777 2007-02-20 Thiemo Seufer <ths@mips.com>
778 Chao-Ying Fu <fu@mips.com>
780 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
781 (INSN_DSPR2): Add flag for DSP R2 instructions.
782 (M_BALIGN): New macro.
784 2007-02-14 Alan Modra <amodra@bigpond.net.au>
786 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
787 and Seg3ShortFrom with Shortform.
789 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
792 * i386.h (i386_optab): Put the real "test" before the pseudo
795 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
797 * m68k.h (m68010up): OR fido_a.
799 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
801 * m68k.h (fido_a): New.
803 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
805 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
806 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
809 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
811 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
813 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
815 * score-inst.h (enum score_insn_type): Add Insn_internal.
817 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
818 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
819 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
820 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
821 Alan Modra <amodra@bigpond.net.au>
823 * spu-insns.h: New file.
826 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
828 * ppc.h (PPC_OPCODE_CELL): Define.
830 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
832 * i386.h : Modify opcode to support for the change in POPCNT opcode
833 in amdfam10 architecture.
835 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
837 * i386.h: Replace CpuMNI with CpuSSSE3.
839 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
840 Joseph Myers <joseph@codesourcery.com>
841 Ian Lance Taylor <ian@wasabisystems.com>
842 Ben Elliston <bje@wasabisystems.com>
844 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
846 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
848 * score-datadep.h: New file.
849 * score-inst.h: New file.
851 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
853 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
854 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
857 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
858 Michael Meissner <michael.meissner@amd.com>
860 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
862 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
864 * i386.h (i386_optab): Add "nop" with memory reference.
866 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
868 * i386.h (i386_optab): Update comment for 64bit NOP.
870 2006-06-06 Ben Elliston <bje@au.ibm.com>
871 Anton Blanchard <anton@samba.org>
873 * ppc.h (PPC_OPCODE_POWER6): Define.
876 2006-06-05 Thiemo Seufer <ths@mips.com>
878 * mips.h: Improve description of MT flags.
880 2006-05-25 Richard Sandiford <richard@codesourcery.com>
882 * m68k.h (mcf_mask): Define.
884 2006-05-05 Thiemo Seufer <ths@mips.com>
885 David Ung <davidu@mips.com>
887 * mips.h (enum): Add macro M_CACHE_AB.
889 2006-05-04 Thiemo Seufer <ths@mips.com>
890 Nigel Stephens <nigel@mips.com>
891 David Ung <davidu@mips.com>
893 * mips.h: Add INSN_SMARTMIPS define.
895 2006-04-30 Thiemo Seufer <ths@mips.com>
896 David Ung <davidu@mips.com>
898 * mips.h: Defines udi bits and masks. Add description of
899 characters which may appear in the args field of udi
902 2006-04-26 Thiemo Seufer <ths@networkno.de>
904 * mips.h: Improve comments describing the bitfield instruction
907 2006-04-26 Julian Brown <julian@codesourcery.com>
909 * arm.h (FPU_VFP_EXT_V3): Define constant.
910 (FPU_NEON_EXT_V1): Likewise.
911 (FPU_VFP_HARD): Update.
912 (FPU_VFP_V3): Define macro.
913 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
915 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
917 * avr.h (AVR_ISA_PWMx): New.
919 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
921 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
922 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
923 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
924 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
925 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
927 2006-03-10 Paul Brook <paul@codesourcery.com>
929 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
931 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
933 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
934 first. Correct mask of bb "B" opcode.
936 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
938 * i386.h (i386_optab): Support Intel Merom New Instructions.
940 2006-02-24 Paul Brook <paul@codesourcery.com>
942 * arm.h: Add V7 feature bits.
944 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
946 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
948 2006-01-31 Paul Brook <paul@codesourcery.com>
949 Richard Earnshaw <rearnsha@arm.com>
951 * arm.h: Use ARM_CPU_FEATURE.
952 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
953 (arm_feature_set): Change to a structure.
954 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
955 ARM_FEATURE): New macros.
957 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
959 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
960 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
961 (ADD_PC_INCR_OPCODE): Don't define.
963 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
966 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
968 2005-11-14 David Ung <davidu@mips.com>
970 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
971 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
972 save/restore encoding of the args field.
974 2005-10-28 Dave Brolley <brolley@redhat.com>
976 Contribute the following changes:
977 2005-02-16 Dave Brolley <brolley@redhat.com>
979 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
980 cgen_isa_mask_* to cgen_bitset_*.
983 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
985 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
986 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
987 (CGEN_CPU_TABLE): Make isas a ponter.
989 2003-09-29 Dave Brolley <brolley@redhat.com>
991 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
992 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
993 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
995 2002-12-13 Dave Brolley <brolley@redhat.com>
997 * cgen.h (symcat.h): #include it.
998 (cgen-bitset.h): #include it.
999 (CGEN_ATTR_VALUE_TYPE): Now a union.
1000 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1001 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1002 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1003 * cgen-bitset.h: New file.
1005 2005-09-30 Catherine Moore <clm@cm00re.com>
1009 2005-10-24 Jan Beulich <jbeulich@novell.com>
1011 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1014 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1016 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1017 Add FLAG_STRICT to pa10 ftest opcode.
1019 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1021 * hppa.h (pa_opcodes): Remove lha entries.
1023 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1025 * hppa.h (FLAG_STRICT): Revise comment.
1026 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1027 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1030 2005-09-30 Catherine Moore <clm@cm00re.com>
1034 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1036 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1038 2005-09-06 Chao-ying Fu <fu@mips.com>
1040 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1041 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1043 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1044 (INSN_ASE_MASK): Update to include INSN_MT.
1045 (INSN_MT): New define for MT ASE.
1047 2005-08-25 Chao-ying Fu <fu@mips.com>
1049 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1050 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1051 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1052 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1053 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1054 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1056 (INSN_DSP): New define for DSP ASE.
1058 2005-08-18 Alan Modra <amodra@bigpond.net.au>
1062 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1064 * ppc.h (PPC_OPCODE_E300): Define.
1066 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1068 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1070 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1073 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1076 2005-07-27 Jan Beulich <jbeulich@novell.com>
1078 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1079 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1080 Add movq-s as 64-bit variants of movd-s.
1082 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1084 * hppa.h: Fix punctuation in comment.
1086 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1087 implicit space-register addressing. Set space-register bits on opcodes
1088 using implicit space-register addressing. Add various missing pa20
1089 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1090 space-register addressing. Use "fE" instead of "fe" in various
1093 2005-07-18 Jan Beulich <jbeulich@novell.com>
1095 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1097 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1099 * i386.h (i386_optab): Support Intel VMX Instructions.
1101 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1103 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1105 2005-07-05 Jan Beulich <jbeulich@novell.com>
1107 * i386.h (i386_optab): Add new insns.
1109 2005-07-01 Nick Clifton <nickc@redhat.com>
1111 * sparc.h: Add typedefs to structure declarations.
1113 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1116 * i386.h (i386_optab): Update comments for 64bit addressing on
1117 mov. Allow 64bit addressing for mov and movq.
1119 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1121 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1122 respectively, in various floating-point load and store patterns.
1124 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1126 * hppa.h (FLAG_STRICT): Correct comment.
1127 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1128 PA 2.0 mneumonics when equivalent. Entries with cache control
1129 completers now require PA 1.1. Adjust whitespace.
1131 2005-05-19 Anton Blanchard <anton@samba.org>
1133 * ppc.h (PPC_OPCODE_POWER5): Define.
1135 2005-05-10 Nick Clifton <nickc@redhat.com>
1137 * Update the address and phone number of the FSF organization in
1138 the GPL notices in the following files:
1139 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1140 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1141 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1142 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1143 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1144 tic54x.h, tic80.h, v850.h, vax.h
1146 2005-05-09 Jan Beulich <jbeulich@novell.com>
1148 * i386.h (i386_optab): Add ht and hnt.
1150 2005-04-18 Mark Kettenis <kettenis@gnu.org>
1152 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1153 Add xcrypt-ctr. Provide aliases without hyphens.
1155 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1157 Moved from ../ChangeLog
1159 2005-04-12 Paul Brook <paul@codesourcery.com>
1160 * m88k.h: Rename psr macros to avoid conflicts.
1162 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1163 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1164 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1165 and ARM_ARCH_V6ZKT2.
1167 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1168 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1169 Remove redundant instruction types.
1170 (struct argument): X_op - new field.
1171 (struct cst4_entry): Remove.
1172 (no_op_insn): Declare.
1174 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1175 * crx.h (enum argtype): Rename types, remove unused types.
1177 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1178 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1179 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1180 (enum operand_type): Rearrange operands, edit comments.
1181 replace us<N> with ui<N> for unsigned immediate.
1182 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1183 displacements (respectively).
1184 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1185 (instruction type): Add NO_TYPE_INS.
1186 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1187 (operand_entry): New field - 'flags'.
1188 (operand flags): New.
1190 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1191 * crx.h (operand_type): Remove redundant types i3, i4,
1193 Add new unsigned immediate types us3, us4, us5, us16.
1195 2005-04-12 Mark Kettenis <kettenis@gnu.org>
1197 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1198 adjust them accordingly.
1200 2005-04-01 Jan Beulich <jbeulich@novell.com>
1202 * i386.h (i386_optab): Add rdtscp.
1204 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1206 * i386.h (i386_optab): Don't allow the `l' suffix for moving
1207 between memory and segment register. Allow movq for moving between
1208 general-purpose register and segment register.
1210 2005-02-09 Jan Beulich <jbeulich@novell.com>
1213 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1214 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1217 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1219 * m68k.h (m68008, m68ec030, m68882): Remove.
1221 (cpu_m68k, cpu_cf): New.
1222 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1223 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1225 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
1227 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1228 * cgen.h (enum cgen_parse_operand_type): Add
1229 CGEN_PARSE_OPERAND_SYMBOLIC.
1231 2005-01-21 Fred Fish <fnf@specifixinc.com>
1233 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1234 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1235 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1237 2005-01-19 Fred Fish <fnf@specifixinc.com>
1239 * mips.h (struct mips_opcode): Add new pinfo2 member.
1240 (INSN_ALIAS): New define for opcode table entries that are
1241 specific instances of another entry, such as 'move' for an 'or'
1242 with a zero operand.
1243 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1244 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1246 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1248 * mips.h (CPU_RM9000): Define.
1249 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1251 2004-11-25 Jan Beulich <jbeulich@novell.com>
1253 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1254 to/from test registers are illegal in 64-bit mode. Add missing
1255 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1256 (previously one had to explicitly encode a rex64 prefix). Re-enable
1257 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1258 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1260 2004-11-23 Jan Beulich <jbeulich@novell.com>
1262 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1263 available only with SSE2. Change the MMX additions introduced by SSE
1264 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1265 instructions by their now designated identifier (since combining i686
1266 and 3DNow! does not really imply 3DNow!A).
1268 2004-11-19 Alan Modra <amodra@bigpond.net.au>
1270 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1271 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1273 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1274 Vineet Sharma <vineets@noida.hcltech.com>
1276 * maxq.h: New file: Disassembly information for the maxq port.
1278 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1280 * i386.h (i386_optab): Put back "movzb".
1282 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
1284 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1285 comments. Remove member cris_ver_sim. Add members
1286 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1287 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1288 (struct cris_support_reg, struct cris_cond15): New types.
1289 (cris_conds15): Declare.
1290 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1291 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1292 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1293 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1294 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1295 SIZE_FIELD_UNSIGNED.
1297 2004-11-04 Jan Beulich <jbeulich@novell.com>
1299 * i386.h (sldx_Suf): Remove.
1300 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1301 (q_FP): Define, implying no REX64.
1302 (x_FP, sl_FP): Imply FloatMF.
1303 (i386_optab): Split reg and mem forms of moving from segment registers
1304 so that the memory forms can ignore the 16-/32-bit operand size
1305 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1306 all non-floating-point instructions. Unite 32- and 64-bit forms of
1307 movsx, movzx, and movd. Adjust floating point operations for the above
1308 changes to the *FP macros. Add DefaultSize to floating point control
1309 insns operating on larger memory ranges. Remove left over comments
1310 hinting at certain insns being Intel-syntax ones where the ones
1311 actually meant are already gone.
1313 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1315 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1318 2004-09-30 Paul Brook <paul@codesourcery.com>
1320 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1321 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1323 2004-09-11 Theodore A. Roth <troth@openavr.org>
1325 * avr.h: Add support for
1326 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1328 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1330 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1332 2004-08-24 Dmitry Diky <diwil@spec.ru>
1334 * msp430.h (msp430_opc): Add new instructions.
1335 (msp430_rcodes): Declare new instructions.
1336 (msp430_hcodes): Likewise..
1338 2004-08-13 Nick Clifton <nickc@redhat.com>
1341 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1344 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1346 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1348 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1350 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1352 2004-07-21 Jan Beulich <jbeulich@novell.com>
1354 * i386.h: Adjust instruction descriptions to better match the
1357 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
1359 * arm.h: Remove all old content. Replace with architecture defines
1360 from gas/config/tc-arm.c.
1362 2004-07-09 Andreas Schwab <schwab@suse.de>
1364 * m68k.h: Fix comment.
1366 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1370 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1372 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1374 2004-05-24 Peter Barada <peter@the-baradas.com>
1376 * m68k.h: Add 'size' to m68k_opcode.
1378 2004-05-05 Peter Barada <peter@the-baradas.com>
1380 * m68k.h: Switch from ColdFire chip name to core variant.
1382 2004-04-22 Peter Barada <peter@the-baradas.com>
1384 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1385 descriptions for new EMAC cases.
1386 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1387 handle Motorola MAC syntax.
1388 Allow disassembly of ColdFire V4e object files.
1390 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1392 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1394 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1396 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1398 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1400 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1402 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1404 * i386.h (i386_optab): Added xstore/xcrypt insns.
1406 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1408 * h8300.h (32bit ldc/stc): Add relaxing support.
1410 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1412 * h8300.h (BITOP): Pass MEMRELAX flag.
1414 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1416 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1419 For older changes see ChangeLog-9103
1425 version-control: never