1 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
3 * mips.h: Document "+i".
5 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
7 * mips.h: Remove "mi" documentation. Update "mh" documentation.
8 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
10 (INSN2_WRITE_GPR_MHI): Rename to...
11 (INSN2_WRITE_GPR_MH): ...this.
13 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
15 * mips.h: Remove documentation of "+D" and "+T".
17 2013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
19 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
20 Use "source" rather than "destination" for microMIPS "G".
22 2013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
24 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
27 2013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
29 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
31 2013-06-17 Catherine Moore <clm@codesourcery.com>
32 Maciej W. Rozycki <macro@codesourcery.com>
33 Chao-Ying Fu <fu@mips.com>
35 * mips.h (OP_SH_EVAOFFSET): Define.
36 (OP_MASK_EVAOFFSET): Define.
37 (INSN_ASE_MASK): Delete.
39 (M_CACHEE_AB, M_CACHEE_OB): New.
40 (M_LBE_OB, M_LBE_AB): New.
41 (M_LBUE_OB, M_LBUE_AB): New.
42 (M_LHE_OB, M_LHE_AB): New.
43 (M_LHUE_OB, M_LHUE_AB): New.
44 (M_LLE_AB, M_LLE_OB): New.
45 (M_LWE_OB, M_LWE_AB): New.
46 (M_LWLE_AB, M_LWLE_OB): New.
47 (M_LWRE_AB, M_LWRE_OB): New.
48 (M_PREFE_AB, M_PREFE_OB): New.
49 (M_SCE_AB, M_SCE_OB): New.
50 (M_SBE_OB, M_SBE_AB): New.
51 (M_SHE_OB, M_SHE_AB): New.
52 (M_SWE_OB, M_SWE_AB): New.
53 (M_SWLE_AB, M_SWLE_OB): New.
54 (M_SWRE_AB, M_SWRE_OB): New.
55 (MICROMIPSOP_SH_EVAOFFSET): Define.
56 (MICROMIPSOP_MASK_EVAOFFSET): Define.
58 2013-06-12 Sandra Loosemore <sandra@codesourcery.com>
60 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
62 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
64 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
66 2013-05-09 Andrew Pinski <apinski@cavium.com>
68 * mips.h (OP_MASK_CODE10): Correct definition.
69 (OP_SH_CODE10): Likewise.
70 Add a comment that "+J" is used now for OP_*CODE10.
71 (INSN_ASE_MASK): Update.
72 (INSN_VIRT): New macro.
73 (INSN_VIRT64): New macro
75 2013-05-02 Nick Clifton <nickc@redhat.com>
77 * msp430.h: Add patterns for MSP430X instructions.
79 2013-04-06 David S. Miller <davem@davemloft.net>
81 * sparc.h (F_PREFERRED): Define.
82 (F_PREF_ALIAS): Define.
84 2013-04-03 Nick Clifton <nickc@redhat.com>
86 * v850.h (V850_INVERSE_PCREL): Define.
88 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
91 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
93 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
96 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
98 * tic6xc-opcode-table.h: Add 16-bit insns.
99 * tic6x.h: Add support for 16-bit insns.
101 2013-03-21 Michael Schewe <michael.schewe@gmx.net>
103 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
104 and mov.b/w/l Rs,@(d:32,ERd).
106 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
109 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
110 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
111 tic6x_operand_xregpair operand coding type.
112 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
113 opcode field, usu ORXREGD1324 for the src2 operand and remove the
116 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
119 * tic6x.h (enum tic6x_coding_method): Add
120 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
121 separately the msb and lsb of a register pair. This is needed to
122 encode the opcodes in the same way as TI assembler does.
123 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
124 and rsqrdp opcodes to use the new field coding types.
126 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
128 * arm.h (CRC_EXT_ARMV8): New constant.
129 (ARCH_CRC_ARMV8): New macro.
131 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
133 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
135 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
136 Andrew Jenner <andrew@codesourcery.com>
138 Based on patches from Altera Corporation.
142 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
144 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
146 2013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
149 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
151 2013-01-24 Nick Clifton <nickc@redhat.com>
153 * v850.h: Add e3v5 support.
155 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
157 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
159 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
161 * ppc.h (PPC_OPCODE_POWER8): New define.
162 (PPC_OPCODE_HTM): Likewise.
164 2013-01-10 Will Newton <will.newton@imgtec.com>
168 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
170 * cr16.h (make_instruction): Rename to cr16_make_instruction.
171 (match_opcode): Rename to cr16_match_opcode.
173 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
175 * mips.h: Add support for r5900 instructions including lq and sq.
177 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
179 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
180 (make_instruction,match_opcode): Added function prototypes.
181 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
183 2012-11-23 Alan Modra <amodra@gmail.com>
185 * ppc.h (ppc_parse_cpu): Update prototype.
187 2012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
189 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
190 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
192 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
194 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
196 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
198 * ia64.h (ia64_opnd): Add new operand types.
200 2012-08-21 David S. Miller <davem@davemloft.net>
202 * sparc.h (F3F4): New macro.
204 2012-08-13 Ian Bolton <ian.bolton@arm.com>
205 Laurent Desnogues <laurent.desnogues@arm.com>
206 Jim MacArthur <jim.macarthur@arm.com>
207 Marcus Shawcroft <marcus.shawcroft@arm.com>
208 Nigel Stephens <nigel.stephens@arm.com>
209 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
210 Richard Earnshaw <rearnsha@arm.com>
211 Sofiane Naci <sofiane.naci@arm.com>
212 Tejas Belagod <tejas.belagod@arm.com>
213 Yufeng Zhang <yufeng.zhang@arm.com>
215 * aarch64.h: New file.
217 2012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
218 Maciej W. Rozycki <macro@codesourcery.com>
220 * mips.h (mips_opcode): Add the exclusions field.
221 (OPCODE_IS_MEMBER): Remove macro.
222 (cpu_is_member): New inline function.
223 (opcode_is_member): Likewise.
225 2012-07-31 Chao-Ying Fu <fu@mips.com>
226 Catherine Moore <clm@codesourcery.com>
227 Maciej W. Rozycki <macro@codesourcery.com>
229 * mips.h: Document microMIPS DSP ASE usage.
230 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
231 microMIPS DSP ASE support.
232 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
233 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
234 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
235 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
236 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
237 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
238 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
240 2012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
242 * mips.h: Fix a typo in description.
244 2012-06-07 Georg-Johann Lay <avr@gjlay.de>
246 * avr.h: (AVR_ISA_XCH): New define.
247 (AVR_ISA_XMEGA): Use it.
248 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
250 2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
252 * m68hc11.h: Add XGate definitions.
253 (struct m68hc11_opcode): Add xg_mask field.
255 2012-05-14 Catherine Moore <clm@codesourcery.com>
256 Maciej W. Rozycki <macro@codesourcery.com>
257 Rhonda Wittels <rhonda@codesourcery.com>
259 * ppc.h (PPC_OPCODE_VLE): New definition.
260 (PPC_OP_SA): New macro.
261 (PPC_OP_SE_VLE): New macro.
262 (PPC_OP): Use a variable shift amount.
263 (powerpc_operand): Update comments.
264 (PPC_OPSHIFT_INV): New macro.
265 (PPC_OPERAND_CR): Replace with...
266 (PPC_OPERAND_CR_BIT): ...this and
267 (PPC_OPERAND_CR_REG): ...this.
270 2012-05-03 Sean Keys <skeys@ipdatasys.com>
272 * xgate.h: Header file for XGATE assembler.
274 2012-04-27 David S. Miller <davem@davemloft.net>
276 * sparc.h: Document new arg code' )' for crypto RS3
279 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
280 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
281 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
282 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
283 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
284 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
285 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
286 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
287 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
288 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
289 HWCAP_CBCOND, HWCAP_CRC32): New defines.
291 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
293 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
295 2012-02-27 Alan Modra <amodra@gmail.com>
297 * crx.h (cst4_map): Update declaration.
299 2012-02-25 Walter Lee <walt@tilera.com>
301 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
303 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
304 TILEPRO_OPC_LW_TLS_SN.
306 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
308 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
309 (XRELEASE_PREFIX_OPCODE): Likewise.
311 2011-12-08 Andrew Pinski <apinski@cavium.com>
312 Adam Nemet <anemet@caviumnetworks.com>
314 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
315 (INSN_OCTEON2): New macro.
316 (CPU_OCTEON2): New macro.
317 (OPCODE_IS_MEMBER): Add Octeon2.
319 2011-11-29 Andrew Pinski <apinski@cavium.com>
321 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
322 (INSN_OCTEONP): New macro.
323 (CPU_OCTEONP): New macro.
324 (OPCODE_IS_MEMBER): Add Octeon+.
325 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
327 2011-11-01 DJ Delorie <dj@redhat.com>
331 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
333 * mips.h: Fix a typo in description.
335 2011-09-21 David S. Miller <davem@davemloft.net>
337 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
338 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
339 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
340 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
342 2011-08-09 Chao-ying Fu <fu@mips.com>
343 Maciej W. Rozycki <macro@codesourcery.com>
345 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
346 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
347 (INSN_ASE_MASK): Add the MCU bit.
348 (INSN_MCU): New macro.
349 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
350 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
352 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
354 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
355 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
356 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
357 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
358 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
359 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
360 (INSN2_READ_GPR_MMN): Likewise.
361 (INSN2_READ_FPR_D): Change the bit used.
362 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
363 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
364 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
365 (INSN2_COND_BRANCH): Likewise.
366 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
367 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
368 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
369 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
370 (INSN2_MOD_GPR_MN): Likewise.
372 2011-08-05 David S. Miller <davem@davemloft.net>
374 * sparc.h: Document new format codes '4', '5', and '('.
375 (OPF_LOW4, RS3): New macros.
377 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
379 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
380 order of flags documented.
382 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
384 * mips.h: Clarify the description of microMIPS instruction
386 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
388 2011-07-24 Chao-ying Fu <fu@mips.com>
389 Maciej W. Rozycki <macro@codesourcery.com>
391 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
392 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
393 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
394 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
395 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
396 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
397 (OP_MASK_RS3, OP_SH_RS3): Likewise.
398 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
399 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
400 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
401 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
402 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
403 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
404 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
405 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
406 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
407 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
408 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
409 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
410 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
411 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
412 (INSN_WRITE_GPR_S): New macro.
413 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
414 (INSN2_READ_FPR_D): Likewise.
415 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
416 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
417 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
418 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
419 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
420 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
421 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
422 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
423 (CPU_MICROMIPS): New macro.
424 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
425 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
426 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
427 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
428 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
429 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
430 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
431 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
432 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
433 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
434 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
435 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
436 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
437 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
438 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
439 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
440 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
441 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
442 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
443 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
444 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
445 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
446 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
447 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
448 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
449 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
450 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
451 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
452 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
453 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
454 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
455 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
456 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
457 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
458 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
459 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
460 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
461 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
462 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
463 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
464 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
465 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
466 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
467 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
468 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
469 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
470 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
471 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
472 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
473 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
474 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
475 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
476 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
477 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
478 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
479 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
480 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
481 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
482 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
483 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
484 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
485 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
486 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
487 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
488 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
489 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
490 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
491 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
492 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
493 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
494 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
495 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
496 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
497 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
498 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
499 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
500 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
501 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
502 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
503 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
504 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
505 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
506 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
507 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
508 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
509 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
510 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
511 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
512 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
513 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
514 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
515 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
516 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
517 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
518 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
519 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
520 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
521 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
522 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
523 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
524 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
525 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
526 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
527 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
528 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
529 (micromips_opcodes): New declaration.
530 (bfd_micromips_num_opcodes): Likewise.
532 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
534 * mips.h (INSN_TRAP): Rename to...
535 (INSN_NO_DELAY_SLOT): ... this.
536 (INSN_SYNC): Remove macro.
538 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
540 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
541 a duplicate of AVR_ISA_SPM.
543 2011-07-01 Nick Clifton <nickc@redhat.com>
545 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
547 2011-06-18 Robin Getz <robin.getz@analog.com>
549 * bfin.h (is_macmod_signed): New func
551 2011-06-18 Mike Frysinger <vapier@gentoo.org>
553 * bfin.h (is_macmod_pmove): Add missing space before func args.
554 (is_macmod_hmove): Likewise.
556 2011-06-13 Walter Lee <walt@tilera.com>
558 * tilegx.h: New file.
559 * tilepro.h: New file.
561 2011-05-31 Paul Brook <paul@codesourcery.com>
563 * arm.h (ARM_ARCH_V7R_IDIV): Define.
565 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
567 * s390.h: Replace S390_OPERAND_REG_EVEN with
568 S390_OPERAND_REG_PAIR.
570 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
572 * s390.h: Add S390_OPCODE_REG_EVEN flag.
574 2011-04-18 Julian Brown <julian@codesourcery.com>
576 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
578 2011-04-11 Dan McDonald <dan@wellkeeper.com>
581 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
583 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
585 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
586 New instruction set flags.
587 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
589 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
591 * mips.h (M_PREF_AB): New enum value.
593 2011-02-12 Mike Frysinger <vapier@gentoo.org>
595 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
597 (is_macmod_pmove, is_macmod_hmove): New functions.
599 2011-02-11 Mike Frysinger <vapier@gentoo.org>
601 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
603 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
605 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
606 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
608 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
611 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
614 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
617 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
619 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
621 * mips.h: Update commentary after last commit.
623 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
625 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
626 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
627 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
629 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
631 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
633 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
635 * mips.h: Fix previous commit.
637 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
639 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
640 (INSN_LOONGSON_3A): Clear bit 31.
642 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
645 * arm.h (ARM_AEXT_V6M_ONLY): New define.
646 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
647 (ARM_ARCH_V6M_ONLY): New define.
649 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
651 * mips.h (INSN_LOONGSON_3A): Defined.
652 (CPU_LOONGSON_3A): Defined.
653 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
655 2010-10-09 Matt Rice <ratmice@gmail.com>
657 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
658 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
660 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
662 * arm.h (ARM_EXT_VIRT): New define.
663 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
664 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
667 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
669 * arm.h (ARM_AEXT_ADIV): New define.
670 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
672 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
674 * arm.h (ARM_EXT_OS): New define.
675 (ARM_AEXT_V6SM): Likewise.
676 (ARM_ARCH_V6SM): Likewise.
678 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
680 * arm.h (ARM_EXT_MP): Add.
681 (ARM_ARCH_V7A_MP): Likewise.
683 2010-09-22 Mike Frysinger <vapier@gentoo.org>
685 * bfin.h: Declare pseudoChr structs/defines.
687 2010-09-21 Mike Frysinger <vapier@gentoo.org>
689 * bfin.h: Strip trailing whitespace.
691 2010-07-29 DJ Delorie <dj@redhat.com>
693 * rx.h (RX_Operand_Type): Add TwoReg.
694 (RX_Opcode_ID): Remove ediv and ediv2.
696 2010-07-27 DJ Delorie <dj@redhat.com>
698 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
700 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
701 Ina Pandit <ina.pandit@kpitcummins.com>
703 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
704 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
705 PROCESSOR_V850E2_ALL.
706 Remove PROCESSOR_V850EA support.
707 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
708 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
709 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
710 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
711 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
712 V850_OPERAND_PERCENT.
713 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
715 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
718 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
720 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
721 (MIPS16_INSN_BRANCH): Rename to...
722 (MIPS16_INSN_COND_BRANCH): ... this.
724 2010-07-03 Alan Modra <amodra@gmail.com>
726 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
727 Renumber other PPC_OPCODE defines.
729 2010-07-03 Alan Modra <amodra@gmail.com>
731 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
733 2010-06-29 Alan Modra <amodra@gmail.com>
735 * maxq.h: Delete file.
737 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
739 * ppc.h (PPC_OPCODE_E500): Define.
741 2010-05-26 Catherine Moore <clm@codesourcery.com>
743 * opcode/mips.h (INSN_MIPS16): Remove.
745 2010-04-21 Joseph Myers <joseph@codesourcery.com>
747 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
749 2010-04-15 Nick Clifton <nickc@redhat.com>
751 * alpha.h: Update copyright notice to use GPLv3.
757 * convex.h: Likewise.
771 * m68hc11.h: Likewise.
777 * mn10200.h: Likewise.
778 * mn10300.h: Likewise.
779 * msp430.h: Likewise.
790 * score-datadep.h: Likewise.
791 * score-inst.h: Likewise.
793 * spu-insns.h: Likewise.
797 * tic54x.h: Likewise.
802 2010-03-25 Joseph Myers <joseph@codesourcery.com>
804 * tic6x-control-registers.h, tic6x-insn-formats.h,
805 tic6x-opcode-table.h, tic6x.h: New.
807 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
809 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
811 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
813 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
815 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
817 * ia64.h (ia64_find_opcode): Remove argument name.
818 (ia64_find_next_opcode): Likewise.
819 (ia64_dis_opcode): Likewise.
820 (ia64_free_opcode): Likewise.
821 (ia64_find_dependency): Likewise.
823 2009-11-22 Doug Evans <dje@sebabeach.org>
825 * cgen.h: Include bfd_stdint.h.
826 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
828 2009-11-18 Paul Brook <paul@codesourcery.com>
830 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
832 2009-11-17 Paul Brook <paul@codesourcery.com>
833 Daniel Jacobowitz <dan@codesourcery.com>
835 * arm.h (ARM_EXT_V6_DSP): Define.
836 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
837 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
839 2009-11-04 DJ Delorie <dj@redhat.com>
841 * rx.h (rx_decode_opcode) (mvtipl): Add.
842 (mvtcp, mvfcp, opecp): Remove.
844 2009-11-02 Paul Brook <paul@codesourcery.com>
846 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
847 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
848 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
849 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
850 FPU_ARCH_NEON_VFP_V4): Define.
852 2009-10-23 Doug Evans <dje@sebabeach.org>
854 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
855 * cgen.h: Update. Improve multi-inclusion macro name.
857 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
859 * ppc.h (PPC_OPCODE_476): Define.
861 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
863 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
865 2009-09-29 DJ Delorie <dj@redhat.com>
869 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
871 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
873 2009-09-21 Ben Elliston <bje@au.ibm.com>
875 * ppc.h (PPC_OPCODE_PPCA2): New.
877 2009-09-05 Martin Thuresson <martin@mtme.org>
879 * ia64.h (struct ia64_operand): Renamed member class to op_class.
881 2009-08-29 Martin Thuresson <martin@mtme.org>
883 * tic30.h (template): Rename type template to
884 insn_template. Updated code to use new name.
885 * tic54x.h (template): Rename type template to
888 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
890 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
892 2009-06-11 Anthony Green <green@moxielogic.com>
894 * moxie.h (MOXIE_F3_PCREL): Define.
895 (moxie_form3_opc_info): Grow.
897 2009-06-06 Anthony Green <green@moxielogic.com>
899 * moxie.h (MOXIE_F1_M): Define.
901 2009-04-15 Anthony Green <green@moxielogic.com>
905 2009-04-06 DJ Delorie <dj@redhat.com>
907 * h8300.h: Add relaxation attributes to MOVA opcodes.
909 2009-03-10 Alan Modra <amodra@bigpond.net.au>
911 * ppc.h (ppc_parse_cpu): Declare.
913 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
915 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
916 and _IMM11 for mbitclr and mbitset.
917 * score-datadep.h: Update dependency information.
919 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
921 * ppc.h (PPC_OPCODE_POWER7): New.
923 2009-02-06 Doug Evans <dje@google.com>
925 * i386.h: Add comment regarding sse* insns and prefixes.
927 2009-02-03 Sandip Matte <sandip@rmicorp.com>
929 * mips.h (INSN_XLR): Define.
930 (INSN_CHIP_MASK): Update.
932 (OPCODE_IS_MEMBER): Update.
933 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
935 2009-01-28 Doug Evans <dje@google.com>
937 * opcode/i386.h: Add multiple inclusion protection.
938 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
939 (EDI_REG_NUM): New macros.
940 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
941 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
942 (REX_PREFIX_P): New macro.
944 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
946 * ppc.h (struct powerpc_opcode): New field "deprecated".
947 (PPC_OPCODE_NOPOWER4): Delete.
949 2008-11-28 Joshua Kinard <kumba@gentoo.org>
951 * mips.h: Define CPU_R14000, CPU_R16000.
952 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
954 2008-11-18 Catherine Moore <clm@codesourcery.com>
956 * arm.h (FPU_NEON_FP16): New.
957 (FPU_ARCH_NEON_FP16): New.
959 2008-11-06 Chao-ying Fu <fu@mips.com>
961 * mips.h: Doucument '1' for 5-bit sync type.
963 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
965 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
968 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
970 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
972 2008-07-30 Michael J. Eager <eager@eagercon.com>
974 * ppc.h (PPC_OPCODE_405): Define.
975 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
977 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
979 * ppc.h (ppc_cpu_t): New typedef.
980 (struct powerpc_opcode <flags>): Use it.
981 (struct powerpc_operand <insert, extract>): Likewise.
982 (struct powerpc_macro <flags>): Likewise.
984 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
986 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
987 Update comment before MIPS16 field descriptors to mention MIPS16.
988 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
990 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
991 New bit masks and shift counts for cins and exts.
993 * mips.h: Document new field descriptors +Q.
994 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
996 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
998 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
999 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1001 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
1003 * ppc.h: (PPC_OPCODE_E500MC): New.
1005 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1007 * i386.h (MAX_OPERANDS): Set to 5.
1008 (MAX_MNEM_SIZE): Changed to 20.
1010 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1012 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1014 2008-03-09 Paul Brook <paul@codesourcery.com>
1016 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1018 2008-03-04 Paul Brook <paul@codesourcery.com>
1020 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1021 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1022 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1024 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
1025 Nick Clifton <nickc@redhat.com>
1028 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1029 with a 32-bit displacement but without the top bit of the 4th byte
1032 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1034 * cr16.h (cr16_num_optab): Declared.
1036 2008-02-14 Hakan Ardo <hakan@debian.org>
1039 * avr.h (AVR_ISA_2xxe): Define.
1041 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1043 * mips.h: Update copyright.
1044 (INSN_CHIP_MASK): New macro.
1045 (INSN_OCTEON): New macro.
1046 (CPU_OCTEON): New macro.
1047 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1049 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1051 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1053 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1055 * avr.h (AVR_ISA_USB162): Add new opcode set.
1056 (AVR_ISA_AVR3): Likewise.
1058 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1060 * mips.h (INSN_LOONGSON_2E): New.
1061 (INSN_LOONGSON_2F): New.
1062 (CPU_LOONGSON_2E): New.
1063 (CPU_LOONGSON_2F): New.
1064 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1066 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1068 * mips.h (INSN_ISA*): Redefine certain values as an
1069 enumeration. Update comments.
1070 (mips_isa_table): New.
1071 (ISA_MIPS*): Redefine to match enumeration.
1072 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1075 2007-08-08 Ben Elliston <bje@au.ibm.com>
1077 * ppc.h (PPC_OPCODE_PPCPS): New.
1079 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1081 * m68k.h: Document j K & E.
1083 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1085 * cr16.h: New file for CR16 target.
1087 2007-05-02 Alan Modra <amodra@bigpond.net.au>
1089 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1091 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1093 * m68k.h (mcfisa_c): New.
1094 (mcfusp, mcf_mask): Adjust.
1096 2007-04-20 Alan Modra <amodra@bigpond.net.au>
1098 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1099 (num_powerpc_operands): Declare.
1100 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1101 (PPC_OPERAND_PLUS1): Define.
1103 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
1105 * i386.h (REX_MODE64): Renamed to ...
1107 (REX_EXTX): Renamed to ...
1109 (REX_EXTY): Renamed to ...
1111 (REX_EXTZ): Renamed to ...
1114 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1116 * i386.h: Add entries from config/tc-i386.h and move tables
1117 to opcodes/i386-opc.h.
1119 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1121 * i386.h (FloatDR): Removed.
1122 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1124 2007-03-01 Alan Modra <amodra@bigpond.net.au>
1126 * spu-insns.h: Add soma double-float insns.
1128 2007-02-20 Thiemo Seufer <ths@mips.com>
1129 Chao-Ying Fu <fu@mips.com>
1131 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1132 (INSN_DSPR2): Add flag for DSP R2 instructions.
1133 (M_BALIGN): New macro.
1135 2007-02-14 Alan Modra <amodra@bigpond.net.au>
1137 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1138 and Seg3ShortFrom with Shortform.
1140 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1143 * i386.h (i386_optab): Put the real "test" before the pseudo
1146 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
1148 * m68k.h (m68010up): OR fido_a.
1150 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
1152 * m68k.h (fido_a): New.
1154 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
1156 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1157 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1160 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1162 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1164 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1166 * score-inst.h (enum score_insn_type): Add Insn_internal.
1168 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1169 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1170 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1171 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1172 Alan Modra <amodra@bigpond.net.au>
1174 * spu-insns.h: New file.
1177 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1179 * ppc.h (PPC_OPCODE_CELL): Define.
1181 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1183 * i386.h : Modify opcode to support for the change in POPCNT opcode
1184 in amdfam10 architecture.
1186 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1188 * i386.h: Replace CpuMNI with CpuSSSE3.
1190 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
1191 Joseph Myers <joseph@codesourcery.com>
1192 Ian Lance Taylor <ian@wasabisystems.com>
1193 Ben Elliston <bje@wasabisystems.com>
1195 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1197 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1199 * score-datadep.h: New file.
1200 * score-inst.h: New file.
1202 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1204 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1205 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1206 movdq2q and movq2dq.
1208 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1209 Michael Meissner <michael.meissner@amd.com>
1211 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1213 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1215 * i386.h (i386_optab): Add "nop" with memory reference.
1217 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1219 * i386.h (i386_optab): Update comment for 64bit NOP.
1221 2006-06-06 Ben Elliston <bje@au.ibm.com>
1222 Anton Blanchard <anton@samba.org>
1224 * ppc.h (PPC_OPCODE_POWER6): Define.
1227 2006-06-05 Thiemo Seufer <ths@mips.com>
1229 * mips.h: Improve description of MT flags.
1231 2006-05-25 Richard Sandiford <richard@codesourcery.com>
1233 * m68k.h (mcf_mask): Define.
1235 2006-05-05 Thiemo Seufer <ths@mips.com>
1236 David Ung <davidu@mips.com>
1238 * mips.h (enum): Add macro M_CACHE_AB.
1240 2006-05-04 Thiemo Seufer <ths@mips.com>
1241 Nigel Stephens <nigel@mips.com>
1242 David Ung <davidu@mips.com>
1244 * mips.h: Add INSN_SMARTMIPS define.
1246 2006-04-30 Thiemo Seufer <ths@mips.com>
1247 David Ung <davidu@mips.com>
1249 * mips.h: Defines udi bits and masks. Add description of
1250 characters which may appear in the args field of udi
1253 2006-04-26 Thiemo Seufer <ths@networkno.de>
1255 * mips.h: Improve comments describing the bitfield instruction
1258 2006-04-26 Julian Brown <julian@codesourcery.com>
1260 * arm.h (FPU_VFP_EXT_V3): Define constant.
1261 (FPU_NEON_EXT_V1): Likewise.
1262 (FPU_VFP_HARD): Update.
1263 (FPU_VFP_V3): Define macro.
1264 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1266 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
1268 * avr.h (AVR_ISA_PWMx): New.
1270 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1272 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1273 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1274 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1275 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1276 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1278 2006-03-10 Paul Brook <paul@codesourcery.com>
1280 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1282 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1284 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1285 first. Correct mask of bb "B" opcode.
1287 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1289 * i386.h (i386_optab): Support Intel Merom New Instructions.
1291 2006-02-24 Paul Brook <paul@codesourcery.com>
1293 * arm.h: Add V7 feature bits.
1295 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1297 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1299 2006-01-31 Paul Brook <paul@codesourcery.com>
1300 Richard Earnshaw <rearnsha@arm.com>
1302 * arm.h: Use ARM_CPU_FEATURE.
1303 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1304 (arm_feature_set): Change to a structure.
1305 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1306 ARM_FEATURE): New macros.
1308 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
1310 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1311 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1312 (ADD_PC_INCR_OPCODE): Don't define.
1314 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1317 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1319 2005-11-14 David Ung <davidu@mips.com>
1321 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1322 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1323 save/restore encoding of the args field.
1325 2005-10-28 Dave Brolley <brolley@redhat.com>
1327 Contribute the following changes:
1328 2005-02-16 Dave Brolley <brolley@redhat.com>
1330 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1331 cgen_isa_mask_* to cgen_bitset_*.
1334 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1336 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1337 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1338 (CGEN_CPU_TABLE): Make isas a ponter.
1340 2003-09-29 Dave Brolley <brolley@redhat.com>
1342 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1343 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1344 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1346 2002-12-13 Dave Brolley <brolley@redhat.com>
1348 * cgen.h (symcat.h): #include it.
1349 (cgen-bitset.h): #include it.
1350 (CGEN_ATTR_VALUE_TYPE): Now a union.
1351 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1352 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1353 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1354 * cgen-bitset.h: New file.
1356 2005-09-30 Catherine Moore <clm@cm00re.com>
1360 2005-10-24 Jan Beulich <jbeulich@novell.com>
1362 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1365 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1367 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1368 Add FLAG_STRICT to pa10 ftest opcode.
1370 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1372 * hppa.h (pa_opcodes): Remove lha entries.
1374 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1376 * hppa.h (FLAG_STRICT): Revise comment.
1377 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1378 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1381 2005-09-30 Catherine Moore <clm@cm00re.com>
1385 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1387 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1389 2005-09-06 Chao-ying Fu <fu@mips.com>
1391 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1392 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1394 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1395 (INSN_ASE_MASK): Update to include INSN_MT.
1396 (INSN_MT): New define for MT ASE.
1398 2005-08-25 Chao-ying Fu <fu@mips.com>
1400 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1401 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1402 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1403 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1404 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1405 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1407 (INSN_DSP): New define for DSP ASE.
1409 2005-08-18 Alan Modra <amodra@bigpond.net.au>
1413 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1415 * ppc.h (PPC_OPCODE_E300): Define.
1417 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1419 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1421 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1424 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1427 2005-07-27 Jan Beulich <jbeulich@novell.com>
1429 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1430 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1431 Add movq-s as 64-bit variants of movd-s.
1433 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1435 * hppa.h: Fix punctuation in comment.
1437 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1438 implicit space-register addressing. Set space-register bits on opcodes
1439 using implicit space-register addressing. Add various missing pa20
1440 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1441 space-register addressing. Use "fE" instead of "fe" in various
1444 2005-07-18 Jan Beulich <jbeulich@novell.com>
1446 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1448 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1450 * i386.h (i386_optab): Support Intel VMX Instructions.
1452 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1454 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1456 2005-07-05 Jan Beulich <jbeulich@novell.com>
1458 * i386.h (i386_optab): Add new insns.
1460 2005-07-01 Nick Clifton <nickc@redhat.com>
1462 * sparc.h: Add typedefs to structure declarations.
1464 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1467 * i386.h (i386_optab): Update comments for 64bit addressing on
1468 mov. Allow 64bit addressing for mov and movq.
1470 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1472 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1473 respectively, in various floating-point load and store patterns.
1475 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1477 * hppa.h (FLAG_STRICT): Correct comment.
1478 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1479 PA 2.0 mneumonics when equivalent. Entries with cache control
1480 completers now require PA 1.1. Adjust whitespace.
1482 2005-05-19 Anton Blanchard <anton@samba.org>
1484 * ppc.h (PPC_OPCODE_POWER5): Define.
1486 2005-05-10 Nick Clifton <nickc@redhat.com>
1488 * Update the address and phone number of the FSF organization in
1489 the GPL notices in the following files:
1490 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1491 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1492 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1493 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1494 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1495 tic54x.h, tic80.h, v850.h, vax.h
1497 2005-05-09 Jan Beulich <jbeulich@novell.com>
1499 * i386.h (i386_optab): Add ht and hnt.
1501 2005-04-18 Mark Kettenis <kettenis@gnu.org>
1503 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1504 Add xcrypt-ctr. Provide aliases without hyphens.
1506 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1508 Moved from ../ChangeLog
1510 2005-04-12 Paul Brook <paul@codesourcery.com>
1511 * m88k.h: Rename psr macros to avoid conflicts.
1513 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1514 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1515 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1516 and ARM_ARCH_V6ZKT2.
1518 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1519 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1520 Remove redundant instruction types.
1521 (struct argument): X_op - new field.
1522 (struct cst4_entry): Remove.
1523 (no_op_insn): Declare.
1525 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1526 * crx.h (enum argtype): Rename types, remove unused types.
1528 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1529 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1530 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1531 (enum operand_type): Rearrange operands, edit comments.
1532 replace us<N> with ui<N> for unsigned immediate.
1533 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1534 displacements (respectively).
1535 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1536 (instruction type): Add NO_TYPE_INS.
1537 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1538 (operand_entry): New field - 'flags'.
1539 (operand flags): New.
1541 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1542 * crx.h (operand_type): Remove redundant types i3, i4,
1544 Add new unsigned immediate types us3, us4, us5, us16.
1546 2005-04-12 Mark Kettenis <kettenis@gnu.org>
1548 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1549 adjust them accordingly.
1551 2005-04-01 Jan Beulich <jbeulich@novell.com>
1553 * i386.h (i386_optab): Add rdtscp.
1555 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1557 * i386.h (i386_optab): Don't allow the `l' suffix for moving
1558 between memory and segment register. Allow movq for moving between
1559 general-purpose register and segment register.
1561 2005-02-09 Jan Beulich <jbeulich@novell.com>
1564 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1565 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1568 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1570 * m68k.h (m68008, m68ec030, m68882): Remove.
1572 (cpu_m68k, cpu_cf): New.
1573 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1574 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1576 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
1578 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1579 * cgen.h (enum cgen_parse_operand_type): Add
1580 CGEN_PARSE_OPERAND_SYMBOLIC.
1582 2005-01-21 Fred Fish <fnf@specifixinc.com>
1584 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1585 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1586 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1588 2005-01-19 Fred Fish <fnf@specifixinc.com>
1590 * mips.h (struct mips_opcode): Add new pinfo2 member.
1591 (INSN_ALIAS): New define for opcode table entries that are
1592 specific instances of another entry, such as 'move' for an 'or'
1593 with a zero operand.
1594 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1595 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1597 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1599 * mips.h (CPU_RM9000): Define.
1600 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1602 2004-11-25 Jan Beulich <jbeulich@novell.com>
1604 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1605 to/from test registers are illegal in 64-bit mode. Add missing
1606 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1607 (previously one had to explicitly encode a rex64 prefix). Re-enable
1608 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1609 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1611 2004-11-23 Jan Beulich <jbeulich@novell.com>
1613 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1614 available only with SSE2. Change the MMX additions introduced by SSE
1615 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1616 instructions by their now designated identifier (since combining i686
1617 and 3DNow! does not really imply 3DNow!A).
1619 2004-11-19 Alan Modra <amodra@bigpond.net.au>
1621 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1622 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1624 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1625 Vineet Sharma <vineets@noida.hcltech.com>
1627 * maxq.h: New file: Disassembly information for the maxq port.
1629 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1631 * i386.h (i386_optab): Put back "movzb".
1633 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
1635 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1636 comments. Remove member cris_ver_sim. Add members
1637 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1638 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1639 (struct cris_support_reg, struct cris_cond15): New types.
1640 (cris_conds15): Declare.
1641 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1642 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1643 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1644 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1645 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1646 SIZE_FIELD_UNSIGNED.
1648 2004-11-04 Jan Beulich <jbeulich@novell.com>
1650 * i386.h (sldx_Suf): Remove.
1651 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1652 (q_FP): Define, implying no REX64.
1653 (x_FP, sl_FP): Imply FloatMF.
1654 (i386_optab): Split reg and mem forms of moving from segment registers
1655 so that the memory forms can ignore the 16-/32-bit operand size
1656 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1657 all non-floating-point instructions. Unite 32- and 64-bit forms of
1658 movsx, movzx, and movd. Adjust floating point operations for the above
1659 changes to the *FP macros. Add DefaultSize to floating point control
1660 insns operating on larger memory ranges. Remove left over comments
1661 hinting at certain insns being Intel-syntax ones where the ones
1662 actually meant are already gone.
1664 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1666 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1669 2004-09-30 Paul Brook <paul@codesourcery.com>
1671 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1672 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1674 2004-09-11 Theodore A. Roth <troth@openavr.org>
1676 * avr.h: Add support for
1677 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1679 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1681 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1683 2004-08-24 Dmitry Diky <diwil@spec.ru>
1685 * msp430.h (msp430_opc): Add new instructions.
1686 (msp430_rcodes): Declare new instructions.
1687 (msp430_hcodes): Likewise..
1689 2004-08-13 Nick Clifton <nickc@redhat.com>
1692 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1695 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1697 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1699 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1701 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1703 2004-07-21 Jan Beulich <jbeulich@novell.com>
1705 * i386.h: Adjust instruction descriptions to better match the
1708 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
1710 * arm.h: Remove all old content. Replace with architecture defines
1711 from gas/config/tc-arm.c.
1713 2004-07-09 Andreas Schwab <schwab@suse.de>
1715 * m68k.h: Fix comment.
1717 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1721 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1723 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1725 2004-05-24 Peter Barada <peter@the-baradas.com>
1727 * m68k.h: Add 'size' to m68k_opcode.
1729 2004-05-05 Peter Barada <peter@the-baradas.com>
1731 * m68k.h: Switch from ColdFire chip name to core variant.
1733 2004-04-22 Peter Barada <peter@the-baradas.com>
1735 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1736 descriptions for new EMAC cases.
1737 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1738 handle Motorola MAC syntax.
1739 Allow disassembly of ColdFire V4e object files.
1741 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1743 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1745 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1747 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1749 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1751 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1753 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1755 * i386.h (i386_optab): Added xstore/xcrypt insns.
1757 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1759 * h8300.h (32bit ldc/stc): Add relaxing support.
1761 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1763 * h8300.h (BITOP): Pass MEMRELAX flag.
1765 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1767 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1770 For older changes see ChangeLog-9103
1772 Copyright (C) 2004-2012 Free Software Foundation, Inc.
1774 Copying and distribution of this file, with or without modification,
1775 are permitted in any medium without royalty provided the copyright
1776 notice and this notice are preserved.
1782 version-control: never