1 2011-02-12 Mike Frysinger <vapier@gentoo.org>
3 * bfin-dis.c (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2,
6 2011-02-11 Mike Frysinger <vapier@gentoo.org>
8 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
10 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
12 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
13 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
15 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
18 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
21 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
24 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
26 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
28 * mips.h: Update commentary after last commit.
30 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
32 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
33 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
34 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
36 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
38 * mips.h: Fix previous commit.
40 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
42 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
43 (INSN_LOONGSON_3A): Clear bit 31.
45 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
48 * arm.h (ARM_AEXT_V6M_ONLY): New define.
49 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
50 (ARM_ARCH_V6M_ONLY): New define.
52 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
54 * mips.h (INSN_LOONGSON_3A): Defined.
55 (CPU_LOONGSON_3A): Defined.
56 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
58 2010-10-09 Matt Rice <ratmice@gmail.com>
60 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
61 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
63 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
65 * arm.h (ARM_EXT_VIRT): New define.
66 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
67 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
70 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
72 * arm.h (ARM_AEXT_ADIV): New define.
73 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
75 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
77 * arm.h (ARM_EXT_OS): New define.
78 (ARM_AEXT_V6SM): Likewise.
79 (ARM_ARCH_V6SM): Likewise.
81 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
83 * arm.h (ARM_EXT_MP): Add.
84 (ARM_ARCH_V7A_MP): Likewise.
86 2010-09-22 Mike Frysinger <vapier@gentoo.org>
88 * bfin.h: Declare pseudoChr structs/defines.
90 2010-09-21 Mike Frysinger <vapier@gentoo.org>
92 * bfin.h: Strip trailing whitespace.
94 2010-07-29 DJ Delorie <dj@redhat.com>
96 * rx.h (RX_Operand_Type): Add TwoReg.
97 (RX_Opcode_ID): Remove ediv and ediv2.
99 2010-07-27 DJ Delorie <dj@redhat.com>
101 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
103 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
104 Ina Pandit <ina.pandit@kpitcummins.com>
106 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
107 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
108 PROCESSOR_V850E2_ALL.
109 Remove PROCESSOR_V850EA support.
110 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
111 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
112 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
113 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
114 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
115 V850_OPERAND_PERCENT.
116 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
118 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
121 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
123 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
124 (MIPS16_INSN_BRANCH): Rename to...
125 (MIPS16_INSN_COND_BRANCH): ... this.
127 2010-07-03 Alan Modra <amodra@gmail.com>
129 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
130 Renumber other PPC_OPCODE defines.
132 2010-07-03 Alan Modra <amodra@gmail.com>
134 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
136 2010-06-29 Alan Modra <amodra@gmail.com>
138 * maxq.h: Delete file.
140 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
142 * ppc.h (PPC_OPCODE_E500): Define.
144 2010-05-26 Catherine Moore <clm@codesourcery.com>
146 * opcode/mips.h (INSN_MIPS16): Remove.
148 2010-04-21 Joseph Myers <joseph@codesourcery.com>
150 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
152 2010-04-15 Nick Clifton <nickc@redhat.com>
154 * alpha.h: Update copyright notice to use GPLv3.
160 * convex.h: Likewise.
174 * m68hc11.h: Likewise.
180 * mn10200.h: Likewise.
181 * mn10300.h: Likewise.
182 * msp430.h: Likewise.
193 * score-datadep.h: Likewise.
194 * score-inst.h: Likewise.
196 * spu-insns.h: Likewise.
200 * tic54x.h: Likewise.
205 2010-03-25 Joseph Myers <joseph@codesourcery.com>
207 * tic6x-control-registers.h, tic6x-insn-formats.h,
208 tic6x-opcode-table.h, tic6x.h: New.
210 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
212 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
214 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
216 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
218 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
220 * ia64.h (ia64_find_opcode): Remove argument name.
221 (ia64_find_next_opcode): Likewise.
222 (ia64_dis_opcode): Likewise.
223 (ia64_free_opcode): Likewise.
224 (ia64_find_dependency): Likewise.
226 2009-11-22 Doug Evans <dje@sebabeach.org>
228 * cgen.h: Include bfd_stdint.h.
229 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
231 2009-11-18 Paul Brook <paul@codesourcery.com>
233 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
235 2009-11-17 Paul Brook <paul@codesourcery.com>
236 Daniel Jacobowitz <dan@codesourcery.com>
238 * arm.h (ARM_EXT_V6_DSP): Define.
239 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
240 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
242 2009-11-04 DJ Delorie <dj@redhat.com>
244 * rx.h (rx_decode_opcode) (mvtipl): Add.
245 (mvtcp, mvfcp, opecp): Remove.
247 2009-11-02 Paul Brook <paul@codesourcery.com>
249 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
250 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
251 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
252 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
253 FPU_ARCH_NEON_VFP_V4): Define.
255 2009-10-23 Doug Evans <dje@sebabeach.org>
257 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
258 * cgen.h: Update. Improve multi-inclusion macro name.
260 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
262 * ppc.h (PPC_OPCODE_476): Define.
264 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
266 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
268 2009-09-29 DJ Delorie <dj@redhat.com>
272 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
274 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
276 2009-09-21 Ben Elliston <bje@au.ibm.com>
278 * ppc.h (PPC_OPCODE_PPCA2): New.
280 2009-09-05 Martin Thuresson <martin@mtme.org>
282 * ia64.h (struct ia64_operand): Renamed member class to op_class.
284 2009-08-29 Martin Thuresson <martin@mtme.org>
286 * tic30.h (template): Rename type template to
287 insn_template. Updated code to use new name.
288 * tic54x.h (template): Rename type template to
291 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
293 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
295 2009-06-11 Anthony Green <green@moxielogic.com>
297 * moxie.h (MOXIE_F3_PCREL): Define.
298 (moxie_form3_opc_info): Grow.
300 2009-06-06 Anthony Green <green@moxielogic.com>
302 * moxie.h (MOXIE_F1_M): Define.
304 2009-04-15 Anthony Green <green@moxielogic.com>
308 2009-04-06 DJ Delorie <dj@redhat.com>
310 * h8300.h: Add relaxation attributes to MOVA opcodes.
312 2009-03-10 Alan Modra <amodra@bigpond.net.au>
314 * ppc.h (ppc_parse_cpu): Declare.
316 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
318 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
319 and _IMM11 for mbitclr and mbitset.
320 * score-datadep.h: Update dependency information.
322 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
324 * ppc.h (PPC_OPCODE_POWER7): New.
326 2009-02-06 Doug Evans <dje@google.com>
328 * i386.h: Add comment regarding sse* insns and prefixes.
330 2009-02-03 Sandip Matte <sandip@rmicorp.com>
332 * mips.h (INSN_XLR): Define.
333 (INSN_CHIP_MASK): Update.
335 (OPCODE_IS_MEMBER): Update.
336 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
338 2009-01-28 Doug Evans <dje@google.com>
340 * opcode/i386.h: Add multiple inclusion protection.
341 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
342 (EDI_REG_NUM): New macros.
343 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
344 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
345 (REX_PREFIX_P): New macro.
347 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
349 * ppc.h (struct powerpc_opcode): New field "deprecated".
350 (PPC_OPCODE_NOPOWER4): Delete.
352 2008-11-28 Joshua Kinard <kumba@gentoo.org>
354 * mips.h: Define CPU_R14000, CPU_R16000.
355 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
357 2008-11-18 Catherine Moore <clm@codesourcery.com>
359 * arm.h (FPU_NEON_FP16): New.
360 (FPU_ARCH_NEON_FP16): New.
362 2008-11-06 Chao-ying Fu <fu@mips.com>
364 * mips.h: Doucument '1' for 5-bit sync type.
366 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
368 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
371 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
373 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
375 2008-07-30 Michael J. Eager <eager@eagercon.com>
377 * ppc.h (PPC_OPCODE_405): Define.
378 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
380 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
382 * ppc.h (ppc_cpu_t): New typedef.
383 (struct powerpc_opcode <flags>): Use it.
384 (struct powerpc_operand <insert, extract>): Likewise.
385 (struct powerpc_macro <flags>): Likewise.
387 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
389 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
390 Update comment before MIPS16 field descriptors to mention MIPS16.
391 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
393 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
394 New bit masks and shift counts for cins and exts.
396 * mips.h: Document new field descriptors +Q.
397 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
399 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
401 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
402 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
404 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
406 * ppc.h: (PPC_OPCODE_E500MC): New.
408 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
410 * i386.h (MAX_OPERANDS): Set to 5.
411 (MAX_MNEM_SIZE): Changed to 20.
413 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
415 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
417 2008-03-09 Paul Brook <paul@codesourcery.com>
419 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
421 2008-03-04 Paul Brook <paul@codesourcery.com>
423 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
424 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
425 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
427 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
428 Nick Clifton <nickc@redhat.com>
431 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
432 with a 32-bit displacement but without the top bit of the 4th byte
435 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
437 * cr16.h (cr16_num_optab): Declared.
439 2008-02-14 Hakan Ardo <hakan@debian.org>
442 * avr.h (AVR_ISA_2xxe): Define.
444 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
446 * mips.h: Update copyright.
447 (INSN_CHIP_MASK): New macro.
448 (INSN_OCTEON): New macro.
449 (CPU_OCTEON): New macro.
450 (OPCODE_IS_MEMBER): Handle Octeon instructions.
452 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
454 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
456 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
458 * avr.h (AVR_ISA_USB162): Add new opcode set.
459 (AVR_ISA_AVR3): Likewise.
461 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
463 * mips.h (INSN_LOONGSON_2E): New.
464 (INSN_LOONGSON_2F): New.
465 (CPU_LOONGSON_2E): New.
466 (CPU_LOONGSON_2F): New.
467 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
469 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
471 * mips.h (INSN_ISA*): Redefine certain values as an
472 enumeration. Update comments.
473 (mips_isa_table): New.
474 (ISA_MIPS*): Redefine to match enumeration.
475 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
478 2007-08-08 Ben Elliston <bje@au.ibm.com>
480 * ppc.h (PPC_OPCODE_PPCPS): New.
482 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
484 * m68k.h: Document j K & E.
486 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
488 * cr16.h: New file for CR16 target.
490 2007-05-02 Alan Modra <amodra@bigpond.net.au>
492 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
494 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
496 * m68k.h (mcfisa_c): New.
497 (mcfusp, mcf_mask): Adjust.
499 2007-04-20 Alan Modra <amodra@bigpond.net.au>
501 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
502 (num_powerpc_operands): Declare.
503 (PPC_OPERAND_SIGNED et al): Redefine as hex.
504 (PPC_OPERAND_PLUS1): Define.
506 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
508 * i386.h (REX_MODE64): Renamed to ...
510 (REX_EXTX): Renamed to ...
512 (REX_EXTY): Renamed to ...
514 (REX_EXTZ): Renamed to ...
517 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
519 * i386.h: Add entries from config/tc-i386.h and move tables
520 to opcodes/i386-opc.h.
522 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
524 * i386.h (FloatDR): Removed.
525 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
527 2007-03-01 Alan Modra <amodra@bigpond.net.au>
529 * spu-insns.h: Add soma double-float insns.
531 2007-02-20 Thiemo Seufer <ths@mips.com>
532 Chao-Ying Fu <fu@mips.com>
534 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
535 (INSN_DSPR2): Add flag for DSP R2 instructions.
536 (M_BALIGN): New macro.
538 2007-02-14 Alan Modra <amodra@bigpond.net.au>
540 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
541 and Seg3ShortFrom with Shortform.
543 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
546 * i386.h (i386_optab): Put the real "test" before the pseudo
549 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
551 * m68k.h (m68010up): OR fido_a.
553 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
555 * m68k.h (fido_a): New.
557 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
559 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
560 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
563 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
565 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
567 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
569 * score-inst.h (enum score_insn_type): Add Insn_internal.
571 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
572 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
573 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
574 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
575 Alan Modra <amodra@bigpond.net.au>
577 * spu-insns.h: New file.
580 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
582 * ppc.h (PPC_OPCODE_CELL): Define.
584 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
586 * i386.h : Modify opcode to support for the change in POPCNT opcode
587 in amdfam10 architecture.
589 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
591 * i386.h: Replace CpuMNI with CpuSSSE3.
593 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
594 Joseph Myers <joseph@codesourcery.com>
595 Ian Lance Taylor <ian@wasabisystems.com>
596 Ben Elliston <bje@wasabisystems.com>
598 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
600 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
602 * score-datadep.h: New file.
603 * score-inst.h: New file.
605 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
607 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
608 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
611 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
612 Michael Meissner <michael.meissner@amd.com>
614 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
616 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
618 * i386.h (i386_optab): Add "nop" with memory reference.
620 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
622 * i386.h (i386_optab): Update comment for 64bit NOP.
624 2006-06-06 Ben Elliston <bje@au.ibm.com>
625 Anton Blanchard <anton@samba.org>
627 * ppc.h (PPC_OPCODE_POWER6): Define.
630 2006-06-05 Thiemo Seufer <ths@mips.com>
632 * mips.h: Improve description of MT flags.
634 2006-05-25 Richard Sandiford <richard@codesourcery.com>
636 * m68k.h (mcf_mask): Define.
638 2006-05-05 Thiemo Seufer <ths@mips.com>
639 David Ung <davidu@mips.com>
641 * mips.h (enum): Add macro M_CACHE_AB.
643 2006-05-04 Thiemo Seufer <ths@mips.com>
644 Nigel Stephens <nigel@mips.com>
645 David Ung <davidu@mips.com>
647 * mips.h: Add INSN_SMARTMIPS define.
649 2006-04-30 Thiemo Seufer <ths@mips.com>
650 David Ung <davidu@mips.com>
652 * mips.h: Defines udi bits and masks. Add description of
653 characters which may appear in the args field of udi
656 2006-04-26 Thiemo Seufer <ths@networkno.de>
658 * mips.h: Improve comments describing the bitfield instruction
661 2006-04-26 Julian Brown <julian@codesourcery.com>
663 * arm.h (FPU_VFP_EXT_V3): Define constant.
664 (FPU_NEON_EXT_V1): Likewise.
665 (FPU_VFP_HARD): Update.
666 (FPU_VFP_V3): Define macro.
667 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
669 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
671 * avr.h (AVR_ISA_PWMx): New.
673 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
675 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
676 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
677 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
678 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
679 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
681 2006-03-10 Paul Brook <paul@codesourcery.com>
683 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
685 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
687 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
688 first. Correct mask of bb "B" opcode.
690 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
692 * i386.h (i386_optab): Support Intel Merom New Instructions.
694 2006-02-24 Paul Brook <paul@codesourcery.com>
696 * arm.h: Add V7 feature bits.
698 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
700 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
702 2006-01-31 Paul Brook <paul@codesourcery.com>
703 Richard Earnshaw <rearnsha@arm.com>
705 * arm.h: Use ARM_CPU_FEATURE.
706 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
707 (arm_feature_set): Change to a structure.
708 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
709 ARM_FEATURE): New macros.
711 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
713 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
714 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
715 (ADD_PC_INCR_OPCODE): Don't define.
717 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
720 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
722 2005-11-14 David Ung <davidu@mips.com>
724 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
725 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
726 save/restore encoding of the args field.
728 2005-10-28 Dave Brolley <brolley@redhat.com>
730 Contribute the following changes:
731 2005-02-16 Dave Brolley <brolley@redhat.com>
733 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
734 cgen_isa_mask_* to cgen_bitset_*.
737 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
739 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
740 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
741 (CGEN_CPU_TABLE): Make isas a ponter.
743 2003-09-29 Dave Brolley <brolley@redhat.com>
745 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
746 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
747 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
749 2002-12-13 Dave Brolley <brolley@redhat.com>
751 * cgen.h (symcat.h): #include it.
752 (cgen-bitset.h): #include it.
753 (CGEN_ATTR_VALUE_TYPE): Now a union.
754 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
755 (CGEN_ATTR_ENTRY): 'value' now unsigned.
756 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
757 * cgen-bitset.h: New file.
759 2005-09-30 Catherine Moore <clm@cm00re.com>
763 2005-10-24 Jan Beulich <jbeulich@novell.com>
765 * ia64.h (enum ia64_opnd): Move memory operand out of set of
768 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
770 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
771 Add FLAG_STRICT to pa10 ftest opcode.
773 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
775 * hppa.h (pa_opcodes): Remove lha entries.
777 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
779 * hppa.h (FLAG_STRICT): Revise comment.
780 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
781 before corresponding pa11 opcodes. Add strict pa10 register-immediate
784 2005-09-30 Catherine Moore <clm@cm00re.com>
788 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
790 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
792 2005-09-06 Chao-ying Fu <fu@mips.com>
794 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
795 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
797 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
798 (INSN_ASE_MASK): Update to include INSN_MT.
799 (INSN_MT): New define for MT ASE.
801 2005-08-25 Chao-ying Fu <fu@mips.com>
803 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
804 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
805 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
806 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
807 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
808 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
810 (INSN_DSP): New define for DSP ASE.
812 2005-08-18 Alan Modra <amodra@bigpond.net.au>
816 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
818 * ppc.h (PPC_OPCODE_E300): Define.
820 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
822 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
824 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
827 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
830 2005-07-27 Jan Beulich <jbeulich@novell.com>
832 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
833 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
834 Add movq-s as 64-bit variants of movd-s.
836 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
838 * hppa.h: Fix punctuation in comment.
840 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
841 implicit space-register addressing. Set space-register bits on opcodes
842 using implicit space-register addressing. Add various missing pa20
843 long-immediate opcodes. Remove various opcodes using implicit 3-bit
844 space-register addressing. Use "fE" instead of "fe" in various
847 2005-07-18 Jan Beulich <jbeulich@novell.com>
849 * i386.h (i386_optab): Operands of aam and aad are unsigned.
851 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
853 * i386.h (i386_optab): Support Intel VMX Instructions.
855 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
857 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
859 2005-07-05 Jan Beulich <jbeulich@novell.com>
861 * i386.h (i386_optab): Add new insns.
863 2005-07-01 Nick Clifton <nickc@redhat.com>
865 * sparc.h: Add typedefs to structure declarations.
867 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
870 * i386.h (i386_optab): Update comments for 64bit addressing on
871 mov. Allow 64bit addressing for mov and movq.
873 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
875 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
876 respectively, in various floating-point load and store patterns.
878 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
880 * hppa.h (FLAG_STRICT): Correct comment.
881 (pa_opcodes): Update load and store entries to allow both PA 1.X and
882 PA 2.0 mneumonics when equivalent. Entries with cache control
883 completers now require PA 1.1. Adjust whitespace.
885 2005-05-19 Anton Blanchard <anton@samba.org>
887 * ppc.h (PPC_OPCODE_POWER5): Define.
889 2005-05-10 Nick Clifton <nickc@redhat.com>
891 * Update the address and phone number of the FSF organization in
892 the GPL notices in the following files:
893 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
894 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
895 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
896 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
897 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
898 tic54x.h, tic80.h, v850.h, vax.h
900 2005-05-09 Jan Beulich <jbeulich@novell.com>
902 * i386.h (i386_optab): Add ht and hnt.
904 2005-04-18 Mark Kettenis <kettenis@gnu.org>
906 * i386.h: Insert hyphens into selected VIA PadLock extensions.
907 Add xcrypt-ctr. Provide aliases without hyphens.
909 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
911 Moved from ../ChangeLog
913 2005-04-12 Paul Brook <paul@codesourcery.com>
914 * m88k.h: Rename psr macros to avoid conflicts.
916 2005-03-12 Zack Weinberg <zack@codesourcery.com>
917 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
918 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
921 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
922 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
923 Remove redundant instruction types.
924 (struct argument): X_op - new field.
925 (struct cst4_entry): Remove.
926 (no_op_insn): Declare.
928 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
929 * crx.h (enum argtype): Rename types, remove unused types.
931 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
932 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
933 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
934 (enum operand_type): Rearrange operands, edit comments.
935 replace us<N> with ui<N> for unsigned immediate.
936 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
937 displacements (respectively).
938 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
939 (instruction type): Add NO_TYPE_INS.
940 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
941 (operand_entry): New field - 'flags'.
942 (operand flags): New.
944 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
945 * crx.h (operand_type): Remove redundant types i3, i4,
947 Add new unsigned immediate types us3, us4, us5, us16.
949 2005-04-12 Mark Kettenis <kettenis@gnu.org>
951 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
952 adjust them accordingly.
954 2005-04-01 Jan Beulich <jbeulich@novell.com>
956 * i386.h (i386_optab): Add rdtscp.
958 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
960 * i386.h (i386_optab): Don't allow the `l' suffix for moving
961 between memory and segment register. Allow movq for moving between
962 general-purpose register and segment register.
964 2005-02-09 Jan Beulich <jbeulich@novell.com>
967 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
968 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
971 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
973 * m68k.h (m68008, m68ec030, m68882): Remove.
975 (cpu_m68k, cpu_cf): New.
976 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
977 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
979 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
981 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
982 * cgen.h (enum cgen_parse_operand_type): Add
983 CGEN_PARSE_OPERAND_SYMBOLIC.
985 2005-01-21 Fred Fish <fnf@specifixinc.com>
987 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
988 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
989 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
991 2005-01-19 Fred Fish <fnf@specifixinc.com>
993 * mips.h (struct mips_opcode): Add new pinfo2 member.
994 (INSN_ALIAS): New define for opcode table entries that are
995 specific instances of another entry, such as 'move' for an 'or'
997 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
998 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1000 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1002 * mips.h (CPU_RM9000): Define.
1003 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1005 2004-11-25 Jan Beulich <jbeulich@novell.com>
1007 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1008 to/from test registers are illegal in 64-bit mode. Add missing
1009 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1010 (previously one had to explicitly encode a rex64 prefix). Re-enable
1011 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1012 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1014 2004-11-23 Jan Beulich <jbeulich@novell.com>
1016 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1017 available only with SSE2. Change the MMX additions introduced by SSE
1018 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1019 instructions by their now designated identifier (since combining i686
1020 and 3DNow! does not really imply 3DNow!A).
1022 2004-11-19 Alan Modra <amodra@bigpond.net.au>
1024 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1025 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1027 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1028 Vineet Sharma <vineets@noida.hcltech.com>
1030 * maxq.h: New file: Disassembly information for the maxq port.
1032 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1034 * i386.h (i386_optab): Put back "movzb".
1036 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
1038 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1039 comments. Remove member cris_ver_sim. Add members
1040 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1041 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1042 (struct cris_support_reg, struct cris_cond15): New types.
1043 (cris_conds15): Declare.
1044 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1045 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1046 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1047 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1048 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1049 SIZE_FIELD_UNSIGNED.
1051 2004-11-04 Jan Beulich <jbeulich@novell.com>
1053 * i386.h (sldx_Suf): Remove.
1054 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1055 (q_FP): Define, implying no REX64.
1056 (x_FP, sl_FP): Imply FloatMF.
1057 (i386_optab): Split reg and mem forms of moving from segment registers
1058 so that the memory forms can ignore the 16-/32-bit operand size
1059 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1060 all non-floating-point instructions. Unite 32- and 64-bit forms of
1061 movsx, movzx, and movd. Adjust floating point operations for the above
1062 changes to the *FP macros. Add DefaultSize to floating point control
1063 insns operating on larger memory ranges. Remove left over comments
1064 hinting at certain insns being Intel-syntax ones where the ones
1065 actually meant are already gone.
1067 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1069 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1072 2004-09-30 Paul Brook <paul@codesourcery.com>
1074 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1075 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1077 2004-09-11 Theodore A. Roth <troth@openavr.org>
1079 * avr.h: Add support for
1080 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1082 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1084 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1086 2004-08-24 Dmitry Diky <diwil@spec.ru>
1088 * msp430.h (msp430_opc): Add new instructions.
1089 (msp430_rcodes): Declare new instructions.
1090 (msp430_hcodes): Likewise..
1092 2004-08-13 Nick Clifton <nickc@redhat.com>
1095 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1098 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1100 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1102 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1104 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1106 2004-07-21 Jan Beulich <jbeulich@novell.com>
1108 * i386.h: Adjust instruction descriptions to better match the
1111 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
1113 * arm.h: Remove all old content. Replace with architecture defines
1114 from gas/config/tc-arm.c.
1116 2004-07-09 Andreas Schwab <schwab@suse.de>
1118 * m68k.h: Fix comment.
1120 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1124 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1126 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1128 2004-05-24 Peter Barada <peter@the-baradas.com>
1130 * m68k.h: Add 'size' to m68k_opcode.
1132 2004-05-05 Peter Barada <peter@the-baradas.com>
1134 * m68k.h: Switch from ColdFire chip name to core variant.
1136 2004-04-22 Peter Barada <peter@the-baradas.com>
1138 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1139 descriptions for new EMAC cases.
1140 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1141 handle Motorola MAC syntax.
1142 Allow disassembly of ColdFire V4e object files.
1144 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1146 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1148 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1150 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1152 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1154 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1156 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1158 * i386.h (i386_optab): Added xstore/xcrypt insns.
1160 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1162 * h8300.h (32bit ldc/stc): Add relaxing support.
1164 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1166 * h8300.h (BITOP): Pass MEMRELAX flag.
1168 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1170 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1173 For older changes see ChangeLog-9103
1179 version-control: never