1 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
3 * mips.h: Clarify the description of microMIPS instruction
5 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
7 2011-07-24 Chao-ying Fu <fu@mips.com>
8 Maciej W. Rozycki <macro@codesourcery.com>
10 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
11 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
12 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
13 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
14 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
15 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
16 (OP_MASK_RS3, OP_SH_RS3): Likewise.
17 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
18 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
19 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
20 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
21 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
22 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
23 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
24 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
25 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
26 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
27 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
28 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
29 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
30 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
31 (INSN_WRITE_GPR_S): New macro.
32 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
33 (INSN2_READ_FPR_D): Likewise.
34 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
35 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
36 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
37 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
38 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
39 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
40 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
41 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
42 (CPU_MICROMIPS): New macro.
43 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
44 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
45 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
46 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
47 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
48 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
49 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
50 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
51 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
52 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
53 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
54 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
55 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
56 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
57 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
58 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
59 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
60 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
61 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
62 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
63 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
64 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
65 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
66 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
67 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
68 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
69 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
70 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
71 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
72 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
73 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
74 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
75 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
76 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
77 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
78 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
79 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
80 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
81 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
82 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
83 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
84 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
85 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
86 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
87 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
88 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
89 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
90 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
91 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
92 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
93 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
94 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
95 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
96 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
97 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
98 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
99 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
100 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
101 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
102 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
103 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
104 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
105 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
106 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
107 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
108 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
109 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
110 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
111 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
112 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
113 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
114 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
115 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
116 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
117 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
118 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
119 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
120 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
121 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
122 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
123 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
124 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
125 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
126 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
127 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
128 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
129 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
130 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
131 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
132 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
133 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
134 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
135 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
136 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
137 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
138 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
139 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
140 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
141 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
142 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
143 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
144 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
145 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
146 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
147 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
148 (micromips_opcodes): New declaration.
149 (bfd_micromips_num_opcodes): Likewise.
151 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
153 * mips.h (INSN_TRAP): Rename to...
154 (INSN_NO_DELAY_SLOT): ... this.
155 (INSN_SYNC): Remove macro.
157 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
159 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
160 a duplicate of AVR_ISA_SPM.
162 2011-07-01 Nick Clifton <nickc@redhat.com>
164 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
166 2011-06-18 Robin Getz <robin.getz@analog.com>
168 * bfin.h (is_macmod_signed): New func
170 2011-06-18 Mike Frysinger <vapier@gentoo.org>
172 * bfin.h (is_macmod_pmove): Add missing space before func args.
173 (is_macmod_hmove): Likewise.
175 2011-06-13 Walter Lee <walt@tilera.com>
177 * tilegx.h: New file.
178 * tilepro.h: New file.
180 2011-05-31 Paul Brook <paul@codesourcery.com>
182 * arm.h (ARM_ARCH_V7R_IDIV): Define.
184 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
186 * s390.h: Replace S390_OPERAND_REG_EVEN with
187 S390_OPERAND_REG_PAIR.
189 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
191 * s390.h: Add S390_OPCODE_REG_EVEN flag.
193 2011-04-18 Julian Brown <julian@codesourcery.com>
195 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
197 2011-04-11 Dan McDonald <dan@wellkeeper.com>
200 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
202 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
204 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
205 New instruction set flags.
206 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
208 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
210 * mips.h (M_PREF_AB): New enum value.
212 2011-02-12 Mike Frysinger <vapier@gentoo.org>
214 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
216 (is_macmod_pmove, is_macmod_hmove): New functions.
218 2011-02-11 Mike Frysinger <vapier@gentoo.org>
220 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
222 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
224 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
225 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
227 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
230 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
233 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
236 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
238 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
240 * mips.h: Update commentary after last commit.
242 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
244 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
245 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
246 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
248 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
250 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
252 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
254 * mips.h: Fix previous commit.
256 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
258 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
259 (INSN_LOONGSON_3A): Clear bit 31.
261 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
264 * arm.h (ARM_AEXT_V6M_ONLY): New define.
265 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
266 (ARM_ARCH_V6M_ONLY): New define.
268 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
270 * mips.h (INSN_LOONGSON_3A): Defined.
271 (CPU_LOONGSON_3A): Defined.
272 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
274 2010-10-09 Matt Rice <ratmice@gmail.com>
276 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
277 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
279 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
281 * arm.h (ARM_EXT_VIRT): New define.
282 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
283 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
286 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
288 * arm.h (ARM_AEXT_ADIV): New define.
289 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
291 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
293 * arm.h (ARM_EXT_OS): New define.
294 (ARM_AEXT_V6SM): Likewise.
295 (ARM_ARCH_V6SM): Likewise.
297 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
299 * arm.h (ARM_EXT_MP): Add.
300 (ARM_ARCH_V7A_MP): Likewise.
302 2010-09-22 Mike Frysinger <vapier@gentoo.org>
304 * bfin.h: Declare pseudoChr structs/defines.
306 2010-09-21 Mike Frysinger <vapier@gentoo.org>
308 * bfin.h: Strip trailing whitespace.
310 2010-07-29 DJ Delorie <dj@redhat.com>
312 * rx.h (RX_Operand_Type): Add TwoReg.
313 (RX_Opcode_ID): Remove ediv and ediv2.
315 2010-07-27 DJ Delorie <dj@redhat.com>
317 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
319 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
320 Ina Pandit <ina.pandit@kpitcummins.com>
322 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
323 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
324 PROCESSOR_V850E2_ALL.
325 Remove PROCESSOR_V850EA support.
326 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
327 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
328 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
329 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
330 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
331 V850_OPERAND_PERCENT.
332 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
334 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
337 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
339 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
340 (MIPS16_INSN_BRANCH): Rename to...
341 (MIPS16_INSN_COND_BRANCH): ... this.
343 2010-07-03 Alan Modra <amodra@gmail.com>
345 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
346 Renumber other PPC_OPCODE defines.
348 2010-07-03 Alan Modra <amodra@gmail.com>
350 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
352 2010-06-29 Alan Modra <amodra@gmail.com>
354 * maxq.h: Delete file.
356 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
358 * ppc.h (PPC_OPCODE_E500): Define.
360 2010-05-26 Catherine Moore <clm@codesourcery.com>
362 * opcode/mips.h (INSN_MIPS16): Remove.
364 2010-04-21 Joseph Myers <joseph@codesourcery.com>
366 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
368 2010-04-15 Nick Clifton <nickc@redhat.com>
370 * alpha.h: Update copyright notice to use GPLv3.
376 * convex.h: Likewise.
390 * m68hc11.h: Likewise.
396 * mn10200.h: Likewise.
397 * mn10300.h: Likewise.
398 * msp430.h: Likewise.
409 * score-datadep.h: Likewise.
410 * score-inst.h: Likewise.
412 * spu-insns.h: Likewise.
416 * tic54x.h: Likewise.
421 2010-03-25 Joseph Myers <joseph@codesourcery.com>
423 * tic6x-control-registers.h, tic6x-insn-formats.h,
424 tic6x-opcode-table.h, tic6x.h: New.
426 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
428 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
430 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
432 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
434 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
436 * ia64.h (ia64_find_opcode): Remove argument name.
437 (ia64_find_next_opcode): Likewise.
438 (ia64_dis_opcode): Likewise.
439 (ia64_free_opcode): Likewise.
440 (ia64_find_dependency): Likewise.
442 2009-11-22 Doug Evans <dje@sebabeach.org>
444 * cgen.h: Include bfd_stdint.h.
445 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
447 2009-11-18 Paul Brook <paul@codesourcery.com>
449 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
451 2009-11-17 Paul Brook <paul@codesourcery.com>
452 Daniel Jacobowitz <dan@codesourcery.com>
454 * arm.h (ARM_EXT_V6_DSP): Define.
455 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
456 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
458 2009-11-04 DJ Delorie <dj@redhat.com>
460 * rx.h (rx_decode_opcode) (mvtipl): Add.
461 (mvtcp, mvfcp, opecp): Remove.
463 2009-11-02 Paul Brook <paul@codesourcery.com>
465 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
466 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
467 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
468 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
469 FPU_ARCH_NEON_VFP_V4): Define.
471 2009-10-23 Doug Evans <dje@sebabeach.org>
473 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
474 * cgen.h: Update. Improve multi-inclusion macro name.
476 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
478 * ppc.h (PPC_OPCODE_476): Define.
480 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
482 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
484 2009-09-29 DJ Delorie <dj@redhat.com>
488 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
490 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
492 2009-09-21 Ben Elliston <bje@au.ibm.com>
494 * ppc.h (PPC_OPCODE_PPCA2): New.
496 2009-09-05 Martin Thuresson <martin@mtme.org>
498 * ia64.h (struct ia64_operand): Renamed member class to op_class.
500 2009-08-29 Martin Thuresson <martin@mtme.org>
502 * tic30.h (template): Rename type template to
503 insn_template. Updated code to use new name.
504 * tic54x.h (template): Rename type template to
507 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
509 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
511 2009-06-11 Anthony Green <green@moxielogic.com>
513 * moxie.h (MOXIE_F3_PCREL): Define.
514 (moxie_form3_opc_info): Grow.
516 2009-06-06 Anthony Green <green@moxielogic.com>
518 * moxie.h (MOXIE_F1_M): Define.
520 2009-04-15 Anthony Green <green@moxielogic.com>
524 2009-04-06 DJ Delorie <dj@redhat.com>
526 * h8300.h: Add relaxation attributes to MOVA opcodes.
528 2009-03-10 Alan Modra <amodra@bigpond.net.au>
530 * ppc.h (ppc_parse_cpu): Declare.
532 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
534 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
535 and _IMM11 for mbitclr and mbitset.
536 * score-datadep.h: Update dependency information.
538 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
540 * ppc.h (PPC_OPCODE_POWER7): New.
542 2009-02-06 Doug Evans <dje@google.com>
544 * i386.h: Add comment regarding sse* insns and prefixes.
546 2009-02-03 Sandip Matte <sandip@rmicorp.com>
548 * mips.h (INSN_XLR): Define.
549 (INSN_CHIP_MASK): Update.
551 (OPCODE_IS_MEMBER): Update.
552 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
554 2009-01-28 Doug Evans <dje@google.com>
556 * opcode/i386.h: Add multiple inclusion protection.
557 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
558 (EDI_REG_NUM): New macros.
559 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
560 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
561 (REX_PREFIX_P): New macro.
563 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
565 * ppc.h (struct powerpc_opcode): New field "deprecated".
566 (PPC_OPCODE_NOPOWER4): Delete.
568 2008-11-28 Joshua Kinard <kumba@gentoo.org>
570 * mips.h: Define CPU_R14000, CPU_R16000.
571 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
573 2008-11-18 Catherine Moore <clm@codesourcery.com>
575 * arm.h (FPU_NEON_FP16): New.
576 (FPU_ARCH_NEON_FP16): New.
578 2008-11-06 Chao-ying Fu <fu@mips.com>
580 * mips.h: Doucument '1' for 5-bit sync type.
582 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
584 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
587 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
589 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
591 2008-07-30 Michael J. Eager <eager@eagercon.com>
593 * ppc.h (PPC_OPCODE_405): Define.
594 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
596 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
598 * ppc.h (ppc_cpu_t): New typedef.
599 (struct powerpc_opcode <flags>): Use it.
600 (struct powerpc_operand <insert, extract>): Likewise.
601 (struct powerpc_macro <flags>): Likewise.
603 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
605 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
606 Update comment before MIPS16 field descriptors to mention MIPS16.
607 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
609 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
610 New bit masks and shift counts for cins and exts.
612 * mips.h: Document new field descriptors +Q.
613 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
615 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
617 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
618 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
620 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
622 * ppc.h: (PPC_OPCODE_E500MC): New.
624 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
626 * i386.h (MAX_OPERANDS): Set to 5.
627 (MAX_MNEM_SIZE): Changed to 20.
629 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
631 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
633 2008-03-09 Paul Brook <paul@codesourcery.com>
635 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
637 2008-03-04 Paul Brook <paul@codesourcery.com>
639 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
640 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
641 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
643 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
644 Nick Clifton <nickc@redhat.com>
647 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
648 with a 32-bit displacement but without the top bit of the 4th byte
651 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
653 * cr16.h (cr16_num_optab): Declared.
655 2008-02-14 Hakan Ardo <hakan@debian.org>
658 * avr.h (AVR_ISA_2xxe): Define.
660 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
662 * mips.h: Update copyright.
663 (INSN_CHIP_MASK): New macro.
664 (INSN_OCTEON): New macro.
665 (CPU_OCTEON): New macro.
666 (OPCODE_IS_MEMBER): Handle Octeon instructions.
668 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
670 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
672 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
674 * avr.h (AVR_ISA_USB162): Add new opcode set.
675 (AVR_ISA_AVR3): Likewise.
677 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
679 * mips.h (INSN_LOONGSON_2E): New.
680 (INSN_LOONGSON_2F): New.
681 (CPU_LOONGSON_2E): New.
682 (CPU_LOONGSON_2F): New.
683 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
685 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
687 * mips.h (INSN_ISA*): Redefine certain values as an
688 enumeration. Update comments.
689 (mips_isa_table): New.
690 (ISA_MIPS*): Redefine to match enumeration.
691 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
694 2007-08-08 Ben Elliston <bje@au.ibm.com>
696 * ppc.h (PPC_OPCODE_PPCPS): New.
698 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
700 * m68k.h: Document j K & E.
702 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
704 * cr16.h: New file for CR16 target.
706 2007-05-02 Alan Modra <amodra@bigpond.net.au>
708 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
710 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
712 * m68k.h (mcfisa_c): New.
713 (mcfusp, mcf_mask): Adjust.
715 2007-04-20 Alan Modra <amodra@bigpond.net.au>
717 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
718 (num_powerpc_operands): Declare.
719 (PPC_OPERAND_SIGNED et al): Redefine as hex.
720 (PPC_OPERAND_PLUS1): Define.
722 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
724 * i386.h (REX_MODE64): Renamed to ...
726 (REX_EXTX): Renamed to ...
728 (REX_EXTY): Renamed to ...
730 (REX_EXTZ): Renamed to ...
733 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
735 * i386.h: Add entries from config/tc-i386.h and move tables
736 to opcodes/i386-opc.h.
738 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
740 * i386.h (FloatDR): Removed.
741 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
743 2007-03-01 Alan Modra <amodra@bigpond.net.au>
745 * spu-insns.h: Add soma double-float insns.
747 2007-02-20 Thiemo Seufer <ths@mips.com>
748 Chao-Ying Fu <fu@mips.com>
750 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
751 (INSN_DSPR2): Add flag for DSP R2 instructions.
752 (M_BALIGN): New macro.
754 2007-02-14 Alan Modra <amodra@bigpond.net.au>
756 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
757 and Seg3ShortFrom with Shortform.
759 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
762 * i386.h (i386_optab): Put the real "test" before the pseudo
765 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
767 * m68k.h (m68010up): OR fido_a.
769 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
771 * m68k.h (fido_a): New.
773 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
775 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
776 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
779 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
781 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
783 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
785 * score-inst.h (enum score_insn_type): Add Insn_internal.
787 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
788 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
789 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
790 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
791 Alan Modra <amodra@bigpond.net.au>
793 * spu-insns.h: New file.
796 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
798 * ppc.h (PPC_OPCODE_CELL): Define.
800 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
802 * i386.h : Modify opcode to support for the change in POPCNT opcode
803 in amdfam10 architecture.
805 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
807 * i386.h: Replace CpuMNI with CpuSSSE3.
809 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
810 Joseph Myers <joseph@codesourcery.com>
811 Ian Lance Taylor <ian@wasabisystems.com>
812 Ben Elliston <bje@wasabisystems.com>
814 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
816 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
818 * score-datadep.h: New file.
819 * score-inst.h: New file.
821 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
823 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
824 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
827 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
828 Michael Meissner <michael.meissner@amd.com>
830 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
832 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
834 * i386.h (i386_optab): Add "nop" with memory reference.
836 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
838 * i386.h (i386_optab): Update comment for 64bit NOP.
840 2006-06-06 Ben Elliston <bje@au.ibm.com>
841 Anton Blanchard <anton@samba.org>
843 * ppc.h (PPC_OPCODE_POWER6): Define.
846 2006-06-05 Thiemo Seufer <ths@mips.com>
848 * mips.h: Improve description of MT flags.
850 2006-05-25 Richard Sandiford <richard@codesourcery.com>
852 * m68k.h (mcf_mask): Define.
854 2006-05-05 Thiemo Seufer <ths@mips.com>
855 David Ung <davidu@mips.com>
857 * mips.h (enum): Add macro M_CACHE_AB.
859 2006-05-04 Thiemo Seufer <ths@mips.com>
860 Nigel Stephens <nigel@mips.com>
861 David Ung <davidu@mips.com>
863 * mips.h: Add INSN_SMARTMIPS define.
865 2006-04-30 Thiemo Seufer <ths@mips.com>
866 David Ung <davidu@mips.com>
868 * mips.h: Defines udi bits and masks. Add description of
869 characters which may appear in the args field of udi
872 2006-04-26 Thiemo Seufer <ths@networkno.de>
874 * mips.h: Improve comments describing the bitfield instruction
877 2006-04-26 Julian Brown <julian@codesourcery.com>
879 * arm.h (FPU_VFP_EXT_V3): Define constant.
880 (FPU_NEON_EXT_V1): Likewise.
881 (FPU_VFP_HARD): Update.
882 (FPU_VFP_V3): Define macro.
883 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
885 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
887 * avr.h (AVR_ISA_PWMx): New.
889 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
891 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
892 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
893 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
894 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
895 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
897 2006-03-10 Paul Brook <paul@codesourcery.com>
899 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
901 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
903 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
904 first. Correct mask of bb "B" opcode.
906 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
908 * i386.h (i386_optab): Support Intel Merom New Instructions.
910 2006-02-24 Paul Brook <paul@codesourcery.com>
912 * arm.h: Add V7 feature bits.
914 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
916 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
918 2006-01-31 Paul Brook <paul@codesourcery.com>
919 Richard Earnshaw <rearnsha@arm.com>
921 * arm.h: Use ARM_CPU_FEATURE.
922 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
923 (arm_feature_set): Change to a structure.
924 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
925 ARM_FEATURE): New macros.
927 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
929 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
930 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
931 (ADD_PC_INCR_OPCODE): Don't define.
933 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
936 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
938 2005-11-14 David Ung <davidu@mips.com>
940 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
941 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
942 save/restore encoding of the args field.
944 2005-10-28 Dave Brolley <brolley@redhat.com>
946 Contribute the following changes:
947 2005-02-16 Dave Brolley <brolley@redhat.com>
949 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
950 cgen_isa_mask_* to cgen_bitset_*.
953 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
955 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
956 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
957 (CGEN_CPU_TABLE): Make isas a ponter.
959 2003-09-29 Dave Brolley <brolley@redhat.com>
961 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
962 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
963 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
965 2002-12-13 Dave Brolley <brolley@redhat.com>
967 * cgen.h (symcat.h): #include it.
968 (cgen-bitset.h): #include it.
969 (CGEN_ATTR_VALUE_TYPE): Now a union.
970 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
971 (CGEN_ATTR_ENTRY): 'value' now unsigned.
972 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
973 * cgen-bitset.h: New file.
975 2005-09-30 Catherine Moore <clm@cm00re.com>
979 2005-10-24 Jan Beulich <jbeulich@novell.com>
981 * ia64.h (enum ia64_opnd): Move memory operand out of set of
984 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
986 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
987 Add FLAG_STRICT to pa10 ftest opcode.
989 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
991 * hppa.h (pa_opcodes): Remove lha entries.
993 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
995 * hppa.h (FLAG_STRICT): Revise comment.
996 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
997 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1000 2005-09-30 Catherine Moore <clm@cm00re.com>
1004 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1006 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1008 2005-09-06 Chao-ying Fu <fu@mips.com>
1010 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1011 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1013 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1014 (INSN_ASE_MASK): Update to include INSN_MT.
1015 (INSN_MT): New define for MT ASE.
1017 2005-08-25 Chao-ying Fu <fu@mips.com>
1019 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1020 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1021 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1022 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1023 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1024 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1026 (INSN_DSP): New define for DSP ASE.
1028 2005-08-18 Alan Modra <amodra@bigpond.net.au>
1032 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1034 * ppc.h (PPC_OPCODE_E300): Define.
1036 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1038 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1040 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1043 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1046 2005-07-27 Jan Beulich <jbeulich@novell.com>
1048 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1049 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1050 Add movq-s as 64-bit variants of movd-s.
1052 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1054 * hppa.h: Fix punctuation in comment.
1056 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1057 implicit space-register addressing. Set space-register bits on opcodes
1058 using implicit space-register addressing. Add various missing pa20
1059 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1060 space-register addressing. Use "fE" instead of "fe" in various
1063 2005-07-18 Jan Beulich <jbeulich@novell.com>
1065 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1067 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1069 * i386.h (i386_optab): Support Intel VMX Instructions.
1071 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1073 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1075 2005-07-05 Jan Beulich <jbeulich@novell.com>
1077 * i386.h (i386_optab): Add new insns.
1079 2005-07-01 Nick Clifton <nickc@redhat.com>
1081 * sparc.h: Add typedefs to structure declarations.
1083 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1086 * i386.h (i386_optab): Update comments for 64bit addressing on
1087 mov. Allow 64bit addressing for mov and movq.
1089 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1091 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1092 respectively, in various floating-point load and store patterns.
1094 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1096 * hppa.h (FLAG_STRICT): Correct comment.
1097 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1098 PA 2.0 mneumonics when equivalent. Entries with cache control
1099 completers now require PA 1.1. Adjust whitespace.
1101 2005-05-19 Anton Blanchard <anton@samba.org>
1103 * ppc.h (PPC_OPCODE_POWER5): Define.
1105 2005-05-10 Nick Clifton <nickc@redhat.com>
1107 * Update the address and phone number of the FSF organization in
1108 the GPL notices in the following files:
1109 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1110 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1111 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1112 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1113 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1114 tic54x.h, tic80.h, v850.h, vax.h
1116 2005-05-09 Jan Beulich <jbeulich@novell.com>
1118 * i386.h (i386_optab): Add ht and hnt.
1120 2005-04-18 Mark Kettenis <kettenis@gnu.org>
1122 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1123 Add xcrypt-ctr. Provide aliases without hyphens.
1125 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1127 Moved from ../ChangeLog
1129 2005-04-12 Paul Brook <paul@codesourcery.com>
1130 * m88k.h: Rename psr macros to avoid conflicts.
1132 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1133 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1134 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1135 and ARM_ARCH_V6ZKT2.
1137 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1138 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1139 Remove redundant instruction types.
1140 (struct argument): X_op - new field.
1141 (struct cst4_entry): Remove.
1142 (no_op_insn): Declare.
1144 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1145 * crx.h (enum argtype): Rename types, remove unused types.
1147 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1148 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1149 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1150 (enum operand_type): Rearrange operands, edit comments.
1151 replace us<N> with ui<N> for unsigned immediate.
1152 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1153 displacements (respectively).
1154 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1155 (instruction type): Add NO_TYPE_INS.
1156 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1157 (operand_entry): New field - 'flags'.
1158 (operand flags): New.
1160 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1161 * crx.h (operand_type): Remove redundant types i3, i4,
1163 Add new unsigned immediate types us3, us4, us5, us16.
1165 2005-04-12 Mark Kettenis <kettenis@gnu.org>
1167 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1168 adjust them accordingly.
1170 2005-04-01 Jan Beulich <jbeulich@novell.com>
1172 * i386.h (i386_optab): Add rdtscp.
1174 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1176 * i386.h (i386_optab): Don't allow the `l' suffix for moving
1177 between memory and segment register. Allow movq for moving between
1178 general-purpose register and segment register.
1180 2005-02-09 Jan Beulich <jbeulich@novell.com>
1183 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1184 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1187 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1189 * m68k.h (m68008, m68ec030, m68882): Remove.
1191 (cpu_m68k, cpu_cf): New.
1192 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1193 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1195 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
1197 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1198 * cgen.h (enum cgen_parse_operand_type): Add
1199 CGEN_PARSE_OPERAND_SYMBOLIC.
1201 2005-01-21 Fred Fish <fnf@specifixinc.com>
1203 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1204 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1205 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1207 2005-01-19 Fred Fish <fnf@specifixinc.com>
1209 * mips.h (struct mips_opcode): Add new pinfo2 member.
1210 (INSN_ALIAS): New define for opcode table entries that are
1211 specific instances of another entry, such as 'move' for an 'or'
1212 with a zero operand.
1213 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1214 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1216 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1218 * mips.h (CPU_RM9000): Define.
1219 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1221 2004-11-25 Jan Beulich <jbeulich@novell.com>
1223 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1224 to/from test registers are illegal in 64-bit mode. Add missing
1225 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1226 (previously one had to explicitly encode a rex64 prefix). Re-enable
1227 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1228 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1230 2004-11-23 Jan Beulich <jbeulich@novell.com>
1232 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1233 available only with SSE2. Change the MMX additions introduced by SSE
1234 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1235 instructions by their now designated identifier (since combining i686
1236 and 3DNow! does not really imply 3DNow!A).
1238 2004-11-19 Alan Modra <amodra@bigpond.net.au>
1240 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1241 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1243 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1244 Vineet Sharma <vineets@noida.hcltech.com>
1246 * maxq.h: New file: Disassembly information for the maxq port.
1248 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1250 * i386.h (i386_optab): Put back "movzb".
1252 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
1254 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1255 comments. Remove member cris_ver_sim. Add members
1256 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1257 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1258 (struct cris_support_reg, struct cris_cond15): New types.
1259 (cris_conds15): Declare.
1260 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1261 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1262 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1263 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1264 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1265 SIZE_FIELD_UNSIGNED.
1267 2004-11-04 Jan Beulich <jbeulich@novell.com>
1269 * i386.h (sldx_Suf): Remove.
1270 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1271 (q_FP): Define, implying no REX64.
1272 (x_FP, sl_FP): Imply FloatMF.
1273 (i386_optab): Split reg and mem forms of moving from segment registers
1274 so that the memory forms can ignore the 16-/32-bit operand size
1275 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1276 all non-floating-point instructions. Unite 32- and 64-bit forms of
1277 movsx, movzx, and movd. Adjust floating point operations for the above
1278 changes to the *FP macros. Add DefaultSize to floating point control
1279 insns operating on larger memory ranges. Remove left over comments
1280 hinting at certain insns being Intel-syntax ones where the ones
1281 actually meant are already gone.
1283 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1285 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1288 2004-09-30 Paul Brook <paul@codesourcery.com>
1290 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1291 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1293 2004-09-11 Theodore A. Roth <troth@openavr.org>
1295 * avr.h: Add support for
1296 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1298 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1300 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1302 2004-08-24 Dmitry Diky <diwil@spec.ru>
1304 * msp430.h (msp430_opc): Add new instructions.
1305 (msp430_rcodes): Declare new instructions.
1306 (msp430_hcodes): Likewise..
1308 2004-08-13 Nick Clifton <nickc@redhat.com>
1311 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1314 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1316 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1318 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1320 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1322 2004-07-21 Jan Beulich <jbeulich@novell.com>
1324 * i386.h: Adjust instruction descriptions to better match the
1327 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
1329 * arm.h: Remove all old content. Replace with architecture defines
1330 from gas/config/tc-arm.c.
1332 2004-07-09 Andreas Schwab <schwab@suse.de>
1334 * m68k.h: Fix comment.
1336 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1340 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1342 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1344 2004-05-24 Peter Barada <peter@the-baradas.com>
1346 * m68k.h: Add 'size' to m68k_opcode.
1348 2004-05-05 Peter Barada <peter@the-baradas.com>
1350 * m68k.h: Switch from ColdFire chip name to core variant.
1352 2004-04-22 Peter Barada <peter@the-baradas.com>
1354 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1355 descriptions for new EMAC cases.
1356 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1357 handle Motorola MAC syntax.
1358 Allow disassembly of ColdFire V4e object files.
1360 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1362 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1364 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1366 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1368 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1370 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1372 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1374 * i386.h (i386_optab): Added xstore/xcrypt insns.
1376 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1378 * h8300.h (32bit ldc/stc): Add relaxing support.
1380 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1382 * h8300.h (BITOP): Pass MEMRELAX flag.
1384 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1386 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1389 For older changes see ChangeLog-9103
1395 version-control: never