1 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
3 * mips.h: Update commentary after last commit.
5 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
7 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
8 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
9 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
11 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
13 * mips.h: Fix previous commit.
15 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
17 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
18 (INSN_LOONGSON_3A): Clear bit 31.
20 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
23 * arm.h (ARM_AEXT_V6M_ONLY): New define.
24 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
25 (ARM_ARCH_V6M_ONLY): New define.
27 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
29 * mips.h (INSN_LOONGSON_3A): Defined.
30 (CPU_LOONGSON_3A): Defined.
31 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
33 2010-10-09 Matt Rice <ratmice@gmail.com>
35 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
36 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
38 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
40 * arm.h (ARM_EXT_VIRT): New define.
41 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
42 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
45 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
47 * arm.h (ARM_AEXT_ADIV): New define.
48 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
50 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
52 * arm.h (ARM_EXT_OS): New define.
53 (ARM_AEXT_V6SM): Likewise.
54 (ARM_ARCH_V6SM): Likewise.
56 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
58 * arm.h (ARM_EXT_MP): Add.
59 (ARM_ARCH_V7A_MP): Likewise.
61 2010-09-22 Mike Frysinger <vapier@gentoo.org>
63 * bfin.h: Declare pseudoChr structs/defines.
65 2010-09-21 Mike Frysinger <vapier@gentoo.org>
67 * bfin.h: Strip trailing whitespace.
69 2010-07-29 DJ Delorie <dj@redhat.com>
71 * rx.h (RX_Operand_Type): Add TwoReg.
72 (RX_Opcode_ID): Remove ediv and ediv2.
74 2010-07-27 DJ Delorie <dj@redhat.com>
76 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
78 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
79 Ina Pandit <ina.pandit@kpitcummins.com>
81 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
82 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
84 Remove PROCESSOR_V850EA support.
85 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
86 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
87 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
88 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
89 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
91 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
93 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
96 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
98 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
99 (MIPS16_INSN_BRANCH): Rename to...
100 (MIPS16_INSN_COND_BRANCH): ... this.
102 2010-07-03 Alan Modra <amodra@gmail.com>
104 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
105 Renumber other PPC_OPCODE defines.
107 2010-07-03 Alan Modra <amodra@gmail.com>
109 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
111 2010-06-29 Alan Modra <amodra@gmail.com>
113 * maxq.h: Delete file.
115 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
117 * ppc.h (PPC_OPCODE_E500): Define.
119 2010-05-26 Catherine Moore <clm@codesourcery.com>
121 * opcode/mips.h (INSN_MIPS16): Remove.
123 2010-04-21 Joseph Myers <joseph@codesourcery.com>
125 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
127 2010-04-15 Nick Clifton <nickc@redhat.com>
129 * alpha.h: Update copyright notice to use GPLv3.
135 * convex.h: Likewise.
149 * m68hc11.h: Likewise.
155 * mn10200.h: Likewise.
156 * mn10300.h: Likewise.
157 * msp430.h: Likewise.
168 * score-datadep.h: Likewise.
169 * score-inst.h: Likewise.
171 * spu-insns.h: Likewise.
175 * tic54x.h: Likewise.
180 2010-03-25 Joseph Myers <joseph@codesourcery.com>
182 * tic6x-control-registers.h, tic6x-insn-formats.h,
183 tic6x-opcode-table.h, tic6x.h: New.
185 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
187 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
189 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
191 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
193 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
195 * ia64.h (ia64_find_opcode): Remove argument name.
196 (ia64_find_next_opcode): Likewise.
197 (ia64_dis_opcode): Likewise.
198 (ia64_free_opcode): Likewise.
199 (ia64_find_dependency): Likewise.
201 2009-11-22 Doug Evans <dje@sebabeach.org>
203 * cgen.h: Include bfd_stdint.h.
204 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
206 2009-11-18 Paul Brook <paul@codesourcery.com>
208 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
210 2009-11-17 Paul Brook <paul@codesourcery.com>
211 Daniel Jacobowitz <dan@codesourcery.com>
213 * arm.h (ARM_EXT_V6_DSP): Define.
214 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
215 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
217 2009-11-04 DJ Delorie <dj@redhat.com>
219 * rx.h (rx_decode_opcode) (mvtipl): Add.
220 (mvtcp, mvfcp, opecp): Remove.
222 2009-11-02 Paul Brook <paul@codesourcery.com>
224 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
225 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
226 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
227 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
228 FPU_ARCH_NEON_VFP_V4): Define.
230 2009-10-23 Doug Evans <dje@sebabeach.org>
232 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
233 * cgen.h: Update. Improve multi-inclusion macro name.
235 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
237 * ppc.h (PPC_OPCODE_476): Define.
239 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
241 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
243 2009-09-29 DJ Delorie <dj@redhat.com>
247 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
249 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
251 2009-09-21 Ben Elliston <bje@au.ibm.com>
253 * ppc.h (PPC_OPCODE_PPCA2): New.
255 2009-09-05 Martin Thuresson <martin@mtme.org>
257 * ia64.h (struct ia64_operand): Renamed member class to op_class.
259 2009-08-29 Martin Thuresson <martin@mtme.org>
261 * tic30.h (template): Rename type template to
262 insn_template. Updated code to use new name.
263 * tic54x.h (template): Rename type template to
266 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
268 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
270 2009-06-11 Anthony Green <green@moxielogic.com>
272 * moxie.h (MOXIE_F3_PCREL): Define.
273 (moxie_form3_opc_info): Grow.
275 2009-06-06 Anthony Green <green@moxielogic.com>
277 * moxie.h (MOXIE_F1_M): Define.
279 2009-04-15 Anthony Green <green@moxielogic.com>
283 2009-04-06 DJ Delorie <dj@redhat.com>
285 * h8300.h: Add relaxation attributes to MOVA opcodes.
287 2009-03-10 Alan Modra <amodra@bigpond.net.au>
289 * ppc.h (ppc_parse_cpu): Declare.
291 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
293 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
294 and _IMM11 for mbitclr and mbitset.
295 * score-datadep.h: Update dependency information.
297 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
299 * ppc.h (PPC_OPCODE_POWER7): New.
301 2009-02-06 Doug Evans <dje@google.com>
303 * i386.h: Add comment regarding sse* insns and prefixes.
305 2009-02-03 Sandip Matte <sandip@rmicorp.com>
307 * mips.h (INSN_XLR): Define.
308 (INSN_CHIP_MASK): Update.
310 (OPCODE_IS_MEMBER): Update.
311 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
313 2009-01-28 Doug Evans <dje@google.com>
315 * opcode/i386.h: Add multiple inclusion protection.
316 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
317 (EDI_REG_NUM): New macros.
318 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
319 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
320 (REX_PREFIX_P): New macro.
322 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
324 * ppc.h (struct powerpc_opcode): New field "deprecated".
325 (PPC_OPCODE_NOPOWER4): Delete.
327 2008-11-28 Joshua Kinard <kumba@gentoo.org>
329 * mips.h: Define CPU_R14000, CPU_R16000.
330 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
332 2008-11-18 Catherine Moore <clm@codesourcery.com>
334 * arm.h (FPU_NEON_FP16): New.
335 (FPU_ARCH_NEON_FP16): New.
337 2008-11-06 Chao-ying Fu <fu@mips.com>
339 * mips.h: Doucument '1' for 5-bit sync type.
341 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
343 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
346 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
348 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
350 2008-07-30 Michael J. Eager <eager@eagercon.com>
352 * ppc.h (PPC_OPCODE_405): Define.
353 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
355 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
357 * ppc.h (ppc_cpu_t): New typedef.
358 (struct powerpc_opcode <flags>): Use it.
359 (struct powerpc_operand <insert, extract>): Likewise.
360 (struct powerpc_macro <flags>): Likewise.
362 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
364 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
365 Update comment before MIPS16 field descriptors to mention MIPS16.
366 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
368 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
369 New bit masks and shift counts for cins and exts.
371 * mips.h: Document new field descriptors +Q.
372 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
374 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
376 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
377 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
379 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
381 * ppc.h: (PPC_OPCODE_E500MC): New.
383 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
385 * i386.h (MAX_OPERANDS): Set to 5.
386 (MAX_MNEM_SIZE): Changed to 20.
388 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
390 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
392 2008-03-09 Paul Brook <paul@codesourcery.com>
394 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
396 2008-03-04 Paul Brook <paul@codesourcery.com>
398 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
399 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
400 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
402 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
403 Nick Clifton <nickc@redhat.com>
406 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
407 with a 32-bit displacement but without the top bit of the 4th byte
410 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
412 * cr16.h (cr16_num_optab): Declared.
414 2008-02-14 Hakan Ardo <hakan@debian.org>
417 * avr.h (AVR_ISA_2xxe): Define.
419 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
421 * mips.h: Update copyright.
422 (INSN_CHIP_MASK): New macro.
423 (INSN_OCTEON): New macro.
424 (CPU_OCTEON): New macro.
425 (OPCODE_IS_MEMBER): Handle Octeon instructions.
427 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
429 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
431 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
433 * avr.h (AVR_ISA_USB162): Add new opcode set.
434 (AVR_ISA_AVR3): Likewise.
436 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
438 * mips.h (INSN_LOONGSON_2E): New.
439 (INSN_LOONGSON_2F): New.
440 (CPU_LOONGSON_2E): New.
441 (CPU_LOONGSON_2F): New.
442 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
444 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
446 * mips.h (INSN_ISA*): Redefine certain values as an
447 enumeration. Update comments.
448 (mips_isa_table): New.
449 (ISA_MIPS*): Redefine to match enumeration.
450 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
453 2007-08-08 Ben Elliston <bje@au.ibm.com>
455 * ppc.h (PPC_OPCODE_PPCPS): New.
457 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
459 * m68k.h: Document j K & E.
461 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
463 * cr16.h: New file for CR16 target.
465 2007-05-02 Alan Modra <amodra@bigpond.net.au>
467 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
469 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
471 * m68k.h (mcfisa_c): New.
472 (mcfusp, mcf_mask): Adjust.
474 2007-04-20 Alan Modra <amodra@bigpond.net.au>
476 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
477 (num_powerpc_operands): Declare.
478 (PPC_OPERAND_SIGNED et al): Redefine as hex.
479 (PPC_OPERAND_PLUS1): Define.
481 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
483 * i386.h (REX_MODE64): Renamed to ...
485 (REX_EXTX): Renamed to ...
487 (REX_EXTY): Renamed to ...
489 (REX_EXTZ): Renamed to ...
492 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
494 * i386.h: Add entries from config/tc-i386.h and move tables
495 to opcodes/i386-opc.h.
497 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
499 * i386.h (FloatDR): Removed.
500 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
502 2007-03-01 Alan Modra <amodra@bigpond.net.au>
504 * spu-insns.h: Add soma double-float insns.
506 2007-02-20 Thiemo Seufer <ths@mips.com>
507 Chao-Ying Fu <fu@mips.com>
509 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
510 (INSN_DSPR2): Add flag for DSP R2 instructions.
511 (M_BALIGN): New macro.
513 2007-02-14 Alan Modra <amodra@bigpond.net.au>
515 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
516 and Seg3ShortFrom with Shortform.
518 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
521 * i386.h (i386_optab): Put the real "test" before the pseudo
524 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
526 * m68k.h (m68010up): OR fido_a.
528 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
530 * m68k.h (fido_a): New.
532 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
534 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
535 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
538 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
540 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
542 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
544 * score-inst.h (enum score_insn_type): Add Insn_internal.
546 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
547 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
548 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
549 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
550 Alan Modra <amodra@bigpond.net.au>
552 * spu-insns.h: New file.
555 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
557 * ppc.h (PPC_OPCODE_CELL): Define.
559 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
561 * i386.h : Modify opcode to support for the change in POPCNT opcode
562 in amdfam10 architecture.
564 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
566 * i386.h: Replace CpuMNI with CpuSSSE3.
568 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
569 Joseph Myers <joseph@codesourcery.com>
570 Ian Lance Taylor <ian@wasabisystems.com>
571 Ben Elliston <bje@wasabisystems.com>
573 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
575 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
577 * score-datadep.h: New file.
578 * score-inst.h: New file.
580 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
582 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
583 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
586 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
587 Michael Meissner <michael.meissner@amd.com>
589 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
591 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
593 * i386.h (i386_optab): Add "nop" with memory reference.
595 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
597 * i386.h (i386_optab): Update comment for 64bit NOP.
599 2006-06-06 Ben Elliston <bje@au.ibm.com>
600 Anton Blanchard <anton@samba.org>
602 * ppc.h (PPC_OPCODE_POWER6): Define.
605 2006-06-05 Thiemo Seufer <ths@mips.com>
607 * mips.h: Improve description of MT flags.
609 2006-05-25 Richard Sandiford <richard@codesourcery.com>
611 * m68k.h (mcf_mask): Define.
613 2006-05-05 Thiemo Seufer <ths@mips.com>
614 David Ung <davidu@mips.com>
616 * mips.h (enum): Add macro M_CACHE_AB.
618 2006-05-04 Thiemo Seufer <ths@mips.com>
619 Nigel Stephens <nigel@mips.com>
620 David Ung <davidu@mips.com>
622 * mips.h: Add INSN_SMARTMIPS define.
624 2006-04-30 Thiemo Seufer <ths@mips.com>
625 David Ung <davidu@mips.com>
627 * mips.h: Defines udi bits and masks. Add description of
628 characters which may appear in the args field of udi
631 2006-04-26 Thiemo Seufer <ths@networkno.de>
633 * mips.h: Improve comments describing the bitfield instruction
636 2006-04-26 Julian Brown <julian@codesourcery.com>
638 * arm.h (FPU_VFP_EXT_V3): Define constant.
639 (FPU_NEON_EXT_V1): Likewise.
640 (FPU_VFP_HARD): Update.
641 (FPU_VFP_V3): Define macro.
642 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
644 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
646 * avr.h (AVR_ISA_PWMx): New.
648 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
650 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
651 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
652 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
653 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
654 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
656 2006-03-10 Paul Brook <paul@codesourcery.com>
658 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
660 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
662 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
663 first. Correct mask of bb "B" opcode.
665 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
667 * i386.h (i386_optab): Support Intel Merom New Instructions.
669 2006-02-24 Paul Brook <paul@codesourcery.com>
671 * arm.h: Add V7 feature bits.
673 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
675 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
677 2006-01-31 Paul Brook <paul@codesourcery.com>
678 Richard Earnshaw <rearnsha@arm.com>
680 * arm.h: Use ARM_CPU_FEATURE.
681 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
682 (arm_feature_set): Change to a structure.
683 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
684 ARM_FEATURE): New macros.
686 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
688 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
689 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
690 (ADD_PC_INCR_OPCODE): Don't define.
692 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
695 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
697 2005-11-14 David Ung <davidu@mips.com>
699 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
700 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
701 save/restore encoding of the args field.
703 2005-10-28 Dave Brolley <brolley@redhat.com>
705 Contribute the following changes:
706 2005-02-16 Dave Brolley <brolley@redhat.com>
708 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
709 cgen_isa_mask_* to cgen_bitset_*.
712 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
714 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
715 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
716 (CGEN_CPU_TABLE): Make isas a ponter.
718 2003-09-29 Dave Brolley <brolley@redhat.com>
720 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
721 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
722 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
724 2002-12-13 Dave Brolley <brolley@redhat.com>
726 * cgen.h (symcat.h): #include it.
727 (cgen-bitset.h): #include it.
728 (CGEN_ATTR_VALUE_TYPE): Now a union.
729 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
730 (CGEN_ATTR_ENTRY): 'value' now unsigned.
731 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
732 * cgen-bitset.h: New file.
734 2005-09-30 Catherine Moore <clm@cm00re.com>
738 2005-10-24 Jan Beulich <jbeulich@novell.com>
740 * ia64.h (enum ia64_opnd): Move memory operand out of set of
743 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
745 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
746 Add FLAG_STRICT to pa10 ftest opcode.
748 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
750 * hppa.h (pa_opcodes): Remove lha entries.
752 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
754 * hppa.h (FLAG_STRICT): Revise comment.
755 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
756 before corresponding pa11 opcodes. Add strict pa10 register-immediate
759 2005-09-30 Catherine Moore <clm@cm00re.com>
763 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
765 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
767 2005-09-06 Chao-ying Fu <fu@mips.com>
769 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
770 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
772 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
773 (INSN_ASE_MASK): Update to include INSN_MT.
774 (INSN_MT): New define for MT ASE.
776 2005-08-25 Chao-ying Fu <fu@mips.com>
778 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
779 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
780 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
781 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
782 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
783 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
785 (INSN_DSP): New define for DSP ASE.
787 2005-08-18 Alan Modra <amodra@bigpond.net.au>
791 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
793 * ppc.h (PPC_OPCODE_E300): Define.
795 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
797 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
799 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
802 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
805 2005-07-27 Jan Beulich <jbeulich@novell.com>
807 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
808 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
809 Add movq-s as 64-bit variants of movd-s.
811 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
813 * hppa.h: Fix punctuation in comment.
815 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
816 implicit space-register addressing. Set space-register bits on opcodes
817 using implicit space-register addressing. Add various missing pa20
818 long-immediate opcodes. Remove various opcodes using implicit 3-bit
819 space-register addressing. Use "fE" instead of "fe" in various
822 2005-07-18 Jan Beulich <jbeulich@novell.com>
824 * i386.h (i386_optab): Operands of aam and aad are unsigned.
826 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
828 * i386.h (i386_optab): Support Intel VMX Instructions.
830 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
832 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
834 2005-07-05 Jan Beulich <jbeulich@novell.com>
836 * i386.h (i386_optab): Add new insns.
838 2005-07-01 Nick Clifton <nickc@redhat.com>
840 * sparc.h: Add typedefs to structure declarations.
842 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
845 * i386.h (i386_optab): Update comments for 64bit addressing on
846 mov. Allow 64bit addressing for mov and movq.
848 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
850 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
851 respectively, in various floating-point load and store patterns.
853 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
855 * hppa.h (FLAG_STRICT): Correct comment.
856 (pa_opcodes): Update load and store entries to allow both PA 1.X and
857 PA 2.0 mneumonics when equivalent. Entries with cache control
858 completers now require PA 1.1. Adjust whitespace.
860 2005-05-19 Anton Blanchard <anton@samba.org>
862 * ppc.h (PPC_OPCODE_POWER5): Define.
864 2005-05-10 Nick Clifton <nickc@redhat.com>
866 * Update the address and phone number of the FSF organization in
867 the GPL notices in the following files:
868 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
869 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
870 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
871 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
872 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
873 tic54x.h, tic80.h, v850.h, vax.h
875 2005-05-09 Jan Beulich <jbeulich@novell.com>
877 * i386.h (i386_optab): Add ht and hnt.
879 2005-04-18 Mark Kettenis <kettenis@gnu.org>
881 * i386.h: Insert hyphens into selected VIA PadLock extensions.
882 Add xcrypt-ctr. Provide aliases without hyphens.
884 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
886 Moved from ../ChangeLog
888 2005-04-12 Paul Brook <paul@codesourcery.com>
889 * m88k.h: Rename psr macros to avoid conflicts.
891 2005-03-12 Zack Weinberg <zack@codesourcery.com>
892 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
893 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
896 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
897 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
898 Remove redundant instruction types.
899 (struct argument): X_op - new field.
900 (struct cst4_entry): Remove.
901 (no_op_insn): Declare.
903 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
904 * crx.h (enum argtype): Rename types, remove unused types.
906 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
907 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
908 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
909 (enum operand_type): Rearrange operands, edit comments.
910 replace us<N> with ui<N> for unsigned immediate.
911 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
912 displacements (respectively).
913 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
914 (instruction type): Add NO_TYPE_INS.
915 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
916 (operand_entry): New field - 'flags'.
917 (operand flags): New.
919 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
920 * crx.h (operand_type): Remove redundant types i3, i4,
922 Add new unsigned immediate types us3, us4, us5, us16.
924 2005-04-12 Mark Kettenis <kettenis@gnu.org>
926 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
927 adjust them accordingly.
929 2005-04-01 Jan Beulich <jbeulich@novell.com>
931 * i386.h (i386_optab): Add rdtscp.
933 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
935 * i386.h (i386_optab): Don't allow the `l' suffix for moving
936 between memory and segment register. Allow movq for moving between
937 general-purpose register and segment register.
939 2005-02-09 Jan Beulich <jbeulich@novell.com>
942 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
943 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
946 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
948 * m68k.h (m68008, m68ec030, m68882): Remove.
950 (cpu_m68k, cpu_cf): New.
951 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
952 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
954 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
956 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
957 * cgen.h (enum cgen_parse_operand_type): Add
958 CGEN_PARSE_OPERAND_SYMBOLIC.
960 2005-01-21 Fred Fish <fnf@specifixinc.com>
962 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
963 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
964 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
966 2005-01-19 Fred Fish <fnf@specifixinc.com>
968 * mips.h (struct mips_opcode): Add new pinfo2 member.
969 (INSN_ALIAS): New define for opcode table entries that are
970 specific instances of another entry, such as 'move' for an 'or'
972 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
973 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
975 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
977 * mips.h (CPU_RM9000): Define.
978 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
980 2004-11-25 Jan Beulich <jbeulich@novell.com>
982 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
983 to/from test registers are illegal in 64-bit mode. Add missing
984 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
985 (previously one had to explicitly encode a rex64 prefix). Re-enable
986 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
987 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
989 2004-11-23 Jan Beulich <jbeulich@novell.com>
991 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
992 available only with SSE2. Change the MMX additions introduced by SSE
993 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
994 instructions by their now designated identifier (since combining i686
995 and 3DNow! does not really imply 3DNow!A).
997 2004-11-19 Alan Modra <amodra@bigpond.net.au>
999 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1000 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1002 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1003 Vineet Sharma <vineets@noida.hcltech.com>
1005 * maxq.h: New file: Disassembly information for the maxq port.
1007 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1009 * i386.h (i386_optab): Put back "movzb".
1011 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
1013 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1014 comments. Remove member cris_ver_sim. Add members
1015 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1016 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1017 (struct cris_support_reg, struct cris_cond15): New types.
1018 (cris_conds15): Declare.
1019 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1020 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1021 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1022 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1023 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1024 SIZE_FIELD_UNSIGNED.
1026 2004-11-04 Jan Beulich <jbeulich@novell.com>
1028 * i386.h (sldx_Suf): Remove.
1029 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1030 (q_FP): Define, implying no REX64.
1031 (x_FP, sl_FP): Imply FloatMF.
1032 (i386_optab): Split reg and mem forms of moving from segment registers
1033 so that the memory forms can ignore the 16-/32-bit operand size
1034 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1035 all non-floating-point instructions. Unite 32- and 64-bit forms of
1036 movsx, movzx, and movd. Adjust floating point operations for the above
1037 changes to the *FP macros. Add DefaultSize to floating point control
1038 insns operating on larger memory ranges. Remove left over comments
1039 hinting at certain insns being Intel-syntax ones where the ones
1040 actually meant are already gone.
1042 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1044 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1047 2004-09-30 Paul Brook <paul@codesourcery.com>
1049 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1050 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1052 2004-09-11 Theodore A. Roth <troth@openavr.org>
1054 * avr.h: Add support for
1055 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1057 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1059 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1061 2004-08-24 Dmitry Diky <diwil@spec.ru>
1063 * msp430.h (msp430_opc): Add new instructions.
1064 (msp430_rcodes): Declare new instructions.
1065 (msp430_hcodes): Likewise..
1067 2004-08-13 Nick Clifton <nickc@redhat.com>
1070 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1073 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1075 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1077 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1079 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1081 2004-07-21 Jan Beulich <jbeulich@novell.com>
1083 * i386.h: Adjust instruction descriptions to better match the
1086 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
1088 * arm.h: Remove all old content. Replace with architecture defines
1089 from gas/config/tc-arm.c.
1091 2004-07-09 Andreas Schwab <schwab@suse.de>
1093 * m68k.h: Fix comment.
1095 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1099 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1101 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1103 2004-05-24 Peter Barada <peter@the-baradas.com>
1105 * m68k.h: Add 'size' to m68k_opcode.
1107 2004-05-05 Peter Barada <peter@the-baradas.com>
1109 * m68k.h: Switch from ColdFire chip name to core variant.
1111 2004-04-22 Peter Barada <peter@the-baradas.com>
1113 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1114 descriptions for new EMAC cases.
1115 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1116 handle Motorola MAC syntax.
1117 Allow disassembly of ColdFire V4e object files.
1119 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1121 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1123 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1125 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1127 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1129 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1131 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1133 * i386.h (i386_optab): Added xstore/xcrypt insns.
1135 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1137 * h8300.h (32bit ldc/stc): Add relaxing support.
1139 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1141 * h8300.h (BITOP): Pass MEMRELAX flag.
1143 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1145 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1148 For older changes see ChangeLog-9103
1154 version-control: never