1 2013-05-02 Nick Clifton <nickc@redhat.com>
3 * msp430.h: Add patterns for MSP430X instructions.
5 2013-04-06 David S. Miller <davem@davemloft.net>
7 * sparc.h (F_PREFERRED): Define.
8 (F_PREF_ALIAS): Define.
10 2013-04-03 Nick Clifton <nickc@redhat.com>
12 * v850.h (V850_INVERSE_PCREL): Define.
14 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
17 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
19 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
22 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
24 * tic6xc-opcode-table.h: Add 16-bit insns.
25 * tic6x.h: Add support for 16-bit insns.
27 2013-03-21 Michael Schewe <michael.schewe@gmx.net>
29 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
30 and mov.b/w/l Rs,@(d:32,ERd).
32 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
35 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
36 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
37 tic6x_operand_xregpair operand coding type.
38 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
39 opcode field, usu ORXREGD1324 for the src2 operand and remove the
42 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
45 * tic6x.h (enum tic6x_coding_method): Add
46 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
47 separately the msb and lsb of a register pair. This is needed to
48 encode the opcodes in the same way as TI assembler does.
49 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
50 and rsqrdp opcodes to use the new field coding types.
52 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
54 * arm.h (CRC_EXT_ARMV8): New constant.
55 (ARCH_CRC_ARMV8): New macro.
57 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
59 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
61 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
62 Andrew Jenner <andrew@codesourcery.com>
64 Based on patches from Altera Corporation.
68 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
70 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
72 2013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
75 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
77 2013-01-24 Nick Clifton <nickc@redhat.com>
79 * v850.h: Add e3v5 support.
81 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
83 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
85 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
87 * ppc.h (PPC_OPCODE_POWER8): New define.
88 (PPC_OPCODE_HTM): Likewise.
90 2013-01-10 Will Newton <will.newton@imgtec.com>
94 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
96 * cr16.h (make_instruction): Rename to cr16_make_instruction.
97 (match_opcode): Rename to cr16_match_opcode.
99 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
101 * mips.h: Add support for r5900 instructions including lq and sq.
103 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
105 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
106 (make_instruction,match_opcode): Added function prototypes.
107 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
109 2012-11-23 Alan Modra <amodra@gmail.com>
111 * ppc.h (ppc_parse_cpu): Update prototype.
113 2012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
115 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
116 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
118 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
120 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
122 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
124 * ia64.h (ia64_opnd): Add new operand types.
126 2012-08-21 David S. Miller <davem@davemloft.net>
128 * sparc.h (F3F4): New macro.
130 2012-08-13 Ian Bolton <ian.bolton@arm.com>
131 Laurent Desnogues <laurent.desnogues@arm.com>
132 Jim MacArthur <jim.macarthur@arm.com>
133 Marcus Shawcroft <marcus.shawcroft@arm.com>
134 Nigel Stephens <nigel.stephens@arm.com>
135 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
136 Richard Earnshaw <rearnsha@arm.com>
137 Sofiane Naci <sofiane.naci@arm.com>
138 Tejas Belagod <tejas.belagod@arm.com>
139 Yufeng Zhang <yufeng.zhang@arm.com>
141 * aarch64.h: New file.
143 2012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
144 Maciej W. Rozycki <macro@codesourcery.com>
146 * mips.h (mips_opcode): Add the exclusions field.
147 (OPCODE_IS_MEMBER): Remove macro.
148 (cpu_is_member): New inline function.
149 (opcode_is_member): Likewise.
151 2012-07-31 Chao-Ying Fu <fu@mips.com>
152 Catherine Moore <clm@codesourcery.com>
153 Maciej W. Rozycki <macro@codesourcery.com>
155 * mips.h: Document microMIPS DSP ASE usage.
156 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
157 microMIPS DSP ASE support.
158 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
159 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
160 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
161 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
162 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
163 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
164 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
166 2012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
168 * mips.h: Fix a typo in description.
170 2012-06-07 Georg-Johann Lay <avr@gjlay.de>
172 * avr.h: (AVR_ISA_XCH): New define.
173 (AVR_ISA_XMEGA): Use it.
174 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
176 2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
178 * m68hc11.h: Add XGate definitions.
179 (struct m68hc11_opcode): Add xg_mask field.
181 2012-05-14 Catherine Moore <clm@codesourcery.com>
182 Maciej W. Rozycki <macro@codesourcery.com>
183 Rhonda Wittels <rhonda@codesourcery.com>
185 * ppc.h (PPC_OPCODE_VLE): New definition.
186 (PPC_OP_SA): New macro.
187 (PPC_OP_SE_VLE): New macro.
188 (PPC_OP): Use a variable shift amount.
189 (powerpc_operand): Update comments.
190 (PPC_OPSHIFT_INV): New macro.
191 (PPC_OPERAND_CR): Replace with...
192 (PPC_OPERAND_CR_BIT): ...this and
193 (PPC_OPERAND_CR_REG): ...this.
196 2012-05-03 Sean Keys <skeys@ipdatasys.com>
198 * xgate.h: Header file for XGATE assembler.
200 2012-04-27 David S. Miller <davem@davemloft.net>
202 * sparc.h: Document new arg code' )' for crypto RS3
205 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
206 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
207 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
208 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
209 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
210 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
211 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
212 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
213 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
214 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
215 HWCAP_CBCOND, HWCAP_CRC32): New defines.
217 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
219 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
221 2012-02-27 Alan Modra <amodra@gmail.com>
223 * crx.h (cst4_map): Update declaration.
225 2012-02-25 Walter Lee <walt@tilera.com>
227 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
229 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
230 TILEPRO_OPC_LW_TLS_SN.
232 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
234 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
235 (XRELEASE_PREFIX_OPCODE): Likewise.
237 2011-12-08 Andrew Pinski <apinski@cavium.com>
238 Adam Nemet <anemet@caviumnetworks.com>
240 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
241 (INSN_OCTEON2): New macro.
242 (CPU_OCTEON2): New macro.
243 (OPCODE_IS_MEMBER): Add Octeon2.
245 2011-11-29 Andrew Pinski <apinski@cavium.com>
247 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
248 (INSN_OCTEONP): New macro.
249 (CPU_OCTEONP): New macro.
250 (OPCODE_IS_MEMBER): Add Octeon+.
251 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
253 2011-11-01 DJ Delorie <dj@redhat.com>
257 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
259 * mips.h: Fix a typo in description.
261 2011-09-21 David S. Miller <davem@davemloft.net>
263 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
264 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
265 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
266 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
268 2011-08-09 Chao-ying Fu <fu@mips.com>
269 Maciej W. Rozycki <macro@codesourcery.com>
271 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
272 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
273 (INSN_ASE_MASK): Add the MCU bit.
274 (INSN_MCU): New macro.
275 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
276 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
278 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
280 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
281 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
282 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
283 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
284 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
285 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
286 (INSN2_READ_GPR_MMN): Likewise.
287 (INSN2_READ_FPR_D): Change the bit used.
288 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
289 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
290 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
291 (INSN2_COND_BRANCH): Likewise.
292 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
293 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
294 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
295 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
296 (INSN2_MOD_GPR_MN): Likewise.
298 2011-08-05 David S. Miller <davem@davemloft.net>
300 * sparc.h: Document new format codes '4', '5', and '('.
301 (OPF_LOW4, RS3): New macros.
303 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
305 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
306 order of flags documented.
308 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
310 * mips.h: Clarify the description of microMIPS instruction
312 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
314 2011-07-24 Chao-ying Fu <fu@mips.com>
315 Maciej W. Rozycki <macro@codesourcery.com>
317 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
318 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
319 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
320 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
321 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
322 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
323 (OP_MASK_RS3, OP_SH_RS3): Likewise.
324 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
325 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
326 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
327 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
328 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
329 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
330 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
331 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
332 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
333 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
334 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
335 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
336 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
337 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
338 (INSN_WRITE_GPR_S): New macro.
339 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
340 (INSN2_READ_FPR_D): Likewise.
341 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
342 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
343 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
344 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
345 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
346 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
347 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
348 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
349 (CPU_MICROMIPS): New macro.
350 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
351 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
352 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
353 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
354 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
355 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
356 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
357 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
358 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
359 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
360 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
361 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
362 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
363 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
364 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
365 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
366 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
367 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
368 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
369 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
370 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
371 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
372 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
373 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
374 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
375 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
376 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
377 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
378 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
379 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
380 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
381 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
382 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
383 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
384 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
385 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
386 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
387 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
388 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
389 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
390 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
391 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
392 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
393 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
394 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
395 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
396 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
397 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
398 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
399 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
400 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
401 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
402 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
403 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
404 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
405 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
406 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
407 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
408 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
409 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
410 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
411 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
412 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
413 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
414 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
415 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
416 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
417 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
418 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
419 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
420 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
421 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
422 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
423 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
424 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
425 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
426 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
427 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
428 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
429 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
430 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
431 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
432 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
433 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
434 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
435 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
436 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
437 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
438 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
439 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
440 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
441 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
442 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
443 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
444 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
445 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
446 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
447 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
448 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
449 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
450 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
451 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
452 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
453 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
454 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
455 (micromips_opcodes): New declaration.
456 (bfd_micromips_num_opcodes): Likewise.
458 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
460 * mips.h (INSN_TRAP): Rename to...
461 (INSN_NO_DELAY_SLOT): ... this.
462 (INSN_SYNC): Remove macro.
464 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
466 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
467 a duplicate of AVR_ISA_SPM.
469 2011-07-01 Nick Clifton <nickc@redhat.com>
471 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
473 2011-06-18 Robin Getz <robin.getz@analog.com>
475 * bfin.h (is_macmod_signed): New func
477 2011-06-18 Mike Frysinger <vapier@gentoo.org>
479 * bfin.h (is_macmod_pmove): Add missing space before func args.
480 (is_macmod_hmove): Likewise.
482 2011-06-13 Walter Lee <walt@tilera.com>
484 * tilegx.h: New file.
485 * tilepro.h: New file.
487 2011-05-31 Paul Brook <paul@codesourcery.com>
489 * arm.h (ARM_ARCH_V7R_IDIV): Define.
491 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
493 * s390.h: Replace S390_OPERAND_REG_EVEN with
494 S390_OPERAND_REG_PAIR.
496 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
498 * s390.h: Add S390_OPCODE_REG_EVEN flag.
500 2011-04-18 Julian Brown <julian@codesourcery.com>
502 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
504 2011-04-11 Dan McDonald <dan@wellkeeper.com>
507 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
509 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
511 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
512 New instruction set flags.
513 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
515 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
517 * mips.h (M_PREF_AB): New enum value.
519 2011-02-12 Mike Frysinger <vapier@gentoo.org>
521 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
523 (is_macmod_pmove, is_macmod_hmove): New functions.
525 2011-02-11 Mike Frysinger <vapier@gentoo.org>
527 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
529 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
531 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
532 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
534 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
537 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
540 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
543 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
545 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
547 * mips.h: Update commentary after last commit.
549 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
551 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
552 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
553 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
555 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
557 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
559 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
561 * mips.h: Fix previous commit.
563 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
565 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
566 (INSN_LOONGSON_3A): Clear bit 31.
568 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
571 * arm.h (ARM_AEXT_V6M_ONLY): New define.
572 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
573 (ARM_ARCH_V6M_ONLY): New define.
575 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
577 * mips.h (INSN_LOONGSON_3A): Defined.
578 (CPU_LOONGSON_3A): Defined.
579 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
581 2010-10-09 Matt Rice <ratmice@gmail.com>
583 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
584 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
586 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
588 * arm.h (ARM_EXT_VIRT): New define.
589 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
590 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
593 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
595 * arm.h (ARM_AEXT_ADIV): New define.
596 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
598 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
600 * arm.h (ARM_EXT_OS): New define.
601 (ARM_AEXT_V6SM): Likewise.
602 (ARM_ARCH_V6SM): Likewise.
604 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
606 * arm.h (ARM_EXT_MP): Add.
607 (ARM_ARCH_V7A_MP): Likewise.
609 2010-09-22 Mike Frysinger <vapier@gentoo.org>
611 * bfin.h: Declare pseudoChr structs/defines.
613 2010-09-21 Mike Frysinger <vapier@gentoo.org>
615 * bfin.h: Strip trailing whitespace.
617 2010-07-29 DJ Delorie <dj@redhat.com>
619 * rx.h (RX_Operand_Type): Add TwoReg.
620 (RX_Opcode_ID): Remove ediv and ediv2.
622 2010-07-27 DJ Delorie <dj@redhat.com>
624 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
626 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
627 Ina Pandit <ina.pandit@kpitcummins.com>
629 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
630 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
631 PROCESSOR_V850E2_ALL.
632 Remove PROCESSOR_V850EA support.
633 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
634 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
635 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
636 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
637 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
638 V850_OPERAND_PERCENT.
639 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
641 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
644 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
646 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
647 (MIPS16_INSN_BRANCH): Rename to...
648 (MIPS16_INSN_COND_BRANCH): ... this.
650 2010-07-03 Alan Modra <amodra@gmail.com>
652 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
653 Renumber other PPC_OPCODE defines.
655 2010-07-03 Alan Modra <amodra@gmail.com>
657 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
659 2010-06-29 Alan Modra <amodra@gmail.com>
661 * maxq.h: Delete file.
663 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
665 * ppc.h (PPC_OPCODE_E500): Define.
667 2010-05-26 Catherine Moore <clm@codesourcery.com>
669 * opcode/mips.h (INSN_MIPS16): Remove.
671 2010-04-21 Joseph Myers <joseph@codesourcery.com>
673 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
675 2010-04-15 Nick Clifton <nickc@redhat.com>
677 * alpha.h: Update copyright notice to use GPLv3.
683 * convex.h: Likewise.
697 * m68hc11.h: Likewise.
703 * mn10200.h: Likewise.
704 * mn10300.h: Likewise.
705 * msp430.h: Likewise.
716 * score-datadep.h: Likewise.
717 * score-inst.h: Likewise.
719 * spu-insns.h: Likewise.
723 * tic54x.h: Likewise.
728 2010-03-25 Joseph Myers <joseph@codesourcery.com>
730 * tic6x-control-registers.h, tic6x-insn-formats.h,
731 tic6x-opcode-table.h, tic6x.h: New.
733 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
735 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
737 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
739 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
741 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
743 * ia64.h (ia64_find_opcode): Remove argument name.
744 (ia64_find_next_opcode): Likewise.
745 (ia64_dis_opcode): Likewise.
746 (ia64_free_opcode): Likewise.
747 (ia64_find_dependency): Likewise.
749 2009-11-22 Doug Evans <dje@sebabeach.org>
751 * cgen.h: Include bfd_stdint.h.
752 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
754 2009-11-18 Paul Brook <paul@codesourcery.com>
756 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
758 2009-11-17 Paul Brook <paul@codesourcery.com>
759 Daniel Jacobowitz <dan@codesourcery.com>
761 * arm.h (ARM_EXT_V6_DSP): Define.
762 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
763 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
765 2009-11-04 DJ Delorie <dj@redhat.com>
767 * rx.h (rx_decode_opcode) (mvtipl): Add.
768 (mvtcp, mvfcp, opecp): Remove.
770 2009-11-02 Paul Brook <paul@codesourcery.com>
772 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
773 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
774 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
775 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
776 FPU_ARCH_NEON_VFP_V4): Define.
778 2009-10-23 Doug Evans <dje@sebabeach.org>
780 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
781 * cgen.h: Update. Improve multi-inclusion macro name.
783 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
785 * ppc.h (PPC_OPCODE_476): Define.
787 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
789 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
791 2009-09-29 DJ Delorie <dj@redhat.com>
795 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
797 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
799 2009-09-21 Ben Elliston <bje@au.ibm.com>
801 * ppc.h (PPC_OPCODE_PPCA2): New.
803 2009-09-05 Martin Thuresson <martin@mtme.org>
805 * ia64.h (struct ia64_operand): Renamed member class to op_class.
807 2009-08-29 Martin Thuresson <martin@mtme.org>
809 * tic30.h (template): Rename type template to
810 insn_template. Updated code to use new name.
811 * tic54x.h (template): Rename type template to
814 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
816 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
818 2009-06-11 Anthony Green <green@moxielogic.com>
820 * moxie.h (MOXIE_F3_PCREL): Define.
821 (moxie_form3_opc_info): Grow.
823 2009-06-06 Anthony Green <green@moxielogic.com>
825 * moxie.h (MOXIE_F1_M): Define.
827 2009-04-15 Anthony Green <green@moxielogic.com>
831 2009-04-06 DJ Delorie <dj@redhat.com>
833 * h8300.h: Add relaxation attributes to MOVA opcodes.
835 2009-03-10 Alan Modra <amodra@bigpond.net.au>
837 * ppc.h (ppc_parse_cpu): Declare.
839 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
841 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
842 and _IMM11 for mbitclr and mbitset.
843 * score-datadep.h: Update dependency information.
845 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
847 * ppc.h (PPC_OPCODE_POWER7): New.
849 2009-02-06 Doug Evans <dje@google.com>
851 * i386.h: Add comment regarding sse* insns and prefixes.
853 2009-02-03 Sandip Matte <sandip@rmicorp.com>
855 * mips.h (INSN_XLR): Define.
856 (INSN_CHIP_MASK): Update.
858 (OPCODE_IS_MEMBER): Update.
859 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
861 2009-01-28 Doug Evans <dje@google.com>
863 * opcode/i386.h: Add multiple inclusion protection.
864 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
865 (EDI_REG_NUM): New macros.
866 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
867 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
868 (REX_PREFIX_P): New macro.
870 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
872 * ppc.h (struct powerpc_opcode): New field "deprecated".
873 (PPC_OPCODE_NOPOWER4): Delete.
875 2008-11-28 Joshua Kinard <kumba@gentoo.org>
877 * mips.h: Define CPU_R14000, CPU_R16000.
878 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
880 2008-11-18 Catherine Moore <clm@codesourcery.com>
882 * arm.h (FPU_NEON_FP16): New.
883 (FPU_ARCH_NEON_FP16): New.
885 2008-11-06 Chao-ying Fu <fu@mips.com>
887 * mips.h: Doucument '1' for 5-bit sync type.
889 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
891 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
894 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
896 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
898 2008-07-30 Michael J. Eager <eager@eagercon.com>
900 * ppc.h (PPC_OPCODE_405): Define.
901 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
903 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
905 * ppc.h (ppc_cpu_t): New typedef.
906 (struct powerpc_opcode <flags>): Use it.
907 (struct powerpc_operand <insert, extract>): Likewise.
908 (struct powerpc_macro <flags>): Likewise.
910 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
912 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
913 Update comment before MIPS16 field descriptors to mention MIPS16.
914 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
916 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
917 New bit masks and shift counts for cins and exts.
919 * mips.h: Document new field descriptors +Q.
920 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
922 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
924 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
925 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
927 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
929 * ppc.h: (PPC_OPCODE_E500MC): New.
931 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
933 * i386.h (MAX_OPERANDS): Set to 5.
934 (MAX_MNEM_SIZE): Changed to 20.
936 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
938 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
940 2008-03-09 Paul Brook <paul@codesourcery.com>
942 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
944 2008-03-04 Paul Brook <paul@codesourcery.com>
946 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
947 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
948 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
950 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
951 Nick Clifton <nickc@redhat.com>
954 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
955 with a 32-bit displacement but without the top bit of the 4th byte
958 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
960 * cr16.h (cr16_num_optab): Declared.
962 2008-02-14 Hakan Ardo <hakan@debian.org>
965 * avr.h (AVR_ISA_2xxe): Define.
967 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
969 * mips.h: Update copyright.
970 (INSN_CHIP_MASK): New macro.
971 (INSN_OCTEON): New macro.
972 (CPU_OCTEON): New macro.
973 (OPCODE_IS_MEMBER): Handle Octeon instructions.
975 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
977 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
979 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
981 * avr.h (AVR_ISA_USB162): Add new opcode set.
982 (AVR_ISA_AVR3): Likewise.
984 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
986 * mips.h (INSN_LOONGSON_2E): New.
987 (INSN_LOONGSON_2F): New.
988 (CPU_LOONGSON_2E): New.
989 (CPU_LOONGSON_2F): New.
990 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
992 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
994 * mips.h (INSN_ISA*): Redefine certain values as an
995 enumeration. Update comments.
996 (mips_isa_table): New.
997 (ISA_MIPS*): Redefine to match enumeration.
998 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1001 2007-08-08 Ben Elliston <bje@au.ibm.com>
1003 * ppc.h (PPC_OPCODE_PPCPS): New.
1005 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1007 * m68k.h: Document j K & E.
1009 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1011 * cr16.h: New file for CR16 target.
1013 2007-05-02 Alan Modra <amodra@bigpond.net.au>
1015 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1017 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1019 * m68k.h (mcfisa_c): New.
1020 (mcfusp, mcf_mask): Adjust.
1022 2007-04-20 Alan Modra <amodra@bigpond.net.au>
1024 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1025 (num_powerpc_operands): Declare.
1026 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1027 (PPC_OPERAND_PLUS1): Define.
1029 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
1031 * i386.h (REX_MODE64): Renamed to ...
1033 (REX_EXTX): Renamed to ...
1035 (REX_EXTY): Renamed to ...
1037 (REX_EXTZ): Renamed to ...
1040 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1042 * i386.h: Add entries from config/tc-i386.h and move tables
1043 to opcodes/i386-opc.h.
1045 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1047 * i386.h (FloatDR): Removed.
1048 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1050 2007-03-01 Alan Modra <amodra@bigpond.net.au>
1052 * spu-insns.h: Add soma double-float insns.
1054 2007-02-20 Thiemo Seufer <ths@mips.com>
1055 Chao-Ying Fu <fu@mips.com>
1057 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1058 (INSN_DSPR2): Add flag for DSP R2 instructions.
1059 (M_BALIGN): New macro.
1061 2007-02-14 Alan Modra <amodra@bigpond.net.au>
1063 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1064 and Seg3ShortFrom with Shortform.
1066 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1069 * i386.h (i386_optab): Put the real "test" before the pseudo
1072 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
1074 * m68k.h (m68010up): OR fido_a.
1076 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
1078 * m68k.h (fido_a): New.
1080 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
1082 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1083 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1086 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1088 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1090 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1092 * score-inst.h (enum score_insn_type): Add Insn_internal.
1094 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1095 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1096 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1097 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1098 Alan Modra <amodra@bigpond.net.au>
1100 * spu-insns.h: New file.
1103 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1105 * ppc.h (PPC_OPCODE_CELL): Define.
1107 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1109 * i386.h : Modify opcode to support for the change in POPCNT opcode
1110 in amdfam10 architecture.
1112 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1114 * i386.h: Replace CpuMNI with CpuSSSE3.
1116 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
1117 Joseph Myers <joseph@codesourcery.com>
1118 Ian Lance Taylor <ian@wasabisystems.com>
1119 Ben Elliston <bje@wasabisystems.com>
1121 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1123 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1125 * score-datadep.h: New file.
1126 * score-inst.h: New file.
1128 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1130 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1131 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1132 movdq2q and movq2dq.
1134 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1135 Michael Meissner <michael.meissner@amd.com>
1137 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1139 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1141 * i386.h (i386_optab): Add "nop" with memory reference.
1143 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1145 * i386.h (i386_optab): Update comment for 64bit NOP.
1147 2006-06-06 Ben Elliston <bje@au.ibm.com>
1148 Anton Blanchard <anton@samba.org>
1150 * ppc.h (PPC_OPCODE_POWER6): Define.
1153 2006-06-05 Thiemo Seufer <ths@mips.com>
1155 * mips.h: Improve description of MT flags.
1157 2006-05-25 Richard Sandiford <richard@codesourcery.com>
1159 * m68k.h (mcf_mask): Define.
1161 2006-05-05 Thiemo Seufer <ths@mips.com>
1162 David Ung <davidu@mips.com>
1164 * mips.h (enum): Add macro M_CACHE_AB.
1166 2006-05-04 Thiemo Seufer <ths@mips.com>
1167 Nigel Stephens <nigel@mips.com>
1168 David Ung <davidu@mips.com>
1170 * mips.h: Add INSN_SMARTMIPS define.
1172 2006-04-30 Thiemo Seufer <ths@mips.com>
1173 David Ung <davidu@mips.com>
1175 * mips.h: Defines udi bits and masks. Add description of
1176 characters which may appear in the args field of udi
1179 2006-04-26 Thiemo Seufer <ths@networkno.de>
1181 * mips.h: Improve comments describing the bitfield instruction
1184 2006-04-26 Julian Brown <julian@codesourcery.com>
1186 * arm.h (FPU_VFP_EXT_V3): Define constant.
1187 (FPU_NEON_EXT_V1): Likewise.
1188 (FPU_VFP_HARD): Update.
1189 (FPU_VFP_V3): Define macro.
1190 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1192 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
1194 * avr.h (AVR_ISA_PWMx): New.
1196 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1198 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1199 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1200 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1201 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1202 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1204 2006-03-10 Paul Brook <paul@codesourcery.com>
1206 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1208 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1210 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1211 first. Correct mask of bb "B" opcode.
1213 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1215 * i386.h (i386_optab): Support Intel Merom New Instructions.
1217 2006-02-24 Paul Brook <paul@codesourcery.com>
1219 * arm.h: Add V7 feature bits.
1221 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1223 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1225 2006-01-31 Paul Brook <paul@codesourcery.com>
1226 Richard Earnshaw <rearnsha@arm.com>
1228 * arm.h: Use ARM_CPU_FEATURE.
1229 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1230 (arm_feature_set): Change to a structure.
1231 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1232 ARM_FEATURE): New macros.
1234 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
1236 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1237 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1238 (ADD_PC_INCR_OPCODE): Don't define.
1240 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1243 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1245 2005-11-14 David Ung <davidu@mips.com>
1247 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1248 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1249 save/restore encoding of the args field.
1251 2005-10-28 Dave Brolley <brolley@redhat.com>
1253 Contribute the following changes:
1254 2005-02-16 Dave Brolley <brolley@redhat.com>
1256 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1257 cgen_isa_mask_* to cgen_bitset_*.
1260 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1262 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1263 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1264 (CGEN_CPU_TABLE): Make isas a ponter.
1266 2003-09-29 Dave Brolley <brolley@redhat.com>
1268 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1269 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1270 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1272 2002-12-13 Dave Brolley <brolley@redhat.com>
1274 * cgen.h (symcat.h): #include it.
1275 (cgen-bitset.h): #include it.
1276 (CGEN_ATTR_VALUE_TYPE): Now a union.
1277 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1278 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1279 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1280 * cgen-bitset.h: New file.
1282 2005-09-30 Catherine Moore <clm@cm00re.com>
1286 2005-10-24 Jan Beulich <jbeulich@novell.com>
1288 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1291 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1293 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1294 Add FLAG_STRICT to pa10 ftest opcode.
1296 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1298 * hppa.h (pa_opcodes): Remove lha entries.
1300 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1302 * hppa.h (FLAG_STRICT): Revise comment.
1303 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1304 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1307 2005-09-30 Catherine Moore <clm@cm00re.com>
1311 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1313 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1315 2005-09-06 Chao-ying Fu <fu@mips.com>
1317 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1318 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1320 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1321 (INSN_ASE_MASK): Update to include INSN_MT.
1322 (INSN_MT): New define for MT ASE.
1324 2005-08-25 Chao-ying Fu <fu@mips.com>
1326 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1327 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1328 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1329 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1330 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1331 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1333 (INSN_DSP): New define for DSP ASE.
1335 2005-08-18 Alan Modra <amodra@bigpond.net.au>
1339 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1341 * ppc.h (PPC_OPCODE_E300): Define.
1343 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1345 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1347 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1350 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1353 2005-07-27 Jan Beulich <jbeulich@novell.com>
1355 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1356 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1357 Add movq-s as 64-bit variants of movd-s.
1359 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1361 * hppa.h: Fix punctuation in comment.
1363 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1364 implicit space-register addressing. Set space-register bits on opcodes
1365 using implicit space-register addressing. Add various missing pa20
1366 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1367 space-register addressing. Use "fE" instead of "fe" in various
1370 2005-07-18 Jan Beulich <jbeulich@novell.com>
1372 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1374 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1376 * i386.h (i386_optab): Support Intel VMX Instructions.
1378 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1380 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1382 2005-07-05 Jan Beulich <jbeulich@novell.com>
1384 * i386.h (i386_optab): Add new insns.
1386 2005-07-01 Nick Clifton <nickc@redhat.com>
1388 * sparc.h: Add typedefs to structure declarations.
1390 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1393 * i386.h (i386_optab): Update comments for 64bit addressing on
1394 mov. Allow 64bit addressing for mov and movq.
1396 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1398 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1399 respectively, in various floating-point load and store patterns.
1401 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1403 * hppa.h (FLAG_STRICT): Correct comment.
1404 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1405 PA 2.0 mneumonics when equivalent. Entries with cache control
1406 completers now require PA 1.1. Adjust whitespace.
1408 2005-05-19 Anton Blanchard <anton@samba.org>
1410 * ppc.h (PPC_OPCODE_POWER5): Define.
1412 2005-05-10 Nick Clifton <nickc@redhat.com>
1414 * Update the address and phone number of the FSF organization in
1415 the GPL notices in the following files:
1416 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1417 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1418 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1419 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1420 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1421 tic54x.h, tic80.h, v850.h, vax.h
1423 2005-05-09 Jan Beulich <jbeulich@novell.com>
1425 * i386.h (i386_optab): Add ht and hnt.
1427 2005-04-18 Mark Kettenis <kettenis@gnu.org>
1429 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1430 Add xcrypt-ctr. Provide aliases without hyphens.
1432 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1434 Moved from ../ChangeLog
1436 2005-04-12 Paul Brook <paul@codesourcery.com>
1437 * m88k.h: Rename psr macros to avoid conflicts.
1439 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1440 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1441 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1442 and ARM_ARCH_V6ZKT2.
1444 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1445 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1446 Remove redundant instruction types.
1447 (struct argument): X_op - new field.
1448 (struct cst4_entry): Remove.
1449 (no_op_insn): Declare.
1451 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1452 * crx.h (enum argtype): Rename types, remove unused types.
1454 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1455 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1456 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1457 (enum operand_type): Rearrange operands, edit comments.
1458 replace us<N> with ui<N> for unsigned immediate.
1459 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1460 displacements (respectively).
1461 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1462 (instruction type): Add NO_TYPE_INS.
1463 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1464 (operand_entry): New field - 'flags'.
1465 (operand flags): New.
1467 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1468 * crx.h (operand_type): Remove redundant types i3, i4,
1470 Add new unsigned immediate types us3, us4, us5, us16.
1472 2005-04-12 Mark Kettenis <kettenis@gnu.org>
1474 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1475 adjust them accordingly.
1477 2005-04-01 Jan Beulich <jbeulich@novell.com>
1479 * i386.h (i386_optab): Add rdtscp.
1481 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1483 * i386.h (i386_optab): Don't allow the `l' suffix for moving
1484 between memory and segment register. Allow movq for moving between
1485 general-purpose register and segment register.
1487 2005-02-09 Jan Beulich <jbeulich@novell.com>
1490 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1491 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1494 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1496 * m68k.h (m68008, m68ec030, m68882): Remove.
1498 (cpu_m68k, cpu_cf): New.
1499 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1500 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1502 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
1504 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1505 * cgen.h (enum cgen_parse_operand_type): Add
1506 CGEN_PARSE_OPERAND_SYMBOLIC.
1508 2005-01-21 Fred Fish <fnf@specifixinc.com>
1510 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1511 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1512 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1514 2005-01-19 Fred Fish <fnf@specifixinc.com>
1516 * mips.h (struct mips_opcode): Add new pinfo2 member.
1517 (INSN_ALIAS): New define for opcode table entries that are
1518 specific instances of another entry, such as 'move' for an 'or'
1519 with a zero operand.
1520 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1521 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1523 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1525 * mips.h (CPU_RM9000): Define.
1526 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1528 2004-11-25 Jan Beulich <jbeulich@novell.com>
1530 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1531 to/from test registers are illegal in 64-bit mode. Add missing
1532 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1533 (previously one had to explicitly encode a rex64 prefix). Re-enable
1534 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1535 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1537 2004-11-23 Jan Beulich <jbeulich@novell.com>
1539 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1540 available only with SSE2. Change the MMX additions introduced by SSE
1541 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1542 instructions by their now designated identifier (since combining i686
1543 and 3DNow! does not really imply 3DNow!A).
1545 2004-11-19 Alan Modra <amodra@bigpond.net.au>
1547 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1548 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1550 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1551 Vineet Sharma <vineets@noida.hcltech.com>
1553 * maxq.h: New file: Disassembly information for the maxq port.
1555 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1557 * i386.h (i386_optab): Put back "movzb".
1559 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
1561 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1562 comments. Remove member cris_ver_sim. Add members
1563 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1564 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1565 (struct cris_support_reg, struct cris_cond15): New types.
1566 (cris_conds15): Declare.
1567 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1568 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1569 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1570 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1571 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1572 SIZE_FIELD_UNSIGNED.
1574 2004-11-04 Jan Beulich <jbeulich@novell.com>
1576 * i386.h (sldx_Suf): Remove.
1577 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1578 (q_FP): Define, implying no REX64.
1579 (x_FP, sl_FP): Imply FloatMF.
1580 (i386_optab): Split reg and mem forms of moving from segment registers
1581 so that the memory forms can ignore the 16-/32-bit operand size
1582 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1583 all non-floating-point instructions. Unite 32- and 64-bit forms of
1584 movsx, movzx, and movd. Adjust floating point operations for the above
1585 changes to the *FP macros. Add DefaultSize to floating point control
1586 insns operating on larger memory ranges. Remove left over comments
1587 hinting at certain insns being Intel-syntax ones where the ones
1588 actually meant are already gone.
1590 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1592 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1595 2004-09-30 Paul Brook <paul@codesourcery.com>
1597 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1598 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1600 2004-09-11 Theodore A. Roth <troth@openavr.org>
1602 * avr.h: Add support for
1603 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1605 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1607 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1609 2004-08-24 Dmitry Diky <diwil@spec.ru>
1611 * msp430.h (msp430_opc): Add new instructions.
1612 (msp430_rcodes): Declare new instructions.
1613 (msp430_hcodes): Likewise..
1615 2004-08-13 Nick Clifton <nickc@redhat.com>
1618 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1621 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1623 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1625 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1627 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1629 2004-07-21 Jan Beulich <jbeulich@novell.com>
1631 * i386.h: Adjust instruction descriptions to better match the
1634 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
1636 * arm.h: Remove all old content. Replace with architecture defines
1637 from gas/config/tc-arm.c.
1639 2004-07-09 Andreas Schwab <schwab@suse.de>
1641 * m68k.h: Fix comment.
1643 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1647 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1649 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1651 2004-05-24 Peter Barada <peter@the-baradas.com>
1653 * m68k.h: Add 'size' to m68k_opcode.
1655 2004-05-05 Peter Barada <peter@the-baradas.com>
1657 * m68k.h: Switch from ColdFire chip name to core variant.
1659 2004-04-22 Peter Barada <peter@the-baradas.com>
1661 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1662 descriptions for new EMAC cases.
1663 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1664 handle Motorola MAC syntax.
1665 Allow disassembly of ColdFire V4e object files.
1667 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1669 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1671 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1673 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1675 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1677 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1679 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1681 * i386.h (i386_optab): Added xstore/xcrypt insns.
1683 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1685 * h8300.h (32bit ldc/stc): Add relaxing support.
1687 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1689 * h8300.h (BITOP): Pass MEMRELAX flag.
1691 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1693 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1696 For older changes see ChangeLog-9103
1698 Copyright (C) 2004-2012 Free Software Foundation, Inc.
1700 Copying and distribution of this file, with or without modification,
1701 are permitted in any medium without royalty provided the copyright
1702 notice and this notice are preserved.
1708 version-control: never