1 2013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
4 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
6 2013-01-24 Nick Clifton <nickc@redhat.com>
8 * v850.h: Add e3v5 support.
10 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
12 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
14 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
16 * ppc.h (PPC_OPCODE_POWER8): New define.
17 (PPC_OPCODE_HTM): Likewise.
19 2013-01-10 Will Newton <will.newton@imgtec.com>
23 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
25 * cr16.h (make_instruction): Rename to cr16_make_instruction.
26 (match_opcode): Rename to cr16_match_opcode.
28 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
30 * mips.h: Add support for r5900 instructions including lq and sq.
32 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
34 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
35 (make_instruction,match_opcode): Added function prototypes.
36 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
38 2012-11-23 Alan Modra <amodra@gmail.com>
40 * ppc.h (ppc_parse_cpu): Update prototype.
42 2012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
44 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
45 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
47 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
49 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
51 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
53 * ia64.h (ia64_opnd): Add new operand types.
55 2012-08-21 David S. Miller <davem@davemloft.net>
57 * sparc.h (F3F4): New macro.
59 2012-08-13 Ian Bolton <ian.bolton@arm.com>
60 Laurent Desnogues <laurent.desnogues@arm.com>
61 Jim MacArthur <jim.macarthur@arm.com>
62 Marcus Shawcroft <marcus.shawcroft@arm.com>
63 Nigel Stephens <nigel.stephens@arm.com>
64 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
65 Richard Earnshaw <rearnsha@arm.com>
66 Sofiane Naci <sofiane.naci@arm.com>
67 Tejas Belagod <tejas.belagod@arm.com>
68 Yufeng Zhang <yufeng.zhang@arm.com>
70 * aarch64.h: New file.
72 2012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
73 Maciej W. Rozycki <macro@codesourcery.com>
75 * mips.h (mips_opcode): Add the exclusions field.
76 (OPCODE_IS_MEMBER): Remove macro.
77 (cpu_is_member): New inline function.
78 (opcode_is_member): Likewise.
80 2012-07-31 Chao-Ying Fu <fu@mips.com>
81 Catherine Moore <clm@codesourcery.com>
82 Maciej W. Rozycki <macro@codesourcery.com>
84 * mips.h: Document microMIPS DSP ASE usage.
85 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
86 microMIPS DSP ASE support.
87 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
88 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
89 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
90 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
91 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
92 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
93 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
95 2012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
97 * mips.h: Fix a typo in description.
99 2012-06-07 Georg-Johann Lay <avr@gjlay.de>
101 * avr.h: (AVR_ISA_XCH): New define.
102 (AVR_ISA_XMEGA): Use it.
103 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
105 2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
107 * m68hc11.h: Add XGate definitions.
108 (struct m68hc11_opcode): Add xg_mask field.
110 2012-05-14 Catherine Moore <clm@codesourcery.com>
111 Maciej W. Rozycki <macro@codesourcery.com>
112 Rhonda Wittels <rhonda@codesourcery.com>
114 * ppc.h (PPC_OPCODE_VLE): New definition.
115 (PPC_OP_SA): New macro.
116 (PPC_OP_SE_VLE): New macro.
117 (PPC_OP): Use a variable shift amount.
118 (powerpc_operand): Update comments.
119 (PPC_OPSHIFT_INV): New macro.
120 (PPC_OPERAND_CR): Replace with...
121 (PPC_OPERAND_CR_BIT): ...this and
122 (PPC_OPERAND_CR_REG): ...this.
125 2012-05-03 Sean Keys <skeys@ipdatasys.com>
127 * xgate.h: Header file for XGATE assembler.
129 2012-04-27 David S. Miller <davem@davemloft.net>
131 * sparc.h: Document new arg code' )' for crypto RS3
134 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
135 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
136 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
137 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
138 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
139 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
140 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
141 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
142 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
143 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
144 HWCAP_CBCOND, HWCAP_CRC32): New defines.
146 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
148 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
150 2012-02-27 Alan Modra <amodra@gmail.com>
152 * crx.h (cst4_map): Update declaration.
154 2012-02-25 Walter Lee <walt@tilera.com>
156 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
158 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
159 TILEPRO_OPC_LW_TLS_SN.
161 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
163 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
164 (XRELEASE_PREFIX_OPCODE): Likewise.
166 2011-12-08 Andrew Pinski <apinski@cavium.com>
167 Adam Nemet <anemet@caviumnetworks.com>
169 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
170 (INSN_OCTEON2): New macro.
171 (CPU_OCTEON2): New macro.
172 (OPCODE_IS_MEMBER): Add Octeon2.
174 2011-11-29 Andrew Pinski <apinski@cavium.com>
176 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
177 (INSN_OCTEONP): New macro.
178 (CPU_OCTEONP): New macro.
179 (OPCODE_IS_MEMBER): Add Octeon+.
180 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
182 2011-11-01 DJ Delorie <dj@redhat.com>
186 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
188 * mips.h: Fix a typo in description.
190 2011-09-21 David S. Miller <davem@davemloft.net>
192 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
193 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
194 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
195 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
197 2011-08-09 Chao-ying Fu <fu@mips.com>
198 Maciej W. Rozycki <macro@codesourcery.com>
200 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
201 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
202 (INSN_ASE_MASK): Add the MCU bit.
203 (INSN_MCU): New macro.
204 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
205 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
207 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
209 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
210 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
211 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
212 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
213 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
214 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
215 (INSN2_READ_GPR_MMN): Likewise.
216 (INSN2_READ_FPR_D): Change the bit used.
217 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
218 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
219 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
220 (INSN2_COND_BRANCH): Likewise.
221 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
222 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
223 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
224 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
225 (INSN2_MOD_GPR_MN): Likewise.
227 2011-08-05 David S. Miller <davem@davemloft.net>
229 * sparc.h: Document new format codes '4', '5', and '('.
230 (OPF_LOW4, RS3): New macros.
232 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
234 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
235 order of flags documented.
237 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
239 * mips.h: Clarify the description of microMIPS instruction
241 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
243 2011-07-24 Chao-ying Fu <fu@mips.com>
244 Maciej W. Rozycki <macro@codesourcery.com>
246 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
247 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
248 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
249 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
250 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
251 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
252 (OP_MASK_RS3, OP_SH_RS3): Likewise.
253 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
254 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
255 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
256 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
257 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
258 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
259 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
260 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
261 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
262 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
263 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
264 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
265 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
266 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
267 (INSN_WRITE_GPR_S): New macro.
268 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
269 (INSN2_READ_FPR_D): Likewise.
270 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
271 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
272 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
273 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
274 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
275 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
276 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
277 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
278 (CPU_MICROMIPS): New macro.
279 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
280 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
281 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
282 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
283 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
284 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
285 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
286 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
287 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
288 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
289 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
290 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
291 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
292 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
293 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
294 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
295 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
296 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
297 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
298 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
299 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
300 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
301 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
302 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
303 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
304 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
305 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
306 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
307 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
308 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
309 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
310 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
311 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
312 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
313 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
314 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
315 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
316 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
317 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
318 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
319 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
320 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
321 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
322 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
323 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
324 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
325 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
326 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
327 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
328 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
329 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
330 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
331 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
332 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
333 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
334 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
335 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
336 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
337 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
338 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
339 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
340 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
341 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
342 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
343 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
344 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
345 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
346 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
347 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
348 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
349 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
350 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
351 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
352 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
353 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
354 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
355 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
356 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
357 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
358 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
359 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
360 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
361 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
362 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
363 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
364 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
365 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
366 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
367 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
368 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
369 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
370 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
371 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
372 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
373 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
374 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
375 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
376 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
377 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
378 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
379 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
380 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
381 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
382 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
383 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
384 (micromips_opcodes): New declaration.
385 (bfd_micromips_num_opcodes): Likewise.
387 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
389 * mips.h (INSN_TRAP): Rename to...
390 (INSN_NO_DELAY_SLOT): ... this.
391 (INSN_SYNC): Remove macro.
393 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
395 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
396 a duplicate of AVR_ISA_SPM.
398 2011-07-01 Nick Clifton <nickc@redhat.com>
400 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
402 2011-06-18 Robin Getz <robin.getz@analog.com>
404 * bfin.h (is_macmod_signed): New func
406 2011-06-18 Mike Frysinger <vapier@gentoo.org>
408 * bfin.h (is_macmod_pmove): Add missing space before func args.
409 (is_macmod_hmove): Likewise.
411 2011-06-13 Walter Lee <walt@tilera.com>
413 * tilegx.h: New file.
414 * tilepro.h: New file.
416 2011-05-31 Paul Brook <paul@codesourcery.com>
418 * arm.h (ARM_ARCH_V7R_IDIV): Define.
420 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
422 * s390.h: Replace S390_OPERAND_REG_EVEN with
423 S390_OPERAND_REG_PAIR.
425 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
427 * s390.h: Add S390_OPCODE_REG_EVEN flag.
429 2011-04-18 Julian Brown <julian@codesourcery.com>
431 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
433 2011-04-11 Dan McDonald <dan@wellkeeper.com>
436 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
438 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
440 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
441 New instruction set flags.
442 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
444 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
446 * mips.h (M_PREF_AB): New enum value.
448 2011-02-12 Mike Frysinger <vapier@gentoo.org>
450 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
452 (is_macmod_pmove, is_macmod_hmove): New functions.
454 2011-02-11 Mike Frysinger <vapier@gentoo.org>
456 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
458 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
460 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
461 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
463 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
466 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
469 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
472 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
474 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
476 * mips.h: Update commentary after last commit.
478 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
480 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
481 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
482 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
484 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
486 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
488 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
490 * mips.h: Fix previous commit.
492 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
494 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
495 (INSN_LOONGSON_3A): Clear bit 31.
497 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
500 * arm.h (ARM_AEXT_V6M_ONLY): New define.
501 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
502 (ARM_ARCH_V6M_ONLY): New define.
504 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
506 * mips.h (INSN_LOONGSON_3A): Defined.
507 (CPU_LOONGSON_3A): Defined.
508 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
510 2010-10-09 Matt Rice <ratmice@gmail.com>
512 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
513 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
515 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
517 * arm.h (ARM_EXT_VIRT): New define.
518 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
519 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
522 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
524 * arm.h (ARM_AEXT_ADIV): New define.
525 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
527 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
529 * arm.h (ARM_EXT_OS): New define.
530 (ARM_AEXT_V6SM): Likewise.
531 (ARM_ARCH_V6SM): Likewise.
533 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
535 * arm.h (ARM_EXT_MP): Add.
536 (ARM_ARCH_V7A_MP): Likewise.
538 2010-09-22 Mike Frysinger <vapier@gentoo.org>
540 * bfin.h: Declare pseudoChr structs/defines.
542 2010-09-21 Mike Frysinger <vapier@gentoo.org>
544 * bfin.h: Strip trailing whitespace.
546 2010-07-29 DJ Delorie <dj@redhat.com>
548 * rx.h (RX_Operand_Type): Add TwoReg.
549 (RX_Opcode_ID): Remove ediv and ediv2.
551 2010-07-27 DJ Delorie <dj@redhat.com>
553 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
555 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
556 Ina Pandit <ina.pandit@kpitcummins.com>
558 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
559 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
560 PROCESSOR_V850E2_ALL.
561 Remove PROCESSOR_V850EA support.
562 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
563 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
564 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
565 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
566 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
567 V850_OPERAND_PERCENT.
568 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
570 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
573 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
575 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
576 (MIPS16_INSN_BRANCH): Rename to...
577 (MIPS16_INSN_COND_BRANCH): ... this.
579 2010-07-03 Alan Modra <amodra@gmail.com>
581 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
582 Renumber other PPC_OPCODE defines.
584 2010-07-03 Alan Modra <amodra@gmail.com>
586 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
588 2010-06-29 Alan Modra <amodra@gmail.com>
590 * maxq.h: Delete file.
592 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
594 * ppc.h (PPC_OPCODE_E500): Define.
596 2010-05-26 Catherine Moore <clm@codesourcery.com>
598 * opcode/mips.h (INSN_MIPS16): Remove.
600 2010-04-21 Joseph Myers <joseph@codesourcery.com>
602 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
604 2010-04-15 Nick Clifton <nickc@redhat.com>
606 * alpha.h: Update copyright notice to use GPLv3.
612 * convex.h: Likewise.
626 * m68hc11.h: Likewise.
632 * mn10200.h: Likewise.
633 * mn10300.h: Likewise.
634 * msp430.h: Likewise.
645 * score-datadep.h: Likewise.
646 * score-inst.h: Likewise.
648 * spu-insns.h: Likewise.
652 * tic54x.h: Likewise.
657 2010-03-25 Joseph Myers <joseph@codesourcery.com>
659 * tic6x-control-registers.h, tic6x-insn-formats.h,
660 tic6x-opcode-table.h, tic6x.h: New.
662 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
664 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
666 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
668 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
670 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
672 * ia64.h (ia64_find_opcode): Remove argument name.
673 (ia64_find_next_opcode): Likewise.
674 (ia64_dis_opcode): Likewise.
675 (ia64_free_opcode): Likewise.
676 (ia64_find_dependency): Likewise.
678 2009-11-22 Doug Evans <dje@sebabeach.org>
680 * cgen.h: Include bfd_stdint.h.
681 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
683 2009-11-18 Paul Brook <paul@codesourcery.com>
685 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
687 2009-11-17 Paul Brook <paul@codesourcery.com>
688 Daniel Jacobowitz <dan@codesourcery.com>
690 * arm.h (ARM_EXT_V6_DSP): Define.
691 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
692 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
694 2009-11-04 DJ Delorie <dj@redhat.com>
696 * rx.h (rx_decode_opcode) (mvtipl): Add.
697 (mvtcp, mvfcp, opecp): Remove.
699 2009-11-02 Paul Brook <paul@codesourcery.com>
701 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
702 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
703 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
704 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
705 FPU_ARCH_NEON_VFP_V4): Define.
707 2009-10-23 Doug Evans <dje@sebabeach.org>
709 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
710 * cgen.h: Update. Improve multi-inclusion macro name.
712 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
714 * ppc.h (PPC_OPCODE_476): Define.
716 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
718 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
720 2009-09-29 DJ Delorie <dj@redhat.com>
724 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
726 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
728 2009-09-21 Ben Elliston <bje@au.ibm.com>
730 * ppc.h (PPC_OPCODE_PPCA2): New.
732 2009-09-05 Martin Thuresson <martin@mtme.org>
734 * ia64.h (struct ia64_operand): Renamed member class to op_class.
736 2009-08-29 Martin Thuresson <martin@mtme.org>
738 * tic30.h (template): Rename type template to
739 insn_template. Updated code to use new name.
740 * tic54x.h (template): Rename type template to
743 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
745 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
747 2009-06-11 Anthony Green <green@moxielogic.com>
749 * moxie.h (MOXIE_F3_PCREL): Define.
750 (moxie_form3_opc_info): Grow.
752 2009-06-06 Anthony Green <green@moxielogic.com>
754 * moxie.h (MOXIE_F1_M): Define.
756 2009-04-15 Anthony Green <green@moxielogic.com>
760 2009-04-06 DJ Delorie <dj@redhat.com>
762 * h8300.h: Add relaxation attributes to MOVA opcodes.
764 2009-03-10 Alan Modra <amodra@bigpond.net.au>
766 * ppc.h (ppc_parse_cpu): Declare.
768 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
770 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
771 and _IMM11 for mbitclr and mbitset.
772 * score-datadep.h: Update dependency information.
774 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
776 * ppc.h (PPC_OPCODE_POWER7): New.
778 2009-02-06 Doug Evans <dje@google.com>
780 * i386.h: Add comment regarding sse* insns and prefixes.
782 2009-02-03 Sandip Matte <sandip@rmicorp.com>
784 * mips.h (INSN_XLR): Define.
785 (INSN_CHIP_MASK): Update.
787 (OPCODE_IS_MEMBER): Update.
788 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
790 2009-01-28 Doug Evans <dje@google.com>
792 * opcode/i386.h: Add multiple inclusion protection.
793 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
794 (EDI_REG_NUM): New macros.
795 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
796 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
797 (REX_PREFIX_P): New macro.
799 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
801 * ppc.h (struct powerpc_opcode): New field "deprecated".
802 (PPC_OPCODE_NOPOWER4): Delete.
804 2008-11-28 Joshua Kinard <kumba@gentoo.org>
806 * mips.h: Define CPU_R14000, CPU_R16000.
807 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
809 2008-11-18 Catherine Moore <clm@codesourcery.com>
811 * arm.h (FPU_NEON_FP16): New.
812 (FPU_ARCH_NEON_FP16): New.
814 2008-11-06 Chao-ying Fu <fu@mips.com>
816 * mips.h: Doucument '1' for 5-bit sync type.
818 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
820 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
823 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
825 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
827 2008-07-30 Michael J. Eager <eager@eagercon.com>
829 * ppc.h (PPC_OPCODE_405): Define.
830 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
832 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
834 * ppc.h (ppc_cpu_t): New typedef.
835 (struct powerpc_opcode <flags>): Use it.
836 (struct powerpc_operand <insert, extract>): Likewise.
837 (struct powerpc_macro <flags>): Likewise.
839 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
841 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
842 Update comment before MIPS16 field descriptors to mention MIPS16.
843 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
845 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
846 New bit masks and shift counts for cins and exts.
848 * mips.h: Document new field descriptors +Q.
849 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
851 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
853 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
854 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
856 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
858 * ppc.h: (PPC_OPCODE_E500MC): New.
860 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
862 * i386.h (MAX_OPERANDS): Set to 5.
863 (MAX_MNEM_SIZE): Changed to 20.
865 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
867 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
869 2008-03-09 Paul Brook <paul@codesourcery.com>
871 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
873 2008-03-04 Paul Brook <paul@codesourcery.com>
875 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
876 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
877 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
879 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
880 Nick Clifton <nickc@redhat.com>
883 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
884 with a 32-bit displacement but without the top bit of the 4th byte
887 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
889 * cr16.h (cr16_num_optab): Declared.
891 2008-02-14 Hakan Ardo <hakan@debian.org>
894 * avr.h (AVR_ISA_2xxe): Define.
896 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
898 * mips.h: Update copyright.
899 (INSN_CHIP_MASK): New macro.
900 (INSN_OCTEON): New macro.
901 (CPU_OCTEON): New macro.
902 (OPCODE_IS_MEMBER): Handle Octeon instructions.
904 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
906 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
908 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
910 * avr.h (AVR_ISA_USB162): Add new opcode set.
911 (AVR_ISA_AVR3): Likewise.
913 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
915 * mips.h (INSN_LOONGSON_2E): New.
916 (INSN_LOONGSON_2F): New.
917 (CPU_LOONGSON_2E): New.
918 (CPU_LOONGSON_2F): New.
919 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
921 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
923 * mips.h (INSN_ISA*): Redefine certain values as an
924 enumeration. Update comments.
925 (mips_isa_table): New.
926 (ISA_MIPS*): Redefine to match enumeration.
927 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
930 2007-08-08 Ben Elliston <bje@au.ibm.com>
932 * ppc.h (PPC_OPCODE_PPCPS): New.
934 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
936 * m68k.h: Document j K & E.
938 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
940 * cr16.h: New file for CR16 target.
942 2007-05-02 Alan Modra <amodra@bigpond.net.au>
944 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
946 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
948 * m68k.h (mcfisa_c): New.
949 (mcfusp, mcf_mask): Adjust.
951 2007-04-20 Alan Modra <amodra@bigpond.net.au>
953 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
954 (num_powerpc_operands): Declare.
955 (PPC_OPERAND_SIGNED et al): Redefine as hex.
956 (PPC_OPERAND_PLUS1): Define.
958 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
960 * i386.h (REX_MODE64): Renamed to ...
962 (REX_EXTX): Renamed to ...
964 (REX_EXTY): Renamed to ...
966 (REX_EXTZ): Renamed to ...
969 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
971 * i386.h: Add entries from config/tc-i386.h and move tables
972 to opcodes/i386-opc.h.
974 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
976 * i386.h (FloatDR): Removed.
977 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
979 2007-03-01 Alan Modra <amodra@bigpond.net.au>
981 * spu-insns.h: Add soma double-float insns.
983 2007-02-20 Thiemo Seufer <ths@mips.com>
984 Chao-Ying Fu <fu@mips.com>
986 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
987 (INSN_DSPR2): Add flag for DSP R2 instructions.
988 (M_BALIGN): New macro.
990 2007-02-14 Alan Modra <amodra@bigpond.net.au>
992 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
993 and Seg3ShortFrom with Shortform.
995 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
998 * i386.h (i386_optab): Put the real "test" before the pseudo
1001 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
1003 * m68k.h (m68010up): OR fido_a.
1005 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
1007 * m68k.h (fido_a): New.
1009 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
1011 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1012 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1015 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1017 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1019 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1021 * score-inst.h (enum score_insn_type): Add Insn_internal.
1023 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1024 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1025 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1026 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1027 Alan Modra <amodra@bigpond.net.au>
1029 * spu-insns.h: New file.
1032 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1034 * ppc.h (PPC_OPCODE_CELL): Define.
1036 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1038 * i386.h : Modify opcode to support for the change in POPCNT opcode
1039 in amdfam10 architecture.
1041 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1043 * i386.h: Replace CpuMNI with CpuSSSE3.
1045 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
1046 Joseph Myers <joseph@codesourcery.com>
1047 Ian Lance Taylor <ian@wasabisystems.com>
1048 Ben Elliston <bje@wasabisystems.com>
1050 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1052 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1054 * score-datadep.h: New file.
1055 * score-inst.h: New file.
1057 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1059 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1060 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1061 movdq2q and movq2dq.
1063 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1064 Michael Meissner <michael.meissner@amd.com>
1066 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1068 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1070 * i386.h (i386_optab): Add "nop" with memory reference.
1072 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1074 * i386.h (i386_optab): Update comment for 64bit NOP.
1076 2006-06-06 Ben Elliston <bje@au.ibm.com>
1077 Anton Blanchard <anton@samba.org>
1079 * ppc.h (PPC_OPCODE_POWER6): Define.
1082 2006-06-05 Thiemo Seufer <ths@mips.com>
1084 * mips.h: Improve description of MT flags.
1086 2006-05-25 Richard Sandiford <richard@codesourcery.com>
1088 * m68k.h (mcf_mask): Define.
1090 2006-05-05 Thiemo Seufer <ths@mips.com>
1091 David Ung <davidu@mips.com>
1093 * mips.h (enum): Add macro M_CACHE_AB.
1095 2006-05-04 Thiemo Seufer <ths@mips.com>
1096 Nigel Stephens <nigel@mips.com>
1097 David Ung <davidu@mips.com>
1099 * mips.h: Add INSN_SMARTMIPS define.
1101 2006-04-30 Thiemo Seufer <ths@mips.com>
1102 David Ung <davidu@mips.com>
1104 * mips.h: Defines udi bits and masks. Add description of
1105 characters which may appear in the args field of udi
1108 2006-04-26 Thiemo Seufer <ths@networkno.de>
1110 * mips.h: Improve comments describing the bitfield instruction
1113 2006-04-26 Julian Brown <julian@codesourcery.com>
1115 * arm.h (FPU_VFP_EXT_V3): Define constant.
1116 (FPU_NEON_EXT_V1): Likewise.
1117 (FPU_VFP_HARD): Update.
1118 (FPU_VFP_V3): Define macro.
1119 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1121 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
1123 * avr.h (AVR_ISA_PWMx): New.
1125 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1127 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1128 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1129 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1130 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1131 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1133 2006-03-10 Paul Brook <paul@codesourcery.com>
1135 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1137 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1139 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1140 first. Correct mask of bb "B" opcode.
1142 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1144 * i386.h (i386_optab): Support Intel Merom New Instructions.
1146 2006-02-24 Paul Brook <paul@codesourcery.com>
1148 * arm.h: Add V7 feature bits.
1150 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1152 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1154 2006-01-31 Paul Brook <paul@codesourcery.com>
1155 Richard Earnshaw <rearnsha@arm.com>
1157 * arm.h: Use ARM_CPU_FEATURE.
1158 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1159 (arm_feature_set): Change to a structure.
1160 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1161 ARM_FEATURE): New macros.
1163 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
1165 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1166 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1167 (ADD_PC_INCR_OPCODE): Don't define.
1169 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1172 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1174 2005-11-14 David Ung <davidu@mips.com>
1176 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1177 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1178 save/restore encoding of the args field.
1180 2005-10-28 Dave Brolley <brolley@redhat.com>
1182 Contribute the following changes:
1183 2005-02-16 Dave Brolley <brolley@redhat.com>
1185 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1186 cgen_isa_mask_* to cgen_bitset_*.
1189 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1191 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1192 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1193 (CGEN_CPU_TABLE): Make isas a ponter.
1195 2003-09-29 Dave Brolley <brolley@redhat.com>
1197 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1198 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1199 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1201 2002-12-13 Dave Brolley <brolley@redhat.com>
1203 * cgen.h (symcat.h): #include it.
1204 (cgen-bitset.h): #include it.
1205 (CGEN_ATTR_VALUE_TYPE): Now a union.
1206 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1207 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1208 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1209 * cgen-bitset.h: New file.
1211 2005-09-30 Catherine Moore <clm@cm00re.com>
1215 2005-10-24 Jan Beulich <jbeulich@novell.com>
1217 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1220 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1222 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1223 Add FLAG_STRICT to pa10 ftest opcode.
1225 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1227 * hppa.h (pa_opcodes): Remove lha entries.
1229 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1231 * hppa.h (FLAG_STRICT): Revise comment.
1232 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1233 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1236 2005-09-30 Catherine Moore <clm@cm00re.com>
1240 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1242 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1244 2005-09-06 Chao-ying Fu <fu@mips.com>
1246 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1247 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1249 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1250 (INSN_ASE_MASK): Update to include INSN_MT.
1251 (INSN_MT): New define for MT ASE.
1253 2005-08-25 Chao-ying Fu <fu@mips.com>
1255 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1256 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1257 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1258 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1259 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1260 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1262 (INSN_DSP): New define for DSP ASE.
1264 2005-08-18 Alan Modra <amodra@bigpond.net.au>
1268 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1270 * ppc.h (PPC_OPCODE_E300): Define.
1272 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1274 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1276 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1279 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1282 2005-07-27 Jan Beulich <jbeulich@novell.com>
1284 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1285 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1286 Add movq-s as 64-bit variants of movd-s.
1288 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1290 * hppa.h: Fix punctuation in comment.
1292 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1293 implicit space-register addressing. Set space-register bits on opcodes
1294 using implicit space-register addressing. Add various missing pa20
1295 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1296 space-register addressing. Use "fE" instead of "fe" in various
1299 2005-07-18 Jan Beulich <jbeulich@novell.com>
1301 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1303 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1305 * i386.h (i386_optab): Support Intel VMX Instructions.
1307 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1309 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1311 2005-07-05 Jan Beulich <jbeulich@novell.com>
1313 * i386.h (i386_optab): Add new insns.
1315 2005-07-01 Nick Clifton <nickc@redhat.com>
1317 * sparc.h: Add typedefs to structure declarations.
1319 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1322 * i386.h (i386_optab): Update comments for 64bit addressing on
1323 mov. Allow 64bit addressing for mov and movq.
1325 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1327 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1328 respectively, in various floating-point load and store patterns.
1330 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1332 * hppa.h (FLAG_STRICT): Correct comment.
1333 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1334 PA 2.0 mneumonics when equivalent. Entries with cache control
1335 completers now require PA 1.1. Adjust whitespace.
1337 2005-05-19 Anton Blanchard <anton@samba.org>
1339 * ppc.h (PPC_OPCODE_POWER5): Define.
1341 2005-05-10 Nick Clifton <nickc@redhat.com>
1343 * Update the address and phone number of the FSF organization in
1344 the GPL notices in the following files:
1345 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1346 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1347 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1348 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1349 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1350 tic54x.h, tic80.h, v850.h, vax.h
1352 2005-05-09 Jan Beulich <jbeulich@novell.com>
1354 * i386.h (i386_optab): Add ht and hnt.
1356 2005-04-18 Mark Kettenis <kettenis@gnu.org>
1358 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1359 Add xcrypt-ctr. Provide aliases without hyphens.
1361 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1363 Moved from ../ChangeLog
1365 2005-04-12 Paul Brook <paul@codesourcery.com>
1366 * m88k.h: Rename psr macros to avoid conflicts.
1368 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1369 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1370 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1371 and ARM_ARCH_V6ZKT2.
1373 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1374 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1375 Remove redundant instruction types.
1376 (struct argument): X_op - new field.
1377 (struct cst4_entry): Remove.
1378 (no_op_insn): Declare.
1380 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1381 * crx.h (enum argtype): Rename types, remove unused types.
1383 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1384 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1385 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1386 (enum operand_type): Rearrange operands, edit comments.
1387 replace us<N> with ui<N> for unsigned immediate.
1388 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1389 displacements (respectively).
1390 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1391 (instruction type): Add NO_TYPE_INS.
1392 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1393 (operand_entry): New field - 'flags'.
1394 (operand flags): New.
1396 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1397 * crx.h (operand_type): Remove redundant types i3, i4,
1399 Add new unsigned immediate types us3, us4, us5, us16.
1401 2005-04-12 Mark Kettenis <kettenis@gnu.org>
1403 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1404 adjust them accordingly.
1406 2005-04-01 Jan Beulich <jbeulich@novell.com>
1408 * i386.h (i386_optab): Add rdtscp.
1410 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1412 * i386.h (i386_optab): Don't allow the `l' suffix for moving
1413 between memory and segment register. Allow movq for moving between
1414 general-purpose register and segment register.
1416 2005-02-09 Jan Beulich <jbeulich@novell.com>
1419 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1420 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1423 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1425 * m68k.h (m68008, m68ec030, m68882): Remove.
1427 (cpu_m68k, cpu_cf): New.
1428 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1429 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1431 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
1433 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1434 * cgen.h (enum cgen_parse_operand_type): Add
1435 CGEN_PARSE_OPERAND_SYMBOLIC.
1437 2005-01-21 Fred Fish <fnf@specifixinc.com>
1439 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1440 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1441 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1443 2005-01-19 Fred Fish <fnf@specifixinc.com>
1445 * mips.h (struct mips_opcode): Add new pinfo2 member.
1446 (INSN_ALIAS): New define for opcode table entries that are
1447 specific instances of another entry, such as 'move' for an 'or'
1448 with a zero operand.
1449 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1450 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1452 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1454 * mips.h (CPU_RM9000): Define.
1455 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1457 2004-11-25 Jan Beulich <jbeulich@novell.com>
1459 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1460 to/from test registers are illegal in 64-bit mode. Add missing
1461 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1462 (previously one had to explicitly encode a rex64 prefix). Re-enable
1463 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1464 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1466 2004-11-23 Jan Beulich <jbeulich@novell.com>
1468 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1469 available only with SSE2. Change the MMX additions introduced by SSE
1470 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1471 instructions by their now designated identifier (since combining i686
1472 and 3DNow! does not really imply 3DNow!A).
1474 2004-11-19 Alan Modra <amodra@bigpond.net.au>
1476 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1477 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1479 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1480 Vineet Sharma <vineets@noida.hcltech.com>
1482 * maxq.h: New file: Disassembly information for the maxq port.
1484 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1486 * i386.h (i386_optab): Put back "movzb".
1488 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
1490 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1491 comments. Remove member cris_ver_sim. Add members
1492 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1493 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1494 (struct cris_support_reg, struct cris_cond15): New types.
1495 (cris_conds15): Declare.
1496 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1497 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1498 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1499 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1500 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1501 SIZE_FIELD_UNSIGNED.
1503 2004-11-04 Jan Beulich <jbeulich@novell.com>
1505 * i386.h (sldx_Suf): Remove.
1506 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1507 (q_FP): Define, implying no REX64.
1508 (x_FP, sl_FP): Imply FloatMF.
1509 (i386_optab): Split reg and mem forms of moving from segment registers
1510 so that the memory forms can ignore the 16-/32-bit operand size
1511 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1512 all non-floating-point instructions. Unite 32- and 64-bit forms of
1513 movsx, movzx, and movd. Adjust floating point operations for the above
1514 changes to the *FP macros. Add DefaultSize to floating point control
1515 insns operating on larger memory ranges. Remove left over comments
1516 hinting at certain insns being Intel-syntax ones where the ones
1517 actually meant are already gone.
1519 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1521 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1524 2004-09-30 Paul Brook <paul@codesourcery.com>
1526 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1527 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1529 2004-09-11 Theodore A. Roth <troth@openavr.org>
1531 * avr.h: Add support for
1532 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1534 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1536 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1538 2004-08-24 Dmitry Diky <diwil@spec.ru>
1540 * msp430.h (msp430_opc): Add new instructions.
1541 (msp430_rcodes): Declare new instructions.
1542 (msp430_hcodes): Likewise..
1544 2004-08-13 Nick Clifton <nickc@redhat.com>
1547 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1550 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1552 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1554 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1556 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1558 2004-07-21 Jan Beulich <jbeulich@novell.com>
1560 * i386.h: Adjust instruction descriptions to better match the
1563 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
1565 * arm.h: Remove all old content. Replace with architecture defines
1566 from gas/config/tc-arm.c.
1568 2004-07-09 Andreas Schwab <schwab@suse.de>
1570 * m68k.h: Fix comment.
1572 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1576 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1578 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1580 2004-05-24 Peter Barada <peter@the-baradas.com>
1582 * m68k.h: Add 'size' to m68k_opcode.
1584 2004-05-05 Peter Barada <peter@the-baradas.com>
1586 * m68k.h: Switch from ColdFire chip name to core variant.
1588 2004-04-22 Peter Barada <peter@the-baradas.com>
1590 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1591 descriptions for new EMAC cases.
1592 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1593 handle Motorola MAC syntax.
1594 Allow disassembly of ColdFire V4e object files.
1596 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1598 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1600 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1602 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1604 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1606 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1608 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1610 * i386.h (i386_optab): Added xstore/xcrypt insns.
1612 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1614 * h8300.h (32bit ldc/stc): Add relaxing support.
1616 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1618 * h8300.h (BITOP): Pass MEMRELAX flag.
1620 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1622 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1625 For older changes see ChangeLog-9103
1627 Copyright (C) 2004-2012 Free Software Foundation, Inc.
1629 Copying and distribution of this file, with or without modification,
1630 are permitted in any medium without royalty provided the copyright
1631 notice and this notice are preserved.
1637 version-control: never