1 2013-06-12 Sandra Loosemore <sandra@codesourcery.com>
3 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
5 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
7 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
9 2013-05-09 Andrew Pinski <apinski@cavium.com>
11 * mips.h (OP_MASK_CODE10): Correct definition.
12 (OP_SH_CODE10): Likewise.
13 Add a comment that "+J" is used now for OP_*CODE10.
14 (INSN_ASE_MASK): Update.
15 (INSN_VIRT): New macro.
16 (INSN_VIRT64): New macro
18 2013-05-02 Nick Clifton <nickc@redhat.com>
20 * msp430.h: Add patterns for MSP430X instructions.
22 2013-04-06 David S. Miller <davem@davemloft.net>
24 * sparc.h (F_PREFERRED): Define.
25 (F_PREF_ALIAS): Define.
27 2013-04-03 Nick Clifton <nickc@redhat.com>
29 * v850.h (V850_INVERSE_PCREL): Define.
31 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
34 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
36 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
39 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
41 * tic6xc-opcode-table.h: Add 16-bit insns.
42 * tic6x.h: Add support for 16-bit insns.
44 2013-03-21 Michael Schewe <michael.schewe@gmx.net>
46 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
47 and mov.b/w/l Rs,@(d:32,ERd).
49 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
52 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
53 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
54 tic6x_operand_xregpair operand coding type.
55 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
56 opcode field, usu ORXREGD1324 for the src2 operand and remove the
59 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
62 * tic6x.h (enum tic6x_coding_method): Add
63 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
64 separately the msb and lsb of a register pair. This is needed to
65 encode the opcodes in the same way as TI assembler does.
66 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
67 and rsqrdp opcodes to use the new field coding types.
69 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
71 * arm.h (CRC_EXT_ARMV8): New constant.
72 (ARCH_CRC_ARMV8): New macro.
74 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
76 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
78 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
79 Andrew Jenner <andrew@codesourcery.com>
81 Based on patches from Altera Corporation.
85 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
87 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
89 2013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
92 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
94 2013-01-24 Nick Clifton <nickc@redhat.com>
96 * v850.h: Add e3v5 support.
98 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
100 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
102 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
104 * ppc.h (PPC_OPCODE_POWER8): New define.
105 (PPC_OPCODE_HTM): Likewise.
107 2013-01-10 Will Newton <will.newton@imgtec.com>
111 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
113 * cr16.h (make_instruction): Rename to cr16_make_instruction.
114 (match_opcode): Rename to cr16_match_opcode.
116 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
118 * mips.h: Add support for r5900 instructions including lq and sq.
120 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
122 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
123 (make_instruction,match_opcode): Added function prototypes.
124 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
126 2012-11-23 Alan Modra <amodra@gmail.com>
128 * ppc.h (ppc_parse_cpu): Update prototype.
130 2012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
132 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
133 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
135 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
137 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
139 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
141 * ia64.h (ia64_opnd): Add new operand types.
143 2012-08-21 David S. Miller <davem@davemloft.net>
145 * sparc.h (F3F4): New macro.
147 2012-08-13 Ian Bolton <ian.bolton@arm.com>
148 Laurent Desnogues <laurent.desnogues@arm.com>
149 Jim MacArthur <jim.macarthur@arm.com>
150 Marcus Shawcroft <marcus.shawcroft@arm.com>
151 Nigel Stephens <nigel.stephens@arm.com>
152 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
153 Richard Earnshaw <rearnsha@arm.com>
154 Sofiane Naci <sofiane.naci@arm.com>
155 Tejas Belagod <tejas.belagod@arm.com>
156 Yufeng Zhang <yufeng.zhang@arm.com>
158 * aarch64.h: New file.
160 2012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
161 Maciej W. Rozycki <macro@codesourcery.com>
163 * mips.h (mips_opcode): Add the exclusions field.
164 (OPCODE_IS_MEMBER): Remove macro.
165 (cpu_is_member): New inline function.
166 (opcode_is_member): Likewise.
168 2012-07-31 Chao-Ying Fu <fu@mips.com>
169 Catherine Moore <clm@codesourcery.com>
170 Maciej W. Rozycki <macro@codesourcery.com>
172 * mips.h: Document microMIPS DSP ASE usage.
173 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
174 microMIPS DSP ASE support.
175 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
176 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
177 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
178 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
179 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
180 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
181 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
183 2012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
185 * mips.h: Fix a typo in description.
187 2012-06-07 Georg-Johann Lay <avr@gjlay.de>
189 * avr.h: (AVR_ISA_XCH): New define.
190 (AVR_ISA_XMEGA): Use it.
191 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
193 2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
195 * m68hc11.h: Add XGate definitions.
196 (struct m68hc11_opcode): Add xg_mask field.
198 2012-05-14 Catherine Moore <clm@codesourcery.com>
199 Maciej W. Rozycki <macro@codesourcery.com>
200 Rhonda Wittels <rhonda@codesourcery.com>
202 * ppc.h (PPC_OPCODE_VLE): New definition.
203 (PPC_OP_SA): New macro.
204 (PPC_OP_SE_VLE): New macro.
205 (PPC_OP): Use a variable shift amount.
206 (powerpc_operand): Update comments.
207 (PPC_OPSHIFT_INV): New macro.
208 (PPC_OPERAND_CR): Replace with...
209 (PPC_OPERAND_CR_BIT): ...this and
210 (PPC_OPERAND_CR_REG): ...this.
213 2012-05-03 Sean Keys <skeys@ipdatasys.com>
215 * xgate.h: Header file for XGATE assembler.
217 2012-04-27 David S. Miller <davem@davemloft.net>
219 * sparc.h: Document new arg code' )' for crypto RS3
222 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
223 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
224 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
225 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
226 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
227 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
228 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
229 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
230 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
231 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
232 HWCAP_CBCOND, HWCAP_CRC32): New defines.
234 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
236 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
238 2012-02-27 Alan Modra <amodra@gmail.com>
240 * crx.h (cst4_map): Update declaration.
242 2012-02-25 Walter Lee <walt@tilera.com>
244 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
246 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
247 TILEPRO_OPC_LW_TLS_SN.
249 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
251 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
252 (XRELEASE_PREFIX_OPCODE): Likewise.
254 2011-12-08 Andrew Pinski <apinski@cavium.com>
255 Adam Nemet <anemet@caviumnetworks.com>
257 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
258 (INSN_OCTEON2): New macro.
259 (CPU_OCTEON2): New macro.
260 (OPCODE_IS_MEMBER): Add Octeon2.
262 2011-11-29 Andrew Pinski <apinski@cavium.com>
264 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
265 (INSN_OCTEONP): New macro.
266 (CPU_OCTEONP): New macro.
267 (OPCODE_IS_MEMBER): Add Octeon+.
268 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
270 2011-11-01 DJ Delorie <dj@redhat.com>
274 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
276 * mips.h: Fix a typo in description.
278 2011-09-21 David S. Miller <davem@davemloft.net>
280 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
281 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
282 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
283 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
285 2011-08-09 Chao-ying Fu <fu@mips.com>
286 Maciej W. Rozycki <macro@codesourcery.com>
288 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
289 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
290 (INSN_ASE_MASK): Add the MCU bit.
291 (INSN_MCU): New macro.
292 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
293 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
295 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
297 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
298 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
299 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
300 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
301 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
302 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
303 (INSN2_READ_GPR_MMN): Likewise.
304 (INSN2_READ_FPR_D): Change the bit used.
305 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
306 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
307 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
308 (INSN2_COND_BRANCH): Likewise.
309 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
310 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
311 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
312 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
313 (INSN2_MOD_GPR_MN): Likewise.
315 2011-08-05 David S. Miller <davem@davemloft.net>
317 * sparc.h: Document new format codes '4', '5', and '('.
318 (OPF_LOW4, RS3): New macros.
320 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
322 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
323 order of flags documented.
325 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
327 * mips.h: Clarify the description of microMIPS instruction
329 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
331 2011-07-24 Chao-ying Fu <fu@mips.com>
332 Maciej W. Rozycki <macro@codesourcery.com>
334 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
335 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
336 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
337 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
338 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
339 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
340 (OP_MASK_RS3, OP_SH_RS3): Likewise.
341 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
342 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
343 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
344 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
345 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
346 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
347 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
348 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
349 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
350 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
351 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
352 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
353 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
354 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
355 (INSN_WRITE_GPR_S): New macro.
356 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
357 (INSN2_READ_FPR_D): Likewise.
358 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
359 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
360 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
361 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
362 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
363 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
364 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
365 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
366 (CPU_MICROMIPS): New macro.
367 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
368 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
369 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
370 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
371 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
372 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
373 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
374 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
375 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
376 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
377 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
378 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
379 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
380 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
381 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
382 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
383 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
384 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
385 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
386 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
387 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
388 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
389 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
390 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
391 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
392 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
393 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
394 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
395 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
396 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
397 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
398 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
399 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
400 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
401 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
402 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
403 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
404 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
405 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
406 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
407 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
408 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
409 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
410 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
411 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
412 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
413 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
414 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
415 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
416 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
417 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
418 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
419 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
420 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
421 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
422 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
423 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
424 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
425 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
426 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
427 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
428 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
429 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
430 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
431 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
432 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
433 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
434 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
435 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
436 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
437 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
438 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
439 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
440 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
441 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
442 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
443 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
444 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
445 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
446 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
447 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
448 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
449 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
450 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
451 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
452 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
453 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
454 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
455 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
456 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
457 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
458 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
459 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
460 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
461 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
462 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
463 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
464 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
465 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
466 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
467 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
468 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
469 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
470 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
471 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
472 (micromips_opcodes): New declaration.
473 (bfd_micromips_num_opcodes): Likewise.
475 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
477 * mips.h (INSN_TRAP): Rename to...
478 (INSN_NO_DELAY_SLOT): ... this.
479 (INSN_SYNC): Remove macro.
481 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
483 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
484 a duplicate of AVR_ISA_SPM.
486 2011-07-01 Nick Clifton <nickc@redhat.com>
488 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
490 2011-06-18 Robin Getz <robin.getz@analog.com>
492 * bfin.h (is_macmod_signed): New func
494 2011-06-18 Mike Frysinger <vapier@gentoo.org>
496 * bfin.h (is_macmod_pmove): Add missing space before func args.
497 (is_macmod_hmove): Likewise.
499 2011-06-13 Walter Lee <walt@tilera.com>
501 * tilegx.h: New file.
502 * tilepro.h: New file.
504 2011-05-31 Paul Brook <paul@codesourcery.com>
506 * arm.h (ARM_ARCH_V7R_IDIV): Define.
508 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
510 * s390.h: Replace S390_OPERAND_REG_EVEN with
511 S390_OPERAND_REG_PAIR.
513 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
515 * s390.h: Add S390_OPCODE_REG_EVEN flag.
517 2011-04-18 Julian Brown <julian@codesourcery.com>
519 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
521 2011-04-11 Dan McDonald <dan@wellkeeper.com>
524 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
526 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
528 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
529 New instruction set flags.
530 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
532 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
534 * mips.h (M_PREF_AB): New enum value.
536 2011-02-12 Mike Frysinger <vapier@gentoo.org>
538 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
540 (is_macmod_pmove, is_macmod_hmove): New functions.
542 2011-02-11 Mike Frysinger <vapier@gentoo.org>
544 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
546 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
548 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
549 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
551 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
554 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
557 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
560 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
562 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
564 * mips.h: Update commentary after last commit.
566 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
568 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
569 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
570 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
572 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
574 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
576 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
578 * mips.h: Fix previous commit.
580 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
582 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
583 (INSN_LOONGSON_3A): Clear bit 31.
585 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
588 * arm.h (ARM_AEXT_V6M_ONLY): New define.
589 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
590 (ARM_ARCH_V6M_ONLY): New define.
592 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
594 * mips.h (INSN_LOONGSON_3A): Defined.
595 (CPU_LOONGSON_3A): Defined.
596 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
598 2010-10-09 Matt Rice <ratmice@gmail.com>
600 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
601 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
603 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
605 * arm.h (ARM_EXT_VIRT): New define.
606 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
607 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
610 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
612 * arm.h (ARM_AEXT_ADIV): New define.
613 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
615 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
617 * arm.h (ARM_EXT_OS): New define.
618 (ARM_AEXT_V6SM): Likewise.
619 (ARM_ARCH_V6SM): Likewise.
621 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
623 * arm.h (ARM_EXT_MP): Add.
624 (ARM_ARCH_V7A_MP): Likewise.
626 2010-09-22 Mike Frysinger <vapier@gentoo.org>
628 * bfin.h: Declare pseudoChr structs/defines.
630 2010-09-21 Mike Frysinger <vapier@gentoo.org>
632 * bfin.h: Strip trailing whitespace.
634 2010-07-29 DJ Delorie <dj@redhat.com>
636 * rx.h (RX_Operand_Type): Add TwoReg.
637 (RX_Opcode_ID): Remove ediv and ediv2.
639 2010-07-27 DJ Delorie <dj@redhat.com>
641 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
643 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
644 Ina Pandit <ina.pandit@kpitcummins.com>
646 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
647 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
648 PROCESSOR_V850E2_ALL.
649 Remove PROCESSOR_V850EA support.
650 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
651 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
652 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
653 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
654 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
655 V850_OPERAND_PERCENT.
656 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
658 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
661 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
663 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
664 (MIPS16_INSN_BRANCH): Rename to...
665 (MIPS16_INSN_COND_BRANCH): ... this.
667 2010-07-03 Alan Modra <amodra@gmail.com>
669 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
670 Renumber other PPC_OPCODE defines.
672 2010-07-03 Alan Modra <amodra@gmail.com>
674 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
676 2010-06-29 Alan Modra <amodra@gmail.com>
678 * maxq.h: Delete file.
680 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
682 * ppc.h (PPC_OPCODE_E500): Define.
684 2010-05-26 Catherine Moore <clm@codesourcery.com>
686 * opcode/mips.h (INSN_MIPS16): Remove.
688 2010-04-21 Joseph Myers <joseph@codesourcery.com>
690 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
692 2010-04-15 Nick Clifton <nickc@redhat.com>
694 * alpha.h: Update copyright notice to use GPLv3.
700 * convex.h: Likewise.
714 * m68hc11.h: Likewise.
720 * mn10200.h: Likewise.
721 * mn10300.h: Likewise.
722 * msp430.h: Likewise.
733 * score-datadep.h: Likewise.
734 * score-inst.h: Likewise.
736 * spu-insns.h: Likewise.
740 * tic54x.h: Likewise.
745 2010-03-25 Joseph Myers <joseph@codesourcery.com>
747 * tic6x-control-registers.h, tic6x-insn-formats.h,
748 tic6x-opcode-table.h, tic6x.h: New.
750 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
752 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
754 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
756 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
758 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
760 * ia64.h (ia64_find_opcode): Remove argument name.
761 (ia64_find_next_opcode): Likewise.
762 (ia64_dis_opcode): Likewise.
763 (ia64_free_opcode): Likewise.
764 (ia64_find_dependency): Likewise.
766 2009-11-22 Doug Evans <dje@sebabeach.org>
768 * cgen.h: Include bfd_stdint.h.
769 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
771 2009-11-18 Paul Brook <paul@codesourcery.com>
773 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
775 2009-11-17 Paul Brook <paul@codesourcery.com>
776 Daniel Jacobowitz <dan@codesourcery.com>
778 * arm.h (ARM_EXT_V6_DSP): Define.
779 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
780 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
782 2009-11-04 DJ Delorie <dj@redhat.com>
784 * rx.h (rx_decode_opcode) (mvtipl): Add.
785 (mvtcp, mvfcp, opecp): Remove.
787 2009-11-02 Paul Brook <paul@codesourcery.com>
789 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
790 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
791 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
792 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
793 FPU_ARCH_NEON_VFP_V4): Define.
795 2009-10-23 Doug Evans <dje@sebabeach.org>
797 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
798 * cgen.h: Update. Improve multi-inclusion macro name.
800 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
802 * ppc.h (PPC_OPCODE_476): Define.
804 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
806 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
808 2009-09-29 DJ Delorie <dj@redhat.com>
812 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
814 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
816 2009-09-21 Ben Elliston <bje@au.ibm.com>
818 * ppc.h (PPC_OPCODE_PPCA2): New.
820 2009-09-05 Martin Thuresson <martin@mtme.org>
822 * ia64.h (struct ia64_operand): Renamed member class to op_class.
824 2009-08-29 Martin Thuresson <martin@mtme.org>
826 * tic30.h (template): Rename type template to
827 insn_template. Updated code to use new name.
828 * tic54x.h (template): Rename type template to
831 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
833 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
835 2009-06-11 Anthony Green <green@moxielogic.com>
837 * moxie.h (MOXIE_F3_PCREL): Define.
838 (moxie_form3_opc_info): Grow.
840 2009-06-06 Anthony Green <green@moxielogic.com>
842 * moxie.h (MOXIE_F1_M): Define.
844 2009-04-15 Anthony Green <green@moxielogic.com>
848 2009-04-06 DJ Delorie <dj@redhat.com>
850 * h8300.h: Add relaxation attributes to MOVA opcodes.
852 2009-03-10 Alan Modra <amodra@bigpond.net.au>
854 * ppc.h (ppc_parse_cpu): Declare.
856 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
858 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
859 and _IMM11 for mbitclr and mbitset.
860 * score-datadep.h: Update dependency information.
862 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
864 * ppc.h (PPC_OPCODE_POWER7): New.
866 2009-02-06 Doug Evans <dje@google.com>
868 * i386.h: Add comment regarding sse* insns and prefixes.
870 2009-02-03 Sandip Matte <sandip@rmicorp.com>
872 * mips.h (INSN_XLR): Define.
873 (INSN_CHIP_MASK): Update.
875 (OPCODE_IS_MEMBER): Update.
876 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
878 2009-01-28 Doug Evans <dje@google.com>
880 * opcode/i386.h: Add multiple inclusion protection.
881 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
882 (EDI_REG_NUM): New macros.
883 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
884 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
885 (REX_PREFIX_P): New macro.
887 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
889 * ppc.h (struct powerpc_opcode): New field "deprecated".
890 (PPC_OPCODE_NOPOWER4): Delete.
892 2008-11-28 Joshua Kinard <kumba@gentoo.org>
894 * mips.h: Define CPU_R14000, CPU_R16000.
895 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
897 2008-11-18 Catherine Moore <clm@codesourcery.com>
899 * arm.h (FPU_NEON_FP16): New.
900 (FPU_ARCH_NEON_FP16): New.
902 2008-11-06 Chao-ying Fu <fu@mips.com>
904 * mips.h: Doucument '1' for 5-bit sync type.
906 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
908 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
911 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
913 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
915 2008-07-30 Michael J. Eager <eager@eagercon.com>
917 * ppc.h (PPC_OPCODE_405): Define.
918 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
920 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
922 * ppc.h (ppc_cpu_t): New typedef.
923 (struct powerpc_opcode <flags>): Use it.
924 (struct powerpc_operand <insert, extract>): Likewise.
925 (struct powerpc_macro <flags>): Likewise.
927 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
929 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
930 Update comment before MIPS16 field descriptors to mention MIPS16.
931 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
933 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
934 New bit masks and shift counts for cins and exts.
936 * mips.h: Document new field descriptors +Q.
937 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
939 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
941 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
942 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
944 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
946 * ppc.h: (PPC_OPCODE_E500MC): New.
948 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
950 * i386.h (MAX_OPERANDS): Set to 5.
951 (MAX_MNEM_SIZE): Changed to 20.
953 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
955 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
957 2008-03-09 Paul Brook <paul@codesourcery.com>
959 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
961 2008-03-04 Paul Brook <paul@codesourcery.com>
963 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
964 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
965 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
967 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
968 Nick Clifton <nickc@redhat.com>
971 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
972 with a 32-bit displacement but without the top bit of the 4th byte
975 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
977 * cr16.h (cr16_num_optab): Declared.
979 2008-02-14 Hakan Ardo <hakan@debian.org>
982 * avr.h (AVR_ISA_2xxe): Define.
984 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
986 * mips.h: Update copyright.
987 (INSN_CHIP_MASK): New macro.
988 (INSN_OCTEON): New macro.
989 (CPU_OCTEON): New macro.
990 (OPCODE_IS_MEMBER): Handle Octeon instructions.
992 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
994 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
996 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
998 * avr.h (AVR_ISA_USB162): Add new opcode set.
999 (AVR_ISA_AVR3): Likewise.
1001 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1003 * mips.h (INSN_LOONGSON_2E): New.
1004 (INSN_LOONGSON_2F): New.
1005 (CPU_LOONGSON_2E): New.
1006 (CPU_LOONGSON_2F): New.
1007 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1009 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1011 * mips.h (INSN_ISA*): Redefine certain values as an
1012 enumeration. Update comments.
1013 (mips_isa_table): New.
1014 (ISA_MIPS*): Redefine to match enumeration.
1015 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1018 2007-08-08 Ben Elliston <bje@au.ibm.com>
1020 * ppc.h (PPC_OPCODE_PPCPS): New.
1022 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1024 * m68k.h: Document j K & E.
1026 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1028 * cr16.h: New file for CR16 target.
1030 2007-05-02 Alan Modra <amodra@bigpond.net.au>
1032 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1034 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1036 * m68k.h (mcfisa_c): New.
1037 (mcfusp, mcf_mask): Adjust.
1039 2007-04-20 Alan Modra <amodra@bigpond.net.au>
1041 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1042 (num_powerpc_operands): Declare.
1043 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1044 (PPC_OPERAND_PLUS1): Define.
1046 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
1048 * i386.h (REX_MODE64): Renamed to ...
1050 (REX_EXTX): Renamed to ...
1052 (REX_EXTY): Renamed to ...
1054 (REX_EXTZ): Renamed to ...
1057 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1059 * i386.h: Add entries from config/tc-i386.h and move tables
1060 to opcodes/i386-opc.h.
1062 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1064 * i386.h (FloatDR): Removed.
1065 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1067 2007-03-01 Alan Modra <amodra@bigpond.net.au>
1069 * spu-insns.h: Add soma double-float insns.
1071 2007-02-20 Thiemo Seufer <ths@mips.com>
1072 Chao-Ying Fu <fu@mips.com>
1074 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1075 (INSN_DSPR2): Add flag for DSP R2 instructions.
1076 (M_BALIGN): New macro.
1078 2007-02-14 Alan Modra <amodra@bigpond.net.au>
1080 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1081 and Seg3ShortFrom with Shortform.
1083 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1086 * i386.h (i386_optab): Put the real "test" before the pseudo
1089 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
1091 * m68k.h (m68010up): OR fido_a.
1093 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
1095 * m68k.h (fido_a): New.
1097 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
1099 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1100 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1103 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1105 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1107 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1109 * score-inst.h (enum score_insn_type): Add Insn_internal.
1111 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1112 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1113 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1114 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1115 Alan Modra <amodra@bigpond.net.au>
1117 * spu-insns.h: New file.
1120 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1122 * ppc.h (PPC_OPCODE_CELL): Define.
1124 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1126 * i386.h : Modify opcode to support for the change in POPCNT opcode
1127 in amdfam10 architecture.
1129 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1131 * i386.h: Replace CpuMNI with CpuSSSE3.
1133 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
1134 Joseph Myers <joseph@codesourcery.com>
1135 Ian Lance Taylor <ian@wasabisystems.com>
1136 Ben Elliston <bje@wasabisystems.com>
1138 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1140 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1142 * score-datadep.h: New file.
1143 * score-inst.h: New file.
1145 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1147 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1148 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1149 movdq2q and movq2dq.
1151 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1152 Michael Meissner <michael.meissner@amd.com>
1154 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1156 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1158 * i386.h (i386_optab): Add "nop" with memory reference.
1160 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1162 * i386.h (i386_optab): Update comment for 64bit NOP.
1164 2006-06-06 Ben Elliston <bje@au.ibm.com>
1165 Anton Blanchard <anton@samba.org>
1167 * ppc.h (PPC_OPCODE_POWER6): Define.
1170 2006-06-05 Thiemo Seufer <ths@mips.com>
1172 * mips.h: Improve description of MT flags.
1174 2006-05-25 Richard Sandiford <richard@codesourcery.com>
1176 * m68k.h (mcf_mask): Define.
1178 2006-05-05 Thiemo Seufer <ths@mips.com>
1179 David Ung <davidu@mips.com>
1181 * mips.h (enum): Add macro M_CACHE_AB.
1183 2006-05-04 Thiemo Seufer <ths@mips.com>
1184 Nigel Stephens <nigel@mips.com>
1185 David Ung <davidu@mips.com>
1187 * mips.h: Add INSN_SMARTMIPS define.
1189 2006-04-30 Thiemo Seufer <ths@mips.com>
1190 David Ung <davidu@mips.com>
1192 * mips.h: Defines udi bits and masks. Add description of
1193 characters which may appear in the args field of udi
1196 2006-04-26 Thiemo Seufer <ths@networkno.de>
1198 * mips.h: Improve comments describing the bitfield instruction
1201 2006-04-26 Julian Brown <julian@codesourcery.com>
1203 * arm.h (FPU_VFP_EXT_V3): Define constant.
1204 (FPU_NEON_EXT_V1): Likewise.
1205 (FPU_VFP_HARD): Update.
1206 (FPU_VFP_V3): Define macro.
1207 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1209 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
1211 * avr.h (AVR_ISA_PWMx): New.
1213 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1215 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1216 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1217 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1218 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1219 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1221 2006-03-10 Paul Brook <paul@codesourcery.com>
1223 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1225 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1227 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1228 first. Correct mask of bb "B" opcode.
1230 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1232 * i386.h (i386_optab): Support Intel Merom New Instructions.
1234 2006-02-24 Paul Brook <paul@codesourcery.com>
1236 * arm.h: Add V7 feature bits.
1238 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1240 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1242 2006-01-31 Paul Brook <paul@codesourcery.com>
1243 Richard Earnshaw <rearnsha@arm.com>
1245 * arm.h: Use ARM_CPU_FEATURE.
1246 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1247 (arm_feature_set): Change to a structure.
1248 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1249 ARM_FEATURE): New macros.
1251 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
1253 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1254 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1255 (ADD_PC_INCR_OPCODE): Don't define.
1257 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1260 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1262 2005-11-14 David Ung <davidu@mips.com>
1264 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1265 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1266 save/restore encoding of the args field.
1268 2005-10-28 Dave Brolley <brolley@redhat.com>
1270 Contribute the following changes:
1271 2005-02-16 Dave Brolley <brolley@redhat.com>
1273 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1274 cgen_isa_mask_* to cgen_bitset_*.
1277 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1279 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1280 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1281 (CGEN_CPU_TABLE): Make isas a ponter.
1283 2003-09-29 Dave Brolley <brolley@redhat.com>
1285 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1286 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1287 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1289 2002-12-13 Dave Brolley <brolley@redhat.com>
1291 * cgen.h (symcat.h): #include it.
1292 (cgen-bitset.h): #include it.
1293 (CGEN_ATTR_VALUE_TYPE): Now a union.
1294 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1295 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1296 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1297 * cgen-bitset.h: New file.
1299 2005-09-30 Catherine Moore <clm@cm00re.com>
1303 2005-10-24 Jan Beulich <jbeulich@novell.com>
1305 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1308 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1310 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1311 Add FLAG_STRICT to pa10 ftest opcode.
1313 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1315 * hppa.h (pa_opcodes): Remove lha entries.
1317 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1319 * hppa.h (FLAG_STRICT): Revise comment.
1320 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1321 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1324 2005-09-30 Catherine Moore <clm@cm00re.com>
1328 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1330 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1332 2005-09-06 Chao-ying Fu <fu@mips.com>
1334 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1335 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1337 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1338 (INSN_ASE_MASK): Update to include INSN_MT.
1339 (INSN_MT): New define for MT ASE.
1341 2005-08-25 Chao-ying Fu <fu@mips.com>
1343 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1344 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1345 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1346 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1347 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1348 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1350 (INSN_DSP): New define for DSP ASE.
1352 2005-08-18 Alan Modra <amodra@bigpond.net.au>
1356 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1358 * ppc.h (PPC_OPCODE_E300): Define.
1360 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1362 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1364 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1367 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1370 2005-07-27 Jan Beulich <jbeulich@novell.com>
1372 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1373 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1374 Add movq-s as 64-bit variants of movd-s.
1376 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1378 * hppa.h: Fix punctuation in comment.
1380 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1381 implicit space-register addressing. Set space-register bits on opcodes
1382 using implicit space-register addressing. Add various missing pa20
1383 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1384 space-register addressing. Use "fE" instead of "fe" in various
1387 2005-07-18 Jan Beulich <jbeulich@novell.com>
1389 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1391 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1393 * i386.h (i386_optab): Support Intel VMX Instructions.
1395 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1397 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1399 2005-07-05 Jan Beulich <jbeulich@novell.com>
1401 * i386.h (i386_optab): Add new insns.
1403 2005-07-01 Nick Clifton <nickc@redhat.com>
1405 * sparc.h: Add typedefs to structure declarations.
1407 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1410 * i386.h (i386_optab): Update comments for 64bit addressing on
1411 mov. Allow 64bit addressing for mov and movq.
1413 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1415 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1416 respectively, in various floating-point load and store patterns.
1418 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1420 * hppa.h (FLAG_STRICT): Correct comment.
1421 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1422 PA 2.0 mneumonics when equivalent. Entries with cache control
1423 completers now require PA 1.1. Adjust whitespace.
1425 2005-05-19 Anton Blanchard <anton@samba.org>
1427 * ppc.h (PPC_OPCODE_POWER5): Define.
1429 2005-05-10 Nick Clifton <nickc@redhat.com>
1431 * Update the address and phone number of the FSF organization in
1432 the GPL notices in the following files:
1433 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1434 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1435 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1436 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1437 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1438 tic54x.h, tic80.h, v850.h, vax.h
1440 2005-05-09 Jan Beulich <jbeulich@novell.com>
1442 * i386.h (i386_optab): Add ht and hnt.
1444 2005-04-18 Mark Kettenis <kettenis@gnu.org>
1446 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1447 Add xcrypt-ctr. Provide aliases without hyphens.
1449 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1451 Moved from ../ChangeLog
1453 2005-04-12 Paul Brook <paul@codesourcery.com>
1454 * m88k.h: Rename psr macros to avoid conflicts.
1456 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1457 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1458 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1459 and ARM_ARCH_V6ZKT2.
1461 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1462 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1463 Remove redundant instruction types.
1464 (struct argument): X_op - new field.
1465 (struct cst4_entry): Remove.
1466 (no_op_insn): Declare.
1468 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1469 * crx.h (enum argtype): Rename types, remove unused types.
1471 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1472 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1473 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1474 (enum operand_type): Rearrange operands, edit comments.
1475 replace us<N> with ui<N> for unsigned immediate.
1476 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1477 displacements (respectively).
1478 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1479 (instruction type): Add NO_TYPE_INS.
1480 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1481 (operand_entry): New field - 'flags'.
1482 (operand flags): New.
1484 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1485 * crx.h (operand_type): Remove redundant types i3, i4,
1487 Add new unsigned immediate types us3, us4, us5, us16.
1489 2005-04-12 Mark Kettenis <kettenis@gnu.org>
1491 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1492 adjust them accordingly.
1494 2005-04-01 Jan Beulich <jbeulich@novell.com>
1496 * i386.h (i386_optab): Add rdtscp.
1498 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1500 * i386.h (i386_optab): Don't allow the `l' suffix for moving
1501 between memory and segment register. Allow movq for moving between
1502 general-purpose register and segment register.
1504 2005-02-09 Jan Beulich <jbeulich@novell.com>
1507 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1508 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1511 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1513 * m68k.h (m68008, m68ec030, m68882): Remove.
1515 (cpu_m68k, cpu_cf): New.
1516 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1517 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1519 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
1521 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1522 * cgen.h (enum cgen_parse_operand_type): Add
1523 CGEN_PARSE_OPERAND_SYMBOLIC.
1525 2005-01-21 Fred Fish <fnf@specifixinc.com>
1527 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1528 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1529 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1531 2005-01-19 Fred Fish <fnf@specifixinc.com>
1533 * mips.h (struct mips_opcode): Add new pinfo2 member.
1534 (INSN_ALIAS): New define for opcode table entries that are
1535 specific instances of another entry, such as 'move' for an 'or'
1536 with a zero operand.
1537 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1538 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1540 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1542 * mips.h (CPU_RM9000): Define.
1543 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1545 2004-11-25 Jan Beulich <jbeulich@novell.com>
1547 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1548 to/from test registers are illegal in 64-bit mode. Add missing
1549 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1550 (previously one had to explicitly encode a rex64 prefix). Re-enable
1551 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1552 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1554 2004-11-23 Jan Beulich <jbeulich@novell.com>
1556 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1557 available only with SSE2. Change the MMX additions introduced by SSE
1558 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1559 instructions by their now designated identifier (since combining i686
1560 and 3DNow! does not really imply 3DNow!A).
1562 2004-11-19 Alan Modra <amodra@bigpond.net.au>
1564 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1565 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1567 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1568 Vineet Sharma <vineets@noida.hcltech.com>
1570 * maxq.h: New file: Disassembly information for the maxq port.
1572 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1574 * i386.h (i386_optab): Put back "movzb".
1576 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
1578 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1579 comments. Remove member cris_ver_sim. Add members
1580 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1581 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1582 (struct cris_support_reg, struct cris_cond15): New types.
1583 (cris_conds15): Declare.
1584 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1585 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1586 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1587 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1588 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1589 SIZE_FIELD_UNSIGNED.
1591 2004-11-04 Jan Beulich <jbeulich@novell.com>
1593 * i386.h (sldx_Suf): Remove.
1594 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1595 (q_FP): Define, implying no REX64.
1596 (x_FP, sl_FP): Imply FloatMF.
1597 (i386_optab): Split reg and mem forms of moving from segment registers
1598 so that the memory forms can ignore the 16-/32-bit operand size
1599 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1600 all non-floating-point instructions. Unite 32- and 64-bit forms of
1601 movsx, movzx, and movd. Adjust floating point operations for the above
1602 changes to the *FP macros. Add DefaultSize to floating point control
1603 insns operating on larger memory ranges. Remove left over comments
1604 hinting at certain insns being Intel-syntax ones where the ones
1605 actually meant are already gone.
1607 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1609 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1612 2004-09-30 Paul Brook <paul@codesourcery.com>
1614 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1615 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1617 2004-09-11 Theodore A. Roth <troth@openavr.org>
1619 * avr.h: Add support for
1620 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1622 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1624 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1626 2004-08-24 Dmitry Diky <diwil@spec.ru>
1628 * msp430.h (msp430_opc): Add new instructions.
1629 (msp430_rcodes): Declare new instructions.
1630 (msp430_hcodes): Likewise..
1632 2004-08-13 Nick Clifton <nickc@redhat.com>
1635 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1638 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1640 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1642 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1644 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1646 2004-07-21 Jan Beulich <jbeulich@novell.com>
1648 * i386.h: Adjust instruction descriptions to better match the
1651 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
1653 * arm.h: Remove all old content. Replace with architecture defines
1654 from gas/config/tc-arm.c.
1656 2004-07-09 Andreas Schwab <schwab@suse.de>
1658 * m68k.h: Fix comment.
1660 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1664 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1666 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1668 2004-05-24 Peter Barada <peter@the-baradas.com>
1670 * m68k.h: Add 'size' to m68k_opcode.
1672 2004-05-05 Peter Barada <peter@the-baradas.com>
1674 * m68k.h: Switch from ColdFire chip name to core variant.
1676 2004-04-22 Peter Barada <peter@the-baradas.com>
1678 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1679 descriptions for new EMAC cases.
1680 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1681 handle Motorola MAC syntax.
1682 Allow disassembly of ColdFire V4e object files.
1684 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1686 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1688 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1690 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1692 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1694 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1696 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1698 * i386.h (i386_optab): Added xstore/xcrypt insns.
1700 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1702 * h8300.h (32bit ldc/stc): Add relaxing support.
1704 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1706 * h8300.h (BITOP): Pass MEMRELAX flag.
1708 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1710 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1713 For older changes see ChangeLog-9103
1715 Copyright (C) 2004-2012 Free Software Foundation, Inc.
1717 Copying and distribution of this file, with or without modification,
1718 are permitted in any medium without royalty provided the copyright
1719 notice and this notice are preserved.
1725 version-control: never