1 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
3 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
5 2006-01-31 Paul Brook <paul@codesourcery.com>
6 Richard Earnshaw <rearnsha@arm.com>
8 * arm.h: Use ARM_CPU_FEATURE.
9 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
10 (arm_feature_set): Change to a structure.
11 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
12 ARM_FEATURE): New macros.
14 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
16 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
17 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
18 (ADD_PC_INCR_OPCODE): Don't define.
20 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
23 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
25 2005-11-14 David Ung <davidu@mips.com>
27 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
28 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
29 save/restore encoding of the args field.
31 2005-10-28 Dave Brolley <brolley@redhat.com>
33 Contribute the following changes:
34 2005-02-16 Dave Brolley <brolley@redhat.com>
36 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
37 cgen_isa_mask_* to cgen_bitset_*.
40 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
42 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
43 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
44 (CGEN_CPU_TABLE): Make isas a ponter.
46 2003-09-29 Dave Brolley <brolley@redhat.com>
48 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
49 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
50 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
52 2002-12-13 Dave Brolley <brolley@redhat.com>
54 * cgen.h (symcat.h): #include it.
55 (cgen-bitset.h): #include it.
56 (CGEN_ATTR_VALUE_TYPE): Now a union.
57 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
58 (CGEN_ATTR_ENTRY): 'value' now unsigned.
59 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
60 * cgen-bitset.h: New file.
62 2005-09-30 Catherine Moore <clm@cm00re.com>
66 2005-10-24 Jan Beulich <jbeulich@novell.com>
68 * ia64.h (enum ia64_opnd): Move memory operand out of set of
71 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
73 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
74 Add FLAG_STRICT to pa10 ftest opcode.
76 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
78 * hppa.h (pa_opcodes): Remove lha entries.
80 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
82 * hppa.h (FLAG_STRICT): Revise comment.
83 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
84 before corresponding pa11 opcodes. Add strict pa10 register-immediate
87 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
89 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
91 2005-09-06 Chao-ying Fu <fu@mips.com>
93 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
94 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
96 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
97 (INSN_ASE_MASK): Update to include INSN_MT.
98 (INSN_MT): New define for MT ASE.
100 2005-08-25 Chao-ying Fu <fu@mips.com>
102 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
103 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
104 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
105 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
106 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
107 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
109 (INSN_DSP): New define for DSP ASE.
111 2005-08-18 Alan Modra <amodra@bigpond.net.au>
115 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
117 * ppc.h (PPC_OPCODE_E300): Define.
119 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
121 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
123 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
126 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
129 2005-07-27 Jan Beulich <jbeulich@novell.com>
131 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
132 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
133 Add movq-s as 64-bit variants of movd-s.
135 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
137 * hppa.h: Fix punctuation in comment.
139 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
140 implicit space-register addressing. Set space-register bits on opcodes
141 using implicit space-register addressing. Add various missing pa20
142 long-immediate opcodes. Remove various opcodes using implicit 3-bit
143 space-register addressing. Use "fE" instead of "fe" in various
146 2005-07-18 Jan Beulich <jbeulich@novell.com>
148 * i386.h (i386_optab): Operands of aam and aad are unsigned.
150 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
152 * i386.h (i386_optab): Support Intel VMX Instructions.
154 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
156 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
158 2005-07-05 Jan Beulich <jbeulich@novell.com>
160 * i386.h (i386_optab): Add new insns.
162 2005-07-01 Nick Clifton <nickc@redhat.com>
164 * sparc.h: Add typedefs to structure declarations.
166 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
169 * i386.h (i386_optab): Update comments for 64bit addressing on
170 mov. Allow 64bit addressing for mov and movq.
172 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
174 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
175 respectively, in various floating-point load and store patterns.
177 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
179 * hppa.h (FLAG_STRICT): Correct comment.
180 (pa_opcodes): Update load and store entries to allow both PA 1.X and
181 PA 2.0 mneumonics when equivalent. Entries with cache control
182 completers now require PA 1.1. Adjust whitespace.
184 2005-05-19 Anton Blanchard <anton@samba.org>
186 * ppc.h (PPC_OPCODE_POWER5): Define.
188 2005-05-10 Nick Clifton <nickc@redhat.com>
190 * Update the address and phone number of the FSF organization in
191 the GPL notices in the following files:
192 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
193 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
194 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
195 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
196 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
197 tic54x.h, tic80.h, v850.h, vax.h
199 2005-05-09 Jan Beulich <jbeulich@novell.com>
201 * i386.h (i386_optab): Add ht and hnt.
203 2005-04-18 Mark Kettenis <kettenis@gnu.org>
205 * i386.h: Insert hyphens into selected VIA PadLock extensions.
206 Add xcrypt-ctr. Provide aliases without hyphens.
208 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
210 Moved from ../ChangeLog
212 2005-04-12 Paul Brook <paul@codesourcery.com>
213 * m88k.h: Rename psr macros to avoid conflicts.
215 2005-03-12 Zack Weinberg <zack@codesourcery.com>
216 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
217 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
220 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
221 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
222 Remove redundant instruction types.
223 (struct argument): X_op - new field.
224 (struct cst4_entry): Remove.
225 (no_op_insn): Declare.
227 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
228 * crx.h (enum argtype): Rename types, remove unused types.
230 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
231 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
232 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
233 (enum operand_type): Rearrange operands, edit comments.
234 replace us<N> with ui<N> for unsigned immediate.
235 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
236 displacements (respectively).
237 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
238 (instruction type): Add NO_TYPE_INS.
239 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
240 (operand_entry): New field - 'flags'.
241 (operand flags): New.
243 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
244 * crx.h (operand_type): Remove redundant types i3, i4,
246 Add new unsigned immediate types us3, us4, us5, us16.
248 2005-04-12 Mark Kettenis <kettenis@gnu.org>
250 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
251 adjust them accordingly.
253 2005-04-01 Jan Beulich <jbeulich@novell.com>
255 * i386.h (i386_optab): Add rdtscp.
257 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
259 * i386.h (i386_optab): Don't allow the `l' suffix for moving
260 between memory and segment register. Allow movq for moving between
261 general-purpose register and segment register.
263 2005-02-09 Jan Beulich <jbeulich@novell.com>
266 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
267 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
270 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
272 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
273 * cgen.h (enum cgen_parse_operand_type): Add
274 CGEN_PARSE_OPERAND_SYMBOLIC.
276 2005-01-21 Fred Fish <fnf@specifixinc.com>
278 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
279 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
280 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
282 2005-01-19 Fred Fish <fnf@specifixinc.com>
284 * mips.h (struct mips_opcode): Add new pinfo2 member.
285 (INSN_ALIAS): New define for opcode table entries that are
286 specific instances of another entry, such as 'move' for an 'or'
288 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
289 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
291 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
293 * mips.h (CPU_RM9000): Define.
294 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
296 2004-11-25 Jan Beulich <jbeulich@novell.com>
298 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
299 to/from test registers are illegal in 64-bit mode. Add missing
300 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
301 (previously one had to explicitly encode a rex64 prefix). Re-enable
302 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
303 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
305 2004-11-23 Jan Beulich <jbeulich@novell.com>
307 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
308 available only with SSE2. Change the MMX additions introduced by SSE
309 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
310 instructions by their now designated identifier (since combining i686
311 and 3DNow! does not really imply 3DNow!A).
313 2004-11-19 Alan Modra <amodra@bigpond.net.au>
315 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
316 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
318 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
319 Vineet Sharma <vineets@noida.hcltech.com>
321 * maxq.h: New file: Disassembly information for the maxq port.
323 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
325 * i386.h (i386_optab): Put back "movzb".
327 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
329 * cris.h (enum cris_insn_version_usage): Tweak formatting and
330 comments. Remove member cris_ver_sim. Add members
331 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
332 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
333 (struct cris_support_reg, struct cris_cond15): New types.
334 (cris_conds15): Declare.
335 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
336 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
337 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
338 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
339 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
342 2004-11-04 Jan Beulich <jbeulich@novell.com>
344 * i386.h (sldx_Suf): Remove.
345 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
346 (q_FP): Define, implying no REX64.
347 (x_FP, sl_FP): Imply FloatMF.
348 (i386_optab): Split reg and mem forms of moving from segment registers
349 so that the memory forms can ignore the 16-/32-bit operand size
350 distinction. Adjust a few others for Intel mode. Remove *FP uses from
351 all non-floating-point instructions. Unite 32- and 64-bit forms of
352 movsx, movzx, and movd. Adjust floating point operations for the above
353 changes to the *FP macros. Add DefaultSize to floating point control
354 insns operating on larger memory ranges. Remove left over comments
355 hinting at certain insns being Intel-syntax ones where the ones
356 actually meant are already gone.
358 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
360 * crx.h: Add COPS_REG_INS - Coprocessor Special register
363 2004-09-30 Paul Brook <paul@codesourcery.com>
365 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
366 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
368 2004-09-11 Theodore A. Roth <troth@openavr.org>
370 * avr.h: Add support for
371 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
373 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
375 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
377 2004-08-24 Dmitry Diky <diwil@spec.ru>
379 * msp430.h (msp430_opc): Add new instructions.
380 (msp430_rcodes): Declare new instructions.
381 (msp430_hcodes): Likewise..
383 2004-08-13 Nick Clifton <nickc@redhat.com>
386 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
389 2004-08-30 Michal Ludvig <mludvig@suse.cz>
391 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
393 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
395 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
397 2004-07-21 Jan Beulich <jbeulich@novell.com>
399 * i386.h: Adjust instruction descriptions to better match the
402 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
404 * arm.h: Remove all old content. Replace with architecture defines
405 from gas/config/tc-arm.c.
407 2004-07-09 Andreas Schwab <schwab@suse.de>
409 * m68k.h: Fix comment.
411 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
415 2004-06-24 Alan Modra <amodra@bigpond.net.au>
417 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
419 2004-05-24 Peter Barada <peter@the-baradas.com>
421 * m68k.h: Add 'size' to m68k_opcode.
423 2004-05-05 Peter Barada <peter@the-baradas.com>
425 * m68k.h: Switch from ColdFire chip name to core variant.
427 2004-04-22 Peter Barada <peter@the-baradas.com>
429 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
430 descriptions for new EMAC cases.
431 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
432 handle Motorola MAC syntax.
433 Allow disassembly of ColdFire V4e object files.
435 2004-03-16 Alan Modra <amodra@bigpond.net.au>
437 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
439 2004-03-12 Jakub Jelinek <jakub@redhat.com>
441 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
443 2004-03-12 Michal Ludvig <mludvig@suse.cz>
445 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
447 2004-03-12 Michal Ludvig <mludvig@suse.cz>
449 * i386.h (i386_optab): Added xstore/xcrypt insns.
451 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
453 * h8300.h (32bit ldc/stc): Add relaxing support.
455 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
457 * h8300.h (BITOP): Pass MEMRELAX flag.
459 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
461 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
464 For older changes see ChangeLog-9103
470 version-control: never