1 2015-06-19 Peter Bergner <bergner@vnet.ibm.com>
3 * ppc.h (PPC_OPERAND_OPTIONAL_VALUE): New.
4 (ppc_optional_operand_value): New inline function.
6 2015-06-04 Matthew Wahab <matthew.wahab@arm.com>
8 * aarch64.h (AARCH64_V8_1): New.
10 2015-06-03 Matthew Wahab <matthew.wahab@arm.com>
12 * arm.h (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1): New.
13 (ARM_ARCH_V8_1A): New.
14 (ARM_ARCH_V8_1A_FP): New.
15 (ARM_ARCH_V8_1A_SIMD): New.
16 (ARM_ARCH_V8_1A_CRYPTOV1): New.
17 (ARM_FEATURE_CORE): New.
19 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
21 * arm.h (ARM_EXT2_PAN): New.
22 (ARM_FEATURE_CORE_HIGH): New.
24 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
26 * arm.h (ARM_FEATURE_ALL): New.
28 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
30 * aarch64.h (AARCH64_FEATURE_RDMA): New.
32 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
34 * aarch64.h (AARCH64_FEATURE_LOR): New.
36 2015-06-01 Matthew Wahab <matthew.wahab@arm.com>
38 * aarch64.h (AARCH64_FEATURE_PAN): New.
39 (aarch64_sys_reg_supported_p): Declare.
40 (aarch64_pstatefield_supported_p): Declare.
42 2015-04-30 DJ Delorie <dj@redhat.com>
44 * rl78.h (RL78_Dis_Isa): New.
45 (rl78_decode_opcode): Add ISA parameter.
47 2015-03-24 Terry Guo <terry.guo@arm.com>
49 * arm.h (arm_feature_set): Extended to provide more available bits.
50 (ARM_ANY): Updated to follow above new definition.
51 (ARM_CPU_HAS_FEATURE): Likewise.
52 (ARM_CPU_IS_ANY): Likewise.
53 (ARM_MERGE_FEATURE_SETS): Likewise.
54 (ARM_CLEAR_FEATURE): Likewise.
55 (ARM_FEATURE): Likewise.
56 (ARM_FEATURE_COPY): New macro.
57 (ARM_FEATURE_EQUAL): Likewise.
58 (ARM_FEATURE_ZERO): Likewise.
59 (ARM_FEATURE_CORE_EQUAL): Likewise.
60 (ARM_FEATURE_LOW): Likewise.
61 (ARM_FEATURE_CORE_LOW): Likewise.
62 (ARM_FEATURE_CORE_COPROC): Likewise.
64 2015-02-19 Pedro Alves <palves@redhat.com>
66 * cgen.h [__cplusplus]: Wrap in extern "C".
67 * msp430-decode.h [__cplusplus]: Likewise.
68 * nios2.h [__cplusplus]: Likewise.
69 * rl78.h [__cplusplus]: Likewise.
70 * rx.h [__cplusplus]: Likewise.
71 * tilegx.h [__cplusplus]: Likewise.
73 2015-01-28 James Bowman <james.bowman@ftdichip.com>
77 2015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
79 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13.
81 2015-01-01 Alan Modra <amodra@gmail.com>
83 Update year range in copyright notice of all files.
85 2014-12-27 Anthony Green <green@moxielogic.com>
87 * moxie.h (MOXIE_F1_AiB2, MOXIE_F1_ABi2): Renamed from
88 MOXIE_F1_AiB4 and MOXIE_F1_ABi2.
90 2014-12-06 Eric Botcazou <ebotcazou@adacore.com>
94 2014-11-28 Sandra Loosemore <sandra@codesourcery.com>
96 * nios2.h (NIOS2_INSN_ADDI, NIOS2_INSN_ANDI): Delete.
97 (NIOS2_INSN_ORI, NIOS2_INSN_XORI): Delete.
98 (NIOS2_INSN_OPTARG): Renumber.
100 2014-11-06 Sandra Loosemore <sandra@codesourcery.com>
102 * nios2.h (nios2_find_opcode_hash): Add mach parameter to
103 declaration. Fix obsolete comment.
105 2014-10-23 Sandra Loosemore <sandra@codesourcery.com>
107 * nios2.h (enum iw_format_type): New.
108 (struct nios2_opcode): Update comments. Add size and format fields.
109 (NIOS2_INSN_OPTARG): New.
110 (REG_NORMAL, REG_CONTROL, REG_COPROCESSOR): New.
111 (struct nios2_reg): Add regtype field.
112 (GET_INSN_FIELD, SET_INSN_FIELD): Delete.
113 (IW_A_LSB, IW_A_MSB, IW_A_SZ, IW_A_MASK): Delete.
114 (IW_B_LSB, IW_B_MSB, IW_B_SZ, IW_B_MASK): Delete.
115 (IW_C_LSB, IW_C_MSB, IW_C_SZ, IW_C_MASK): Delete.
116 (IW_IMM16_LSB, IW_IMM16_MSB, IW_IMM16_SZ, IW_IMM16_MASK): Delete.
117 (IW_IMM26_LSB, IW_IMM26_MSB, IW_IMM26_SZ, IW_IMM26_MASK): Delete.
118 (IW_OP_LSB, IW_OP_MSB, IW_OP_SZ, IW_OP_MASK): Delete.
119 (IW_OPX_LSB, IW_OPX_MSB, IW_OPX_SZ, IW_OPX_MASK): Delete.
120 (IW_SHIFT_IMM5_LSB, IW_SHIFT_IMM5_MSB): Delete.
121 (IW_SHIFT_IMM5_SZ, IW_SHIFT_IMM5_MASK): Delete.
122 (IW_CONTROL_REGNUM_LSB, IW_CONTROL_REGNUM_MSB): Delete.
123 (IW_CONTROL_REGNUM_SZ, IW_CONTROL_REGNUM_MASK): Delete.
124 (OP_MASK_OP, OP_SH_OP): Delete.
125 (OP_MASK_IOP, OP_SH_IOP): Delete.
126 (OP_MASK_IRD, OP_SH_IRD): Delete.
127 (OP_MASK_IRT, OP_SH_IRT): Delete.
128 (OP_MASK_IRS, OP_SH_IRS): Delete.
129 (OP_MASK_ROP, OP_SH_ROP): Delete.
130 (OP_MASK_RRD, OP_SH_RRD): Delete.
131 (OP_MASK_RRT, OP_SH_RRT): Delete.
132 (OP_MASK_RRS, OP_SH_RRS): Delete.
133 (OP_MASK_JOP, OP_SH_JOP): Delete.
134 (OP_MASK_IMM26, OP_SH_IMM26): Delete.
135 (OP_MASK_RCTL, OP_SH_RCTL): Delete.
136 (OP_MASK_IMM5, OP_SH_IMM5): Delete.
137 (OP_MASK_CACHE_OPX, OP_SH_CACHE_OPX): Delete.
138 (OP_MASK_CACHE_RRS, OP_SH_CACHE_RRS): Delete.
139 (OP_MASK_CUSTOM_A, OP_SH_CUSTOM_A): Delete.
140 (OP_MASK_CUSTOM_B, OP_SH_CUSTOM_B): Delete.
141 (OP_MASK_CUSTOM_C, OP_SH_CUSTOM_C): Delete.
142 (OP_MASK_CUSTOM_N, OP_SH_CUSTOM_N): Delete.
143 (OP_<insn>, OPX_<insn>, OP_MATCH_<insn>, OPX_MATCH_<insn>): Delete.
144 (OP_MASK_<insn>, OP_MASK): Delete.
145 (GET_IW_A, GET_IW_B, GET_IW_C, GET_IW_CONTROL_REGNUM): Delete.
146 (GET_IW_IMM16, GET_IW_IMM26, GET_IW_OP, GET_IW_OPX): Delete.
147 Include nios2r1.h to define new instruction opcode constants
149 (nios2_builtin_opcodes): Rename to nios2_r1_opcodes.
150 (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
151 (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
152 (NUMOPCODES, NUMREGISTERS): Delete.
153 * nios2r1.h: New file.
155 2014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com>
157 * sparc.h (HWCAP2_VIS3B): Documentation improved.
159 2014-10-09 Jose E. Marchesi <jose.marchesi@oracle.com>
161 * sparc.h (sparc_opcode): new field `hwcaps2'.
162 (HWCAP2_FJATHPLUS): New define.
163 (HWCAP2_VIS3B): Likewise.
164 (HWCAP2_ADP): Likewise.
165 (HWCAP2_SPARC5): Likewise.
166 (HWCAP2_MWAIT): Likewise.
167 (HWCAP2_XMPMUL): Likewise.
168 (HWCAP2_XMONT): Likewise.
169 (HWCAP2_NSEC): Likewise.
170 (HWCAP2_FJATHHPC): Likewise.
171 (HWCAP2_FJDES): Likewise.
172 (HWCAP2_FJAES): Likewise.
173 Document the new operand kind `{', corresponding to the mcdper
174 ancillary state register.
175 Document the new operand kind }, which represents frsd floating
176 point registers (double precision) which must be the same than
177 frs1 in its containing instruction.
179 2014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
181 * nds32.h: Add new opcode declaration.
183 2014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
184 Matthew Fortune <matthew.fortune@imgtec.com>
186 * mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT,
187 OP_CHECK_PREV and OP_NON_ZERO_REG. Add descriptions for the MIPS R6
188 instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B,
189 +I, +O, +R, +:, +\, +", +;
190 (mips_check_prev_operand): New struct.
191 (INSN2_FORBIDDEN_SLOT): New define.
192 (INSN_ISA32R6): New define.
193 (INSN_ISA64R6): New define.
194 (INSN_UPTO32R6): New define.
195 (INSN_UPTO64R6): New define.
196 (mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6.
197 (ISA_MIPS32R6): New define.
198 (ISA_MIPS64R6): New define.
199 (CPU_MIPS32R6): New define.
200 (CPU_MIPS64R6): New define.
201 (cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6.
203 2014-09-03 Jiong Wang <jiong.wang@arm.com>
205 * aarch64.h (AARCH64_FEATURE_LSE): New feature added.
206 (aarch64_opnd): Add AARCH64_OPND_PAIRREG.
207 (aarch64_insn_class): Add lse_atomic.
208 (F_LSE_SZ): New field added.
209 (opcode_has_special_coder): Recognize F_LSE_SZ.
211 2014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
213 * mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B'
216 2014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
218 * mips.h (INSN_LOAD_COPROC_DELAY): Rename to...
219 (INSN_LOAD_COPROC): New define.
220 (INSN_COPROC_MOVE_DELAY): Rename to...
221 (INSN_COPROC_MOVE): New define.
223 2014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
224 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
225 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
226 Soundararajan <Sounderarajan.D@atmel.com>
228 * avr.h (AVR_ISA_TINY): Define avrtiny specific ISA.
229 (AVR_ISA_2xxxa): Define ISA without LPM.
230 (AVR_ISA_AVRTINY): Define avrtiny arch ISA.
231 Add doc for contraint used in 16 bit lds/sts.
232 Adjust ISA group for icall, ijmp, pop and push.
233 Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints.
235 2014-05-19 Nick Clifton <nickc@redhat.com>
237 * msp430.h (struct msp430_operand_s): Add vshift field.
239 2014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
241 * mips.h (INSN_ISA_MASK): Updated.
242 (INSN_ISA32R3): New define.
243 (INSN_ISA32R5): New define.
244 (INSN_ISA64R3): New define.
245 (INSN_ISA64R5): New define.
246 (INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
247 INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
248 (mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
250 (INSN_UPTO32R3): New define.
251 (INSN_UPTO32R5): New define.
252 (INSN_UPTO64R3): New define.
253 (INSN_UPTO64R5): New define.
254 (ISA_MIPS32R3): New define.
255 (ISA_MIPS32R5): New define.
256 (ISA_MIPS64R3): New define.
257 (ISA_MIPS64R5): New define.
258 (CPU_MIPS32R3): New define.
259 (CPU_MIPS32R5): New define.
260 (CPU_MIPS64R3): New define.
261 (CPU_MIPS64R5): New define.
263 2014-05-01 Richard Sandiford <rdsandiford@googlemail.com>
265 * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values.
267 2014-04-22 Christian Svensson <blue@cmd.nu>
271 2014-03-05 Alan Modra <amodra@gmail.com>
273 Update copyright years.
275 2013-12-16 Andrew Bennett <andrew.bennett@imgtec.com>
277 * mips.h: Updated description of +o, +u, +v and +w for MIPS and
280 2013-12-13 Kuan-Lin Chen <kuanlinchentw@gmail.com>
281 Wei-Cheng Wang <cole945@gmail.com>
283 * nds32.h: New file for Andes NDS32.
285 2013-12-07 Mike Frysinger <vapier@gentoo.org>
287 * bfin.h: Remove +x file mode.
289 2013-11-20 Yufeng Zhang <yufeng.zhang@arm.com>
291 * aarch64.h (aarch64_pstatefields): Change element type to
294 2013-11-18 Renlin Li <Renlin.Li@arm.com>
296 * arm.h (ARM_AEXT_V7VE): New define.
297 (ARM_ARCH_V7VE): New define.
298 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
300 2013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
304 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
306 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
307 (aarch64_sys_reg_writeonly_p): Ditto.
309 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
311 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
312 (aarch64_sys_reg_writeonly_p): Ditto.
314 2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
316 * aarch64.h (aarch64_sys_reg): New typedef.
317 (aarch64_sys_regs): Change to define with the new type.
318 (aarch64_sys_reg_deprecated_p): Declare.
320 2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
322 * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
323 (enum aarch64_opnd): Add AARCH64_OPND_COND1.
325 2013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
327 * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
328 (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
329 For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
330 +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
331 For MIPS, update extension character sequences after +.
332 (ASE_MSA): New define.
333 (ASE_MSA64): New define.
334 For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
335 +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
336 For microMIPS, update extension character sequences after +.
338 2013-08-23 Yuri Chornoivan <yurchor@ukr.net>
343 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
345 * mips.h: Remove references to "+I" and imm2_expr.
347 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
349 * mips.h (M_DEXT, M_DINS): Delete.
351 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
353 * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
354 (mips_optional_operand_p): New function.
356 2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
357 Richard Sandiford <rdsandiford@googlemail.com>
359 * mips.h: Document new VU0 operand characters.
360 (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
361 (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
362 (OP_REG_R5900_ACC): New mips_reg_operand_types.
363 (INSN2_VU0_CHANNEL_SUFFIX): New macro.
364 (mips_vu0_channel_mask): Declare.
366 2013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
368 * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
369 (mips_int_operand_min, mips_int_operand_max): New functions.
370 (mips_decode_pcrel_operand): Use mips_decode_int_operand.
372 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
374 * mips.h (mips_decode_reg_operand): New function.
375 (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
376 (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
377 (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
379 (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
380 (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
381 (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
382 (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
383 (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
384 (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
385 (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
386 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
387 (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
388 (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
389 macros to cover the gaps.
390 (INSN2_MOD_SP): Replace with...
391 (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
392 (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
393 (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
394 (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
395 (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
398 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
400 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
401 (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
402 (MIPS16_INSN_COND_BRANCH): Delete.
404 2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
405 Kirill Yukhin <kirill.yukhin@intel.com>
406 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
408 * i386.h (BND_PREFIX_OPCODE): New.
410 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
412 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
413 OP_SAVE_RESTORE_LIST.
414 (decode_mips16_operand): Declare.
416 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
418 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
419 (mips_operand, mips_int_operand, mips_mapped_int_operand)
420 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
421 (mips_pcrel_operand): New structures.
422 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
423 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
424 (decode_mips_operand, decode_micromips_operand): Declare.
426 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
428 * mips.h: Document MIPS16 "I" opcode.
430 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
432 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
433 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
434 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
435 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
436 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
437 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
438 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
439 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
440 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
441 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
442 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
443 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
444 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
446 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
447 (M_USD_AB): ...these.
449 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
451 * mips.h: Remove documentation of "[" and "]". Update documentation
452 of "k" and the MDMX formats.
454 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
456 * mips.h: Update documentation of "+s" and "+S".
458 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
460 * mips.h: Document "+i".
462 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
464 * mips.h: Remove "mi" documentation. Update "mh" documentation.
465 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
467 (INSN2_WRITE_GPR_MHI): Rename to...
468 (INSN2_WRITE_GPR_MH): ...this.
470 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
472 * mips.h: Remove documentation of "+D" and "+T".
474 2013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
476 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
477 Use "source" rather than "destination" for microMIPS "G".
479 2013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
481 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
484 2013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
486 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
488 2013-06-17 Catherine Moore <clm@codesourcery.com>
489 Maciej W. Rozycki <macro@codesourcery.com>
490 Chao-Ying Fu <fu@mips.com>
492 * mips.h (OP_SH_EVAOFFSET): Define.
493 (OP_MASK_EVAOFFSET): Define.
494 (INSN_ASE_MASK): Delete.
496 (M_CACHEE_AB, M_CACHEE_OB): New.
497 (M_LBE_OB, M_LBE_AB): New.
498 (M_LBUE_OB, M_LBUE_AB): New.
499 (M_LHE_OB, M_LHE_AB): New.
500 (M_LHUE_OB, M_LHUE_AB): New.
501 (M_LLE_AB, M_LLE_OB): New.
502 (M_LWE_OB, M_LWE_AB): New.
503 (M_LWLE_AB, M_LWLE_OB): New.
504 (M_LWRE_AB, M_LWRE_OB): New.
505 (M_PREFE_AB, M_PREFE_OB): New.
506 (M_SCE_AB, M_SCE_OB): New.
507 (M_SBE_OB, M_SBE_AB): New.
508 (M_SHE_OB, M_SHE_AB): New.
509 (M_SWE_OB, M_SWE_AB): New.
510 (M_SWLE_AB, M_SWLE_OB): New.
511 (M_SWRE_AB, M_SWRE_OB): New.
512 (MICROMIPSOP_SH_EVAOFFSET): Define.
513 (MICROMIPSOP_MASK_EVAOFFSET): Define.
515 2013-06-12 Sandra Loosemore <sandra@codesourcery.com>
517 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
519 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
521 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
523 2013-05-09 Andrew Pinski <apinski@cavium.com>
525 * mips.h (OP_MASK_CODE10): Correct definition.
526 (OP_SH_CODE10): Likewise.
527 Add a comment that "+J" is used now for OP_*CODE10.
528 (INSN_ASE_MASK): Update.
529 (INSN_VIRT): New macro.
530 (INSN_VIRT64): New macro
532 2013-05-02 Nick Clifton <nickc@redhat.com>
534 * msp430.h: Add patterns for MSP430X instructions.
536 2013-04-06 David S. Miller <davem@davemloft.net>
538 * sparc.h (F_PREFERRED): Define.
539 (F_PREF_ALIAS): Define.
541 2013-04-03 Nick Clifton <nickc@redhat.com>
543 * v850.h (V850_INVERSE_PCREL): Define.
545 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
548 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
550 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
553 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
555 * tic6xc-opcode-table.h: Add 16-bit insns.
556 * tic6x.h: Add support for 16-bit insns.
558 2013-03-21 Michael Schewe <michael.schewe@gmx.net>
560 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
561 and mov.b/w/l Rs,@(d:32,ERd).
563 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
566 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
567 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
568 tic6x_operand_xregpair operand coding type.
569 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
570 opcode field, usu ORXREGD1324 for the src2 operand and remove the
573 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
576 * tic6x.h (enum tic6x_coding_method): Add
577 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
578 separately the msb and lsb of a register pair. This is needed to
579 encode the opcodes in the same way as TI assembler does.
580 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
581 and rsqrdp opcodes to use the new field coding types.
583 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
585 * arm.h (CRC_EXT_ARMV8): New constant.
586 (ARCH_CRC_ARMV8): New macro.
588 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
590 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
592 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
593 Andrew Jenner <andrew@codesourcery.com>
595 Based on patches from Altera Corporation.
599 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
601 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
603 2013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
606 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
608 2013-01-24 Nick Clifton <nickc@redhat.com>
610 * v850.h: Add e3v5 support.
612 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
614 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
616 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
618 * ppc.h (PPC_OPCODE_POWER8): New define.
619 (PPC_OPCODE_HTM): Likewise.
621 2013-01-10 Will Newton <will.newton@imgtec.com>
625 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
627 * cr16.h (make_instruction): Rename to cr16_make_instruction.
628 (match_opcode): Rename to cr16_match_opcode.
630 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
632 * mips.h: Add support for r5900 instructions including lq and sq.
634 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
636 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
637 (make_instruction,match_opcode): Added function prototypes.
638 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
640 2012-11-23 Alan Modra <amodra@gmail.com>
642 * ppc.h (ppc_parse_cpu): Update prototype.
644 2012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
646 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
647 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
649 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
651 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
653 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
655 * ia64.h (ia64_opnd): Add new operand types.
657 2012-08-21 David S. Miller <davem@davemloft.net>
659 * sparc.h (F3F4): New macro.
661 2012-08-13 Ian Bolton <ian.bolton@arm.com>
662 Laurent Desnogues <laurent.desnogues@arm.com>
663 Jim MacArthur <jim.macarthur@arm.com>
664 Marcus Shawcroft <marcus.shawcroft@arm.com>
665 Nigel Stephens <nigel.stephens@arm.com>
666 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
667 Richard Earnshaw <rearnsha@arm.com>
668 Sofiane Naci <sofiane.naci@arm.com>
669 Tejas Belagod <tejas.belagod@arm.com>
670 Yufeng Zhang <yufeng.zhang@arm.com>
672 * aarch64.h: New file.
674 2012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
675 Maciej W. Rozycki <macro@codesourcery.com>
677 * mips.h (mips_opcode): Add the exclusions field.
678 (OPCODE_IS_MEMBER): Remove macro.
679 (cpu_is_member): New inline function.
680 (opcode_is_member): Likewise.
682 2012-07-31 Chao-Ying Fu <fu@mips.com>
683 Catherine Moore <clm@codesourcery.com>
684 Maciej W. Rozycki <macro@codesourcery.com>
686 * mips.h: Document microMIPS DSP ASE usage.
687 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
688 microMIPS DSP ASE support.
689 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
690 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
691 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
692 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
693 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
694 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
695 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
697 2012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
699 * mips.h: Fix a typo in description.
701 2012-06-07 Georg-Johann Lay <avr@gjlay.de>
703 * avr.h: (AVR_ISA_XCH): New define.
704 (AVR_ISA_XMEGA): Use it.
705 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
707 2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
709 * m68hc11.h: Add XGate definitions.
710 (struct m68hc11_opcode): Add xg_mask field.
712 2012-05-14 Catherine Moore <clm@codesourcery.com>
713 Maciej W. Rozycki <macro@codesourcery.com>
714 Rhonda Wittels <rhonda@codesourcery.com>
716 * ppc.h (PPC_OPCODE_VLE): New definition.
717 (PPC_OP_SA): New macro.
718 (PPC_OP_SE_VLE): New macro.
719 (PPC_OP): Use a variable shift amount.
720 (powerpc_operand): Update comments.
721 (PPC_OPSHIFT_INV): New macro.
722 (PPC_OPERAND_CR): Replace with...
723 (PPC_OPERAND_CR_BIT): ...this and
724 (PPC_OPERAND_CR_REG): ...this.
727 2012-05-03 Sean Keys <skeys@ipdatasys.com>
729 * xgate.h: Header file for XGATE assembler.
731 2012-04-27 David S. Miller <davem@davemloft.net>
733 * sparc.h: Document new arg code' )' for crypto RS3
736 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
737 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
738 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
739 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
740 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
741 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
742 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
743 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
744 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
745 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
746 HWCAP_CBCOND, HWCAP_CRC32): New defines.
748 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
750 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
752 2012-02-27 Alan Modra <amodra@gmail.com>
754 * crx.h (cst4_map): Update declaration.
756 2012-02-25 Walter Lee <walt@tilera.com>
758 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
760 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
761 TILEPRO_OPC_LW_TLS_SN.
763 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
765 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
766 (XRELEASE_PREFIX_OPCODE): Likewise.
768 2011-12-08 Andrew Pinski <apinski@cavium.com>
769 Adam Nemet <anemet@caviumnetworks.com>
771 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
772 (INSN_OCTEON2): New macro.
773 (CPU_OCTEON2): New macro.
774 (OPCODE_IS_MEMBER): Add Octeon2.
776 2011-11-29 Andrew Pinski <apinski@cavium.com>
778 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
779 (INSN_OCTEONP): New macro.
780 (CPU_OCTEONP): New macro.
781 (OPCODE_IS_MEMBER): Add Octeon+.
782 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
784 2011-11-01 DJ Delorie <dj@redhat.com>
788 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
790 * mips.h: Fix a typo in description.
792 2011-09-21 David S. Miller <davem@davemloft.net>
794 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
795 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
796 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
797 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
799 2011-08-09 Chao-ying Fu <fu@mips.com>
800 Maciej W. Rozycki <macro@codesourcery.com>
802 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
803 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
804 (INSN_ASE_MASK): Add the MCU bit.
805 (INSN_MCU): New macro.
806 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
807 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
809 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
811 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
812 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
813 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
814 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
815 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
816 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
817 (INSN2_READ_GPR_MMN): Likewise.
818 (INSN2_READ_FPR_D): Change the bit used.
819 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
820 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
821 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
822 (INSN2_COND_BRANCH): Likewise.
823 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
824 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
825 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
826 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
827 (INSN2_MOD_GPR_MN): Likewise.
829 2011-08-05 David S. Miller <davem@davemloft.net>
831 * sparc.h: Document new format codes '4', '5', and '('.
832 (OPF_LOW4, RS3): New macros.
834 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
836 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
837 order of flags documented.
839 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
841 * mips.h: Clarify the description of microMIPS instruction
843 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
845 2011-07-24 Chao-ying Fu <fu@mips.com>
846 Maciej W. Rozycki <macro@codesourcery.com>
848 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
849 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
850 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
851 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
852 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
853 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
854 (OP_MASK_RS3, OP_SH_RS3): Likewise.
855 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
856 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
857 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
858 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
859 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
860 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
861 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
862 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
863 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
864 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
865 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
866 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
867 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
868 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
869 (INSN_WRITE_GPR_S): New macro.
870 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
871 (INSN2_READ_FPR_D): Likewise.
872 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
873 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
874 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
875 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
876 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
877 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
878 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
879 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
880 (CPU_MICROMIPS): New macro.
881 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
882 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
883 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
884 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
885 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
886 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
887 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
888 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
889 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
890 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
891 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
892 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
893 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
894 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
895 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
896 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
897 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
898 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
899 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
900 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
901 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
902 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
903 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
904 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
905 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
906 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
907 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
908 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
909 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
910 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
911 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
912 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
913 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
914 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
915 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
916 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
917 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
918 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
919 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
920 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
921 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
922 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
923 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
924 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
925 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
926 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
927 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
928 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
929 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
930 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
931 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
932 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
933 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
934 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
935 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
936 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
937 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
938 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
939 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
940 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
941 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
942 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
943 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
944 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
945 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
946 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
947 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
948 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
949 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
950 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
951 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
952 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
953 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
954 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
955 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
956 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
957 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
958 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
959 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
960 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
961 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
962 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
963 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
964 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
965 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
966 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
967 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
968 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
969 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
970 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
971 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
972 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
973 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
974 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
975 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
976 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
977 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
978 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
979 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
980 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
981 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
982 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
983 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
984 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
985 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
986 (micromips_opcodes): New declaration.
987 (bfd_micromips_num_opcodes): Likewise.
989 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
991 * mips.h (INSN_TRAP): Rename to...
992 (INSN_NO_DELAY_SLOT): ... this.
993 (INSN_SYNC): Remove macro.
995 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
997 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
998 a duplicate of AVR_ISA_SPM.
1000 2011-07-01 Nick Clifton <nickc@redhat.com>
1002 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
1004 2011-06-18 Robin Getz <robin.getz@analog.com>
1006 * bfin.h (is_macmod_signed): New func
1008 2011-06-18 Mike Frysinger <vapier@gentoo.org>
1010 * bfin.h (is_macmod_pmove): Add missing space before func args.
1011 (is_macmod_hmove): Likewise.
1013 2011-06-13 Walter Lee <walt@tilera.com>
1015 * tilegx.h: New file.
1016 * tilepro.h: New file.
1018 2011-05-31 Paul Brook <paul@codesourcery.com>
1020 * arm.h (ARM_ARCH_V7R_IDIV): Define.
1022 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1024 * s390.h: Replace S390_OPERAND_REG_EVEN with
1025 S390_OPERAND_REG_PAIR.
1027 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1029 * s390.h: Add S390_OPCODE_REG_EVEN flag.
1031 2011-04-18 Julian Brown <julian@codesourcery.com>
1033 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
1035 2011-04-11 Dan McDonald <dan@wellkeeper.com>
1038 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
1040 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
1042 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
1043 New instruction set flags.
1044 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
1046 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
1048 * mips.h (M_PREF_AB): New enum value.
1050 2011-02-12 Mike Frysinger <vapier@gentoo.org>
1052 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
1054 (is_macmod_pmove, is_macmod_hmove): New functions.
1056 2011-02-11 Mike Frysinger <vapier@gentoo.org>
1058 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
1060 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
1062 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
1063 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
1065 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1068 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
1071 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1074 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
1076 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
1078 * mips.h: Update commentary after last commit.
1080 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
1082 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
1083 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
1084 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
1086 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1088 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
1090 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
1092 * mips.h: Fix previous commit.
1094 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
1096 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
1097 (INSN_LOONGSON_3A): Clear bit 31.
1099 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1102 * arm.h (ARM_AEXT_V6M_ONLY): New define.
1103 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
1104 (ARM_ARCH_V6M_ONLY): New define.
1106 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
1108 * mips.h (INSN_LOONGSON_3A): Defined.
1109 (CPU_LOONGSON_3A): Defined.
1110 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
1112 2010-10-09 Matt Rice <ratmice@gmail.com>
1114 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
1115 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
1117 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1119 * arm.h (ARM_EXT_VIRT): New define.
1120 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
1121 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
1124 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1126 * arm.h (ARM_AEXT_ADIV): New define.
1127 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
1129 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1131 * arm.h (ARM_EXT_OS): New define.
1132 (ARM_AEXT_V6SM): Likewise.
1133 (ARM_ARCH_V6SM): Likewise.
1135 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1137 * arm.h (ARM_EXT_MP): Add.
1138 (ARM_ARCH_V7A_MP): Likewise.
1140 2010-09-22 Mike Frysinger <vapier@gentoo.org>
1142 * bfin.h: Declare pseudoChr structs/defines.
1144 2010-09-21 Mike Frysinger <vapier@gentoo.org>
1146 * bfin.h: Strip trailing whitespace.
1148 2010-07-29 DJ Delorie <dj@redhat.com>
1150 * rx.h (RX_Operand_Type): Add TwoReg.
1151 (RX_Opcode_ID): Remove ediv and ediv2.
1153 2010-07-27 DJ Delorie <dj@redhat.com>
1155 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
1157 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
1158 Ina Pandit <ina.pandit@kpitcummins.com>
1160 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
1161 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
1162 PROCESSOR_V850E2_ALL.
1163 Remove PROCESSOR_V850EA support.
1164 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
1165 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
1166 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
1167 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
1168 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
1169 V850_OPERAND_PERCENT.
1170 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
1172 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
1175 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
1177 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
1178 (MIPS16_INSN_BRANCH): Rename to...
1179 (MIPS16_INSN_COND_BRANCH): ... this.
1181 2010-07-03 Alan Modra <amodra@gmail.com>
1183 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
1184 Renumber other PPC_OPCODE defines.
1186 2010-07-03 Alan Modra <amodra@gmail.com>
1188 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
1190 2010-06-29 Alan Modra <amodra@gmail.com>
1192 * maxq.h: Delete file.
1194 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
1196 * ppc.h (PPC_OPCODE_E500): Define.
1198 2010-05-26 Catherine Moore <clm@codesourcery.com>
1200 * opcode/mips.h (INSN_MIPS16): Remove.
1202 2010-04-21 Joseph Myers <joseph@codesourcery.com>
1204 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
1206 2010-04-15 Nick Clifton <nickc@redhat.com>
1208 * alpha.h: Update copyright notice to use GPLv3.
1214 * convex.h: Likewise.
1221 * h8300.h: Likewise.
1228 * m68hc11.h: Likewise.
1234 * mn10200.h: Likewise.
1235 * mn10300.h: Likewise.
1236 * msp430.h: Likewise.
1238 * ns32k.h: Likewise.
1240 * pdp11.h: Likewise.
1247 * score-datadep.h: Likewise.
1248 * score-inst.h: Likewise.
1249 * sparc.h: Likewise.
1250 * spu-insns.h: Likewise.
1252 * tic30.h: Likewise.
1253 * tic4x.h: Likewise.
1254 * tic54x.h: Likewise.
1255 * tic80.h: Likewise.
1259 2010-03-25 Joseph Myers <joseph@codesourcery.com>
1261 * tic6x-control-registers.h, tic6x-insn-formats.h,
1262 tic6x-opcode-table.h, tic6x.h: New.
1264 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
1266 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
1268 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
1270 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
1272 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
1274 * ia64.h (ia64_find_opcode): Remove argument name.
1275 (ia64_find_next_opcode): Likewise.
1276 (ia64_dis_opcode): Likewise.
1277 (ia64_free_opcode): Likewise.
1278 (ia64_find_dependency): Likewise.
1280 2009-11-22 Doug Evans <dje@sebabeach.org>
1282 * cgen.h: Include bfd_stdint.h.
1283 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
1285 2009-11-18 Paul Brook <paul@codesourcery.com>
1287 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
1289 2009-11-17 Paul Brook <paul@codesourcery.com>
1290 Daniel Jacobowitz <dan@codesourcery.com>
1292 * arm.h (ARM_EXT_V6_DSP): Define.
1293 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
1294 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
1296 2009-11-04 DJ Delorie <dj@redhat.com>
1298 * rx.h (rx_decode_opcode) (mvtipl): Add.
1299 (mvtcp, mvfcp, opecp): Remove.
1301 2009-11-02 Paul Brook <paul@codesourcery.com>
1303 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
1304 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
1305 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
1306 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
1307 FPU_ARCH_NEON_VFP_V4): Define.
1309 2009-10-23 Doug Evans <dje@sebabeach.org>
1311 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
1312 * cgen.h: Update. Improve multi-inclusion macro name.
1314 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
1316 * ppc.h (PPC_OPCODE_476): Define.
1318 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
1320 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1322 2009-09-29 DJ Delorie <dj@redhat.com>
1326 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
1328 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1330 2009-09-21 Ben Elliston <bje@au.ibm.com>
1332 * ppc.h (PPC_OPCODE_PPCA2): New.
1334 2009-09-05 Martin Thuresson <martin@mtme.org>
1336 * ia64.h (struct ia64_operand): Renamed member class to op_class.
1338 2009-08-29 Martin Thuresson <martin@mtme.org>
1340 * tic30.h (template): Rename type template to
1341 insn_template. Updated code to use new name.
1342 * tic54x.h (template): Rename type template to
1345 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
1347 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1349 2009-06-11 Anthony Green <green@moxielogic.com>
1351 * moxie.h (MOXIE_F3_PCREL): Define.
1352 (moxie_form3_opc_info): Grow.
1354 2009-06-06 Anthony Green <green@moxielogic.com>
1356 * moxie.h (MOXIE_F1_M): Define.
1358 2009-04-15 Anthony Green <green@moxielogic.com>
1362 2009-04-06 DJ Delorie <dj@redhat.com>
1364 * h8300.h: Add relaxation attributes to MOVA opcodes.
1366 2009-03-10 Alan Modra <amodra@bigpond.net.au>
1368 * ppc.h (ppc_parse_cpu): Declare.
1370 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
1372 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1373 and _IMM11 for mbitclr and mbitset.
1374 * score-datadep.h: Update dependency information.
1376 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
1378 * ppc.h (PPC_OPCODE_POWER7): New.
1380 2009-02-06 Doug Evans <dje@google.com>
1382 * i386.h: Add comment regarding sse* insns and prefixes.
1384 2009-02-03 Sandip Matte <sandip@rmicorp.com>
1386 * mips.h (INSN_XLR): Define.
1387 (INSN_CHIP_MASK): Update.
1389 (OPCODE_IS_MEMBER): Update.
1390 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1392 2009-01-28 Doug Evans <dje@google.com>
1394 * opcode/i386.h: Add multiple inclusion protection.
1395 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1396 (EDI_REG_NUM): New macros.
1397 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1398 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1399 (REX_PREFIX_P): New macro.
1401 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
1403 * ppc.h (struct powerpc_opcode): New field "deprecated".
1404 (PPC_OPCODE_NOPOWER4): Delete.
1406 2008-11-28 Joshua Kinard <kumba@gentoo.org>
1408 * mips.h: Define CPU_R14000, CPU_R16000.
1409 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
1411 2008-11-18 Catherine Moore <clm@codesourcery.com>
1413 * arm.h (FPU_NEON_FP16): New.
1414 (FPU_ARCH_NEON_FP16): New.
1416 2008-11-06 Chao-ying Fu <fu@mips.com>
1418 * mips.h: Doucument '1' for 5-bit sync type.
1420 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1422 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1425 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1427 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1429 2008-07-30 Michael J. Eager <eager@eagercon.com>
1431 * ppc.h (PPC_OPCODE_405): Define.
1432 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1434 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1436 * ppc.h (ppc_cpu_t): New typedef.
1437 (struct powerpc_opcode <flags>): Use it.
1438 (struct powerpc_operand <insert, extract>): Likewise.
1439 (struct powerpc_macro <flags>): Likewise.
1441 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1443 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1444 Update comment before MIPS16 field descriptors to mention MIPS16.
1445 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1447 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1448 New bit masks and shift counts for cins and exts.
1450 * mips.h: Document new field descriptors +Q.
1451 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1453 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1455 * mips.h (INSN_MACRO): Move it up to the pinfo macros.
1456 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1458 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
1460 * ppc.h: (PPC_OPCODE_E500MC): New.
1462 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1464 * i386.h (MAX_OPERANDS): Set to 5.
1465 (MAX_MNEM_SIZE): Changed to 20.
1467 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1469 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1471 2008-03-09 Paul Brook <paul@codesourcery.com>
1473 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1475 2008-03-04 Paul Brook <paul@codesourcery.com>
1477 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1478 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1479 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1481 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
1482 Nick Clifton <nickc@redhat.com>
1485 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1486 with a 32-bit displacement but without the top bit of the 4th byte
1489 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1491 * cr16.h (cr16_num_optab): Declared.
1493 2008-02-14 Hakan Ardo <hakan@debian.org>
1496 * avr.h (AVR_ISA_2xxe): Define.
1498 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1500 * mips.h: Update copyright.
1501 (INSN_CHIP_MASK): New macro.
1502 (INSN_OCTEON): New macro.
1503 (CPU_OCTEON): New macro.
1504 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1506 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1508 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1510 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1512 * avr.h (AVR_ISA_USB162): Add new opcode set.
1513 (AVR_ISA_AVR3): Likewise.
1515 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1517 * mips.h (INSN_LOONGSON_2E): New.
1518 (INSN_LOONGSON_2F): New.
1519 (CPU_LOONGSON_2E): New.
1520 (CPU_LOONGSON_2F): New.
1521 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1523 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1525 * mips.h (INSN_ISA*): Redefine certain values as an
1526 enumeration. Update comments.
1527 (mips_isa_table): New.
1528 (ISA_MIPS*): Redefine to match enumeration.
1529 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1532 2007-08-08 Ben Elliston <bje@au.ibm.com>
1534 * ppc.h (PPC_OPCODE_PPCPS): New.
1536 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1538 * m68k.h: Document j K & E.
1540 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1542 * cr16.h: New file for CR16 target.
1544 2007-05-02 Alan Modra <amodra@bigpond.net.au>
1546 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1548 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1550 * m68k.h (mcfisa_c): New.
1551 (mcfusp, mcf_mask): Adjust.
1553 2007-04-20 Alan Modra <amodra@bigpond.net.au>
1555 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1556 (num_powerpc_operands): Declare.
1557 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1558 (PPC_OPERAND_PLUS1): Define.
1560 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
1562 * i386.h (REX_MODE64): Renamed to ...
1564 (REX_EXTX): Renamed to ...
1566 (REX_EXTY): Renamed to ...
1568 (REX_EXTZ): Renamed to ...
1571 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1573 * i386.h: Add entries from config/tc-i386.h and move tables
1574 to opcodes/i386-opc.h.
1576 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1578 * i386.h (FloatDR): Removed.
1579 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1581 2007-03-01 Alan Modra <amodra@bigpond.net.au>
1583 * spu-insns.h: Add soma double-float insns.
1585 2007-02-20 Thiemo Seufer <ths@mips.com>
1586 Chao-Ying Fu <fu@mips.com>
1588 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1589 (INSN_DSPR2): Add flag for DSP R2 instructions.
1590 (M_BALIGN): New macro.
1592 2007-02-14 Alan Modra <amodra@bigpond.net.au>
1594 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1595 and Seg3ShortFrom with Shortform.
1597 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1600 * i386.h (i386_optab): Put the real "test" before the pseudo
1603 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
1605 * m68k.h (m68010up): OR fido_a.
1607 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
1609 * m68k.h (fido_a): New.
1611 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
1613 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1614 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1617 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1619 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1621 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1623 * score-inst.h (enum score_insn_type): Add Insn_internal.
1625 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1626 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1627 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1628 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1629 Alan Modra <amodra@bigpond.net.au>
1631 * spu-insns.h: New file.
1634 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1636 * ppc.h (PPC_OPCODE_CELL): Define.
1638 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1640 * i386.h : Modify opcode to support for the change in POPCNT opcode
1641 in amdfam10 architecture.
1643 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1645 * i386.h: Replace CpuMNI with CpuSSSE3.
1647 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
1648 Joseph Myers <joseph@codesourcery.com>
1649 Ian Lance Taylor <ian@wasabisystems.com>
1650 Ben Elliston <bje@wasabisystems.com>
1652 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1654 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1656 * score-datadep.h: New file.
1657 * score-inst.h: New file.
1659 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1661 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1662 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1663 movdq2q and movq2dq.
1665 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1666 Michael Meissner <michael.meissner@amd.com>
1668 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1670 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1672 * i386.h (i386_optab): Add "nop" with memory reference.
1674 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1676 * i386.h (i386_optab): Update comment for 64bit NOP.
1678 2006-06-06 Ben Elliston <bje@au.ibm.com>
1679 Anton Blanchard <anton@samba.org>
1681 * ppc.h (PPC_OPCODE_POWER6): Define.
1684 2006-06-05 Thiemo Seufer <ths@mips.com>
1686 * mips.h: Improve description of MT flags.
1688 2006-05-25 Richard Sandiford <richard@codesourcery.com>
1690 * m68k.h (mcf_mask): Define.
1692 2006-05-05 Thiemo Seufer <ths@mips.com>
1693 David Ung <davidu@mips.com>
1695 * mips.h (enum): Add macro M_CACHE_AB.
1697 2006-05-04 Thiemo Seufer <ths@mips.com>
1698 Nigel Stephens <nigel@mips.com>
1699 David Ung <davidu@mips.com>
1701 * mips.h: Add INSN_SMARTMIPS define.
1703 2006-04-30 Thiemo Seufer <ths@mips.com>
1704 David Ung <davidu@mips.com>
1706 * mips.h: Defines udi bits and masks. Add description of
1707 characters which may appear in the args field of udi
1710 2006-04-26 Thiemo Seufer <ths@networkno.de>
1712 * mips.h: Improve comments describing the bitfield instruction
1715 2006-04-26 Julian Brown <julian@codesourcery.com>
1717 * arm.h (FPU_VFP_EXT_V3): Define constant.
1718 (FPU_NEON_EXT_V1): Likewise.
1719 (FPU_VFP_HARD): Update.
1720 (FPU_VFP_V3): Define macro.
1721 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1723 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
1725 * avr.h (AVR_ISA_PWMx): New.
1727 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1729 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1730 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1731 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1732 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1733 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1735 2006-03-10 Paul Brook <paul@codesourcery.com>
1737 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1739 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1741 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1742 first. Correct mask of bb "B" opcode.
1744 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1746 * i386.h (i386_optab): Support Intel Merom New Instructions.
1748 2006-02-24 Paul Brook <paul@codesourcery.com>
1750 * arm.h: Add V7 feature bits.
1752 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1754 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1756 2006-01-31 Paul Brook <paul@codesourcery.com>
1757 Richard Earnshaw <rearnsha@arm.com>
1759 * arm.h: Use ARM_CPU_FEATURE.
1760 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1761 (arm_feature_set): Change to a structure.
1762 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1763 ARM_FEATURE): New macros.
1765 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
1767 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1768 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1769 (ADD_PC_INCR_OPCODE): Don't define.
1771 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1774 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1776 2005-11-14 David Ung <davidu@mips.com>
1778 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1779 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1780 save/restore encoding of the args field.
1782 2005-10-28 Dave Brolley <brolley@redhat.com>
1784 Contribute the following changes:
1785 2005-02-16 Dave Brolley <brolley@redhat.com>
1787 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1788 cgen_isa_mask_* to cgen_bitset_*.
1791 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1793 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1794 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1795 (CGEN_CPU_TABLE): Make isas a ponter.
1797 2003-09-29 Dave Brolley <brolley@redhat.com>
1799 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1800 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1801 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1803 2002-12-13 Dave Brolley <brolley@redhat.com>
1805 * cgen.h (symcat.h): #include it.
1806 (cgen-bitset.h): #include it.
1807 (CGEN_ATTR_VALUE_TYPE): Now a union.
1808 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1809 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1810 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1811 * cgen-bitset.h: New file.
1813 2005-09-30 Catherine Moore <clm@cm00re.com>
1817 2005-10-24 Jan Beulich <jbeulich@novell.com>
1819 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1822 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1824 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1825 Add FLAG_STRICT to pa10 ftest opcode.
1827 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1829 * hppa.h (pa_opcodes): Remove lha entries.
1831 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1833 * hppa.h (FLAG_STRICT): Revise comment.
1834 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1835 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1838 2005-09-30 Catherine Moore <clm@cm00re.com>
1842 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1844 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1846 2005-09-06 Chao-ying Fu <fu@mips.com>
1848 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1849 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1851 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1852 (INSN_ASE_MASK): Update to include INSN_MT.
1853 (INSN_MT): New define for MT ASE.
1855 2005-08-25 Chao-ying Fu <fu@mips.com>
1857 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1858 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1859 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1860 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1861 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1862 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1864 (INSN_DSP): New define for DSP ASE.
1866 2005-08-18 Alan Modra <amodra@bigpond.net.au>
1870 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1872 * ppc.h (PPC_OPCODE_E300): Define.
1874 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1876 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1878 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1881 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1884 2005-07-27 Jan Beulich <jbeulich@novell.com>
1886 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1887 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1888 Add movq-s as 64-bit variants of movd-s.
1890 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1892 * hppa.h: Fix punctuation in comment.
1894 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1895 implicit space-register addressing. Set space-register bits on opcodes
1896 using implicit space-register addressing. Add various missing pa20
1897 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1898 space-register addressing. Use "fE" instead of "fe" in various
1901 2005-07-18 Jan Beulich <jbeulich@novell.com>
1903 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1905 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1907 * i386.h (i386_optab): Support Intel VMX Instructions.
1909 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1911 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1913 2005-07-05 Jan Beulich <jbeulich@novell.com>
1915 * i386.h (i386_optab): Add new insns.
1917 2005-07-01 Nick Clifton <nickc@redhat.com>
1919 * sparc.h: Add typedefs to structure declarations.
1921 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1924 * i386.h (i386_optab): Update comments for 64bit addressing on
1925 mov. Allow 64bit addressing for mov and movq.
1927 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1929 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1930 respectively, in various floating-point load and store patterns.
1932 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1934 * hppa.h (FLAG_STRICT): Correct comment.
1935 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1936 PA 2.0 mneumonics when equivalent. Entries with cache control
1937 completers now require PA 1.1. Adjust whitespace.
1939 2005-05-19 Anton Blanchard <anton@samba.org>
1941 * ppc.h (PPC_OPCODE_POWER5): Define.
1943 2005-05-10 Nick Clifton <nickc@redhat.com>
1945 * Update the address and phone number of the FSF organization in
1946 the GPL notices in the following files:
1947 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1948 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1949 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1950 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1951 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1952 tic54x.h, tic80.h, v850.h, vax.h
1954 2005-05-09 Jan Beulich <jbeulich@novell.com>
1956 * i386.h (i386_optab): Add ht and hnt.
1958 2005-04-18 Mark Kettenis <kettenis@gnu.org>
1960 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1961 Add xcrypt-ctr. Provide aliases without hyphens.
1963 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1965 Moved from ../ChangeLog
1967 2005-04-12 Paul Brook <paul@codesourcery.com>
1968 * m88k.h: Rename psr macros to avoid conflicts.
1970 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1971 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1972 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1973 and ARM_ARCH_V6ZKT2.
1975 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1976 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1977 Remove redundant instruction types.
1978 (struct argument): X_op - new field.
1979 (struct cst4_entry): Remove.
1980 (no_op_insn): Declare.
1982 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1983 * crx.h (enum argtype): Rename types, remove unused types.
1985 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1986 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1987 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1988 (enum operand_type): Rearrange operands, edit comments.
1989 replace us<N> with ui<N> for unsigned immediate.
1990 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1991 displacements (respectively).
1992 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1993 (instruction type): Add NO_TYPE_INS.
1994 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1995 (operand_entry): New field - 'flags'.
1996 (operand flags): New.
1998 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1999 * crx.h (operand_type): Remove redundant types i3, i4,
2001 Add new unsigned immediate types us3, us4, us5, us16.
2003 2005-04-12 Mark Kettenis <kettenis@gnu.org>
2005 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
2006 adjust them accordingly.
2008 2005-04-01 Jan Beulich <jbeulich@novell.com>
2010 * i386.h (i386_optab): Add rdtscp.
2012 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
2014 * i386.h (i386_optab): Don't allow the `l' suffix for moving
2015 between memory and segment register. Allow movq for moving between
2016 general-purpose register and segment register.
2018 2005-02-09 Jan Beulich <jbeulich@novell.com>
2021 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
2022 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
2025 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
2027 * m68k.h (m68008, m68ec030, m68882): Remove.
2029 (cpu_m68k, cpu_cf): New.
2030 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
2031 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
2033 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
2035 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
2036 * cgen.h (enum cgen_parse_operand_type): Add
2037 CGEN_PARSE_OPERAND_SYMBOLIC.
2039 2005-01-21 Fred Fish <fnf@specifixinc.com>
2041 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
2042 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
2043 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
2045 2005-01-19 Fred Fish <fnf@specifixinc.com>
2047 * mips.h (struct mips_opcode): Add new pinfo2 member.
2048 (INSN_ALIAS): New define for opcode table entries that are
2049 specific instances of another entry, such as 'move' for an 'or'
2050 with a zero operand.
2051 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
2052 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
2054 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
2056 * mips.h (CPU_RM9000): Define.
2057 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
2059 2004-11-25 Jan Beulich <jbeulich@novell.com>
2061 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
2062 to/from test registers are illegal in 64-bit mode. Add missing
2063 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
2064 (previously one had to explicitly encode a rex64 prefix). Re-enable
2065 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
2066 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
2068 2004-11-23 Jan Beulich <jbeulich@novell.com>
2070 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
2071 available only with SSE2. Change the MMX additions introduced by SSE
2072 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
2073 instructions by their now designated identifier (since combining i686
2074 and 3DNow! does not really imply 3DNow!A).
2076 2004-11-19 Alan Modra <amodra@bigpond.net.au>
2078 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
2079 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
2081 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
2082 Vineet Sharma <vineets@noida.hcltech.com>
2084 * maxq.h: New file: Disassembly information for the maxq port.
2086 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
2088 * i386.h (i386_optab): Put back "movzb".
2090 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
2092 * cris.h (enum cris_insn_version_usage): Tweak formatting and
2093 comments. Remove member cris_ver_sim. Add members
2094 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
2095 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
2096 (struct cris_support_reg, struct cris_cond15): New types.
2097 (cris_conds15): Declare.
2098 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
2099 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
2100 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
2101 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
2102 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
2103 SIZE_FIELD_UNSIGNED.
2105 2004-11-04 Jan Beulich <jbeulich@novell.com>
2107 * i386.h (sldx_Suf): Remove.
2108 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
2109 (q_FP): Define, implying no REX64.
2110 (x_FP, sl_FP): Imply FloatMF.
2111 (i386_optab): Split reg and mem forms of moving from segment registers
2112 so that the memory forms can ignore the 16-/32-bit operand size
2113 distinction. Adjust a few others for Intel mode. Remove *FP uses from
2114 all non-floating-point instructions. Unite 32- and 64-bit forms of
2115 movsx, movzx, and movd. Adjust floating point operations for the above
2116 changes to the *FP macros. Add DefaultSize to floating point control
2117 insns operating on larger memory ranges. Remove left over comments
2118 hinting at certain insns being Intel-syntax ones where the ones
2119 actually meant are already gone.
2121 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
2123 * crx.h: Add COPS_REG_INS - Coprocessor Special register
2126 2004-09-30 Paul Brook <paul@codesourcery.com>
2128 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
2129 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
2131 2004-09-11 Theodore A. Roth <troth@openavr.org>
2133 * avr.h: Add support for
2134 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
2136 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
2138 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
2140 2004-08-24 Dmitry Diky <diwil@spec.ru>
2142 * msp430.h (msp430_opc): Add new instructions.
2143 (msp430_rcodes): Declare new instructions.
2144 (msp430_hcodes): Likewise..
2146 2004-08-13 Nick Clifton <nickc@redhat.com>
2149 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
2152 2004-08-30 Michal Ludvig <mludvig@suse.cz>
2154 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
2156 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
2158 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
2160 2004-07-21 Jan Beulich <jbeulich@novell.com>
2162 * i386.h: Adjust instruction descriptions to better match the
2165 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
2167 * arm.h: Remove all old content. Replace with architecture defines
2168 from gas/config/tc-arm.c.
2170 2004-07-09 Andreas Schwab <schwab@suse.de>
2172 * m68k.h: Fix comment.
2174 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
2178 2004-06-24 Alan Modra <amodra@bigpond.net.au>
2180 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
2182 2004-05-24 Peter Barada <peter@the-baradas.com>
2184 * m68k.h: Add 'size' to m68k_opcode.
2186 2004-05-05 Peter Barada <peter@the-baradas.com>
2188 * m68k.h: Switch from ColdFire chip name to core variant.
2190 2004-04-22 Peter Barada <peter@the-baradas.com>
2192 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
2193 descriptions for new EMAC cases.
2194 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
2195 handle Motorola MAC syntax.
2196 Allow disassembly of ColdFire V4e object files.
2198 2004-03-16 Alan Modra <amodra@bigpond.net.au>
2200 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
2202 2004-03-12 Jakub Jelinek <jakub@redhat.com>
2204 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
2206 2004-03-12 Michal Ludvig <mludvig@suse.cz>
2208 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
2210 2004-03-12 Michal Ludvig <mludvig@suse.cz>
2212 * i386.h (i386_optab): Added xstore/xcrypt insns.
2214 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
2216 * h8300.h (32bit ldc/stc): Add relaxing support.
2218 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
2220 * h8300.h (BITOP): Pass MEMRELAX flag.
2222 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
2224 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
2227 For older changes see ChangeLog-9103
2229 Copyright (C) 2004-2015 Free Software Foundation, Inc.
2231 Copying and distribution of this file, with or without modification,
2232 are permitted in any medium without royalty provided the copyright
2233 notice and this notice are preserved.
2239 version-control: never
projects / external / binutils.git / blob