1 2007-02-14 Alan Modra <amodra@bigpond.net.au>
3 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
4 and Seg3ShortFrom with Shortform.
6 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
9 * i386.h (i386_optab): Put the real "test" before the pseudo
12 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
14 * m68k.h (m68010up): OR fido_a.
16 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
18 * m68k.h (fido_a): New.
20 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
22 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
23 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
26 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
28 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
30 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
32 * score-inst.h (enum score_insn_type): Add Insn_internal.
34 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
35 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
36 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
37 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
38 Alan Modra <amodra@bigpond.net.au>
40 * spu-insns.h: New file.
43 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
45 * ppc.h (PPC_OPCODE_CELL): Define.
47 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
49 * i386.h : Modify opcode to support for the change in POPCNT opcode
50 in amdfam10 architecture.
52 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
54 * i386.h: Replace CpuMNI with CpuSSSE3.
56 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
57 Joseph Myers <joseph@codesourcery.com>
58 Ian Lance Taylor <ian@wasabisystems.com>
59 Ben Elliston <bje@wasabisystems.com>
61 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
63 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
65 * score-datadep.h: New file.
66 * score-inst.h: New file.
68 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
70 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
71 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
74 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
75 Michael Meissner <michael.meissner@amd.com>
77 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
79 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
81 * i386.h (i386_optab): Add "nop" with memory reference.
83 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
85 * i386.h (i386_optab): Update comment for 64bit NOP.
87 2006-06-06 Ben Elliston <bje@au.ibm.com>
88 Anton Blanchard <anton@samba.org>
90 * ppc.h (PPC_OPCODE_POWER6): Define.
93 2006-06-05 Thiemo Seufer <ths@mips.com>
95 * mips.h: Improve description of MT flags.
97 2006-05-25 Richard Sandiford <richard@codesourcery.com>
99 * m68k.h (mcf_mask): Define.
101 2006-05-05 Thiemo Seufer <ths@mips.com>
102 David Ung <davidu@mips.com>
104 * mips.h (enum): Add macro M_CACHE_AB.
106 2006-05-04 Thiemo Seufer <ths@mips.com>
107 Nigel Stephens <nigel@mips.com>
108 David Ung <davidu@mips.com>
110 * mips.h: Add INSN_SMARTMIPS define.
112 2006-04-30 Thiemo Seufer <ths@mips.com>
113 David Ung <davidu@mips.com>
115 * mips.h: Defines udi bits and masks. Add description of
116 characters which may appear in the args field of udi
119 2006-04-26 Thiemo Seufer <ths@networkno.de>
121 * mips.h: Improve comments describing the bitfield instruction
124 2006-04-26 Julian Brown <julian@codesourcery.com>
126 * arm.h (FPU_VFP_EXT_V3): Define constant.
127 (FPU_NEON_EXT_V1): Likewise.
128 (FPU_VFP_HARD): Update.
129 (FPU_VFP_V3): Define macro.
130 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
132 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
134 * avr.h (AVR_ISA_PWMx): New.
136 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
138 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
139 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
140 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
141 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
142 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
144 2006-03-10 Paul Brook <paul@codesourcery.com>
146 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
148 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
150 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
151 first. Correct mask of bb "B" opcode.
153 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
155 * i386.h (i386_optab): Support Intel Merom New Instructions.
157 2006-02-24 Paul Brook <paul@codesourcery.com>
159 * arm.h: Add V7 feature bits.
161 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
163 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
165 2006-01-31 Paul Brook <paul@codesourcery.com>
166 Richard Earnshaw <rearnsha@arm.com>
168 * arm.h: Use ARM_CPU_FEATURE.
169 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
170 (arm_feature_set): Change to a structure.
171 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
172 ARM_FEATURE): New macros.
174 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
176 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
177 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
178 (ADD_PC_INCR_OPCODE): Don't define.
180 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
183 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
185 2005-11-14 David Ung <davidu@mips.com>
187 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
188 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
189 save/restore encoding of the args field.
191 2005-10-28 Dave Brolley <brolley@redhat.com>
193 Contribute the following changes:
194 2005-02-16 Dave Brolley <brolley@redhat.com>
196 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
197 cgen_isa_mask_* to cgen_bitset_*.
200 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
202 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
203 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
204 (CGEN_CPU_TABLE): Make isas a ponter.
206 2003-09-29 Dave Brolley <brolley@redhat.com>
208 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
209 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
210 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
212 2002-12-13 Dave Brolley <brolley@redhat.com>
214 * cgen.h (symcat.h): #include it.
215 (cgen-bitset.h): #include it.
216 (CGEN_ATTR_VALUE_TYPE): Now a union.
217 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
218 (CGEN_ATTR_ENTRY): 'value' now unsigned.
219 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
220 * cgen-bitset.h: New file.
222 2005-09-30 Catherine Moore <clm@cm00re.com>
226 2005-10-24 Jan Beulich <jbeulich@novell.com>
228 * ia64.h (enum ia64_opnd): Move memory operand out of set of
231 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
233 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
234 Add FLAG_STRICT to pa10 ftest opcode.
236 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
238 * hppa.h (pa_opcodes): Remove lha entries.
240 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
242 * hppa.h (FLAG_STRICT): Revise comment.
243 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
244 before corresponding pa11 opcodes. Add strict pa10 register-immediate
247 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
249 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
251 2005-09-06 Chao-ying Fu <fu@mips.com>
253 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
254 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
256 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
257 (INSN_ASE_MASK): Update to include INSN_MT.
258 (INSN_MT): New define for MT ASE.
260 2005-08-25 Chao-ying Fu <fu@mips.com>
262 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
263 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
264 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
265 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
266 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
267 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
269 (INSN_DSP): New define for DSP ASE.
271 2005-08-18 Alan Modra <amodra@bigpond.net.au>
275 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
277 * ppc.h (PPC_OPCODE_E300): Define.
279 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
281 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
283 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
286 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
289 2005-07-27 Jan Beulich <jbeulich@novell.com>
291 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
292 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
293 Add movq-s as 64-bit variants of movd-s.
295 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
297 * hppa.h: Fix punctuation in comment.
299 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
300 implicit space-register addressing. Set space-register bits on opcodes
301 using implicit space-register addressing. Add various missing pa20
302 long-immediate opcodes. Remove various opcodes using implicit 3-bit
303 space-register addressing. Use "fE" instead of "fe" in various
306 2005-07-18 Jan Beulich <jbeulich@novell.com>
308 * i386.h (i386_optab): Operands of aam and aad are unsigned.
310 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
312 * i386.h (i386_optab): Support Intel VMX Instructions.
314 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
316 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
318 2005-07-05 Jan Beulich <jbeulich@novell.com>
320 * i386.h (i386_optab): Add new insns.
322 2005-07-01 Nick Clifton <nickc@redhat.com>
324 * sparc.h: Add typedefs to structure declarations.
326 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
329 * i386.h (i386_optab): Update comments for 64bit addressing on
330 mov. Allow 64bit addressing for mov and movq.
332 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
334 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
335 respectively, in various floating-point load and store patterns.
337 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
339 * hppa.h (FLAG_STRICT): Correct comment.
340 (pa_opcodes): Update load and store entries to allow both PA 1.X and
341 PA 2.0 mneumonics when equivalent. Entries with cache control
342 completers now require PA 1.1. Adjust whitespace.
344 2005-05-19 Anton Blanchard <anton@samba.org>
346 * ppc.h (PPC_OPCODE_POWER5): Define.
348 2005-05-10 Nick Clifton <nickc@redhat.com>
350 * Update the address and phone number of the FSF organization in
351 the GPL notices in the following files:
352 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
353 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
354 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
355 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
356 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
357 tic54x.h, tic80.h, v850.h, vax.h
359 2005-05-09 Jan Beulich <jbeulich@novell.com>
361 * i386.h (i386_optab): Add ht and hnt.
363 2005-04-18 Mark Kettenis <kettenis@gnu.org>
365 * i386.h: Insert hyphens into selected VIA PadLock extensions.
366 Add xcrypt-ctr. Provide aliases without hyphens.
368 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
370 Moved from ../ChangeLog
372 2005-04-12 Paul Brook <paul@codesourcery.com>
373 * m88k.h: Rename psr macros to avoid conflicts.
375 2005-03-12 Zack Weinberg <zack@codesourcery.com>
376 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
377 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
380 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
381 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
382 Remove redundant instruction types.
383 (struct argument): X_op - new field.
384 (struct cst4_entry): Remove.
385 (no_op_insn): Declare.
387 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
388 * crx.h (enum argtype): Rename types, remove unused types.
390 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
391 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
392 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
393 (enum operand_type): Rearrange operands, edit comments.
394 replace us<N> with ui<N> for unsigned immediate.
395 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
396 displacements (respectively).
397 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
398 (instruction type): Add NO_TYPE_INS.
399 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
400 (operand_entry): New field - 'flags'.
401 (operand flags): New.
403 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
404 * crx.h (operand_type): Remove redundant types i3, i4,
406 Add new unsigned immediate types us3, us4, us5, us16.
408 2005-04-12 Mark Kettenis <kettenis@gnu.org>
410 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
411 adjust them accordingly.
413 2005-04-01 Jan Beulich <jbeulich@novell.com>
415 * i386.h (i386_optab): Add rdtscp.
417 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
419 * i386.h (i386_optab): Don't allow the `l' suffix for moving
420 between memory and segment register. Allow movq for moving between
421 general-purpose register and segment register.
423 2005-02-09 Jan Beulich <jbeulich@novell.com>
426 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
427 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
430 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
432 * m68k.h (m68008, m68ec030, m68882): Remove.
434 (cpu_m68k, cpu_cf): New.
435 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
436 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
438 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
440 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
441 * cgen.h (enum cgen_parse_operand_type): Add
442 CGEN_PARSE_OPERAND_SYMBOLIC.
444 2005-01-21 Fred Fish <fnf@specifixinc.com>
446 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
447 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
448 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
450 2005-01-19 Fred Fish <fnf@specifixinc.com>
452 * mips.h (struct mips_opcode): Add new pinfo2 member.
453 (INSN_ALIAS): New define for opcode table entries that are
454 specific instances of another entry, such as 'move' for an 'or'
456 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
457 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
459 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
461 * mips.h (CPU_RM9000): Define.
462 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
464 2004-11-25 Jan Beulich <jbeulich@novell.com>
466 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
467 to/from test registers are illegal in 64-bit mode. Add missing
468 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
469 (previously one had to explicitly encode a rex64 prefix). Re-enable
470 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
471 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
473 2004-11-23 Jan Beulich <jbeulich@novell.com>
475 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
476 available only with SSE2. Change the MMX additions introduced by SSE
477 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
478 instructions by their now designated identifier (since combining i686
479 and 3DNow! does not really imply 3DNow!A).
481 2004-11-19 Alan Modra <amodra@bigpond.net.au>
483 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
484 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
486 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
487 Vineet Sharma <vineets@noida.hcltech.com>
489 * maxq.h: New file: Disassembly information for the maxq port.
491 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
493 * i386.h (i386_optab): Put back "movzb".
495 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
497 * cris.h (enum cris_insn_version_usage): Tweak formatting and
498 comments. Remove member cris_ver_sim. Add members
499 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
500 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
501 (struct cris_support_reg, struct cris_cond15): New types.
502 (cris_conds15): Declare.
503 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
504 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
505 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
506 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
507 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
510 2004-11-04 Jan Beulich <jbeulich@novell.com>
512 * i386.h (sldx_Suf): Remove.
513 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
514 (q_FP): Define, implying no REX64.
515 (x_FP, sl_FP): Imply FloatMF.
516 (i386_optab): Split reg and mem forms of moving from segment registers
517 so that the memory forms can ignore the 16-/32-bit operand size
518 distinction. Adjust a few others for Intel mode. Remove *FP uses from
519 all non-floating-point instructions. Unite 32- and 64-bit forms of
520 movsx, movzx, and movd. Adjust floating point operations for the above
521 changes to the *FP macros. Add DefaultSize to floating point control
522 insns operating on larger memory ranges. Remove left over comments
523 hinting at certain insns being Intel-syntax ones where the ones
524 actually meant are already gone.
526 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
528 * crx.h: Add COPS_REG_INS - Coprocessor Special register
531 2004-09-30 Paul Brook <paul@codesourcery.com>
533 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
534 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
536 2004-09-11 Theodore A. Roth <troth@openavr.org>
538 * avr.h: Add support for
539 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
541 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
543 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
545 2004-08-24 Dmitry Diky <diwil@spec.ru>
547 * msp430.h (msp430_opc): Add new instructions.
548 (msp430_rcodes): Declare new instructions.
549 (msp430_hcodes): Likewise..
551 2004-08-13 Nick Clifton <nickc@redhat.com>
554 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
557 2004-08-30 Michal Ludvig <mludvig@suse.cz>
559 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
561 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
563 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
565 2004-07-21 Jan Beulich <jbeulich@novell.com>
567 * i386.h: Adjust instruction descriptions to better match the
570 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
572 * arm.h: Remove all old content. Replace with architecture defines
573 from gas/config/tc-arm.c.
575 2004-07-09 Andreas Schwab <schwab@suse.de>
577 * m68k.h: Fix comment.
579 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
583 2004-06-24 Alan Modra <amodra@bigpond.net.au>
585 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
587 2004-05-24 Peter Barada <peter@the-baradas.com>
589 * m68k.h: Add 'size' to m68k_opcode.
591 2004-05-05 Peter Barada <peter@the-baradas.com>
593 * m68k.h: Switch from ColdFire chip name to core variant.
595 2004-04-22 Peter Barada <peter@the-baradas.com>
597 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
598 descriptions for new EMAC cases.
599 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
600 handle Motorola MAC syntax.
601 Allow disassembly of ColdFire V4e object files.
603 2004-03-16 Alan Modra <amodra@bigpond.net.au>
605 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
607 2004-03-12 Jakub Jelinek <jakub@redhat.com>
609 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
611 2004-03-12 Michal Ludvig <mludvig@suse.cz>
613 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
615 2004-03-12 Michal Ludvig <mludvig@suse.cz>
617 * i386.h (i386_optab): Added xstore/xcrypt insns.
619 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
621 * h8300.h (32bit ldc/stc): Add relaxing support.
623 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
625 * h8300.h (BITOP): Pass MEMRELAX flag.
627 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
629 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
632 For older changes see ChangeLog-9103
638 version-control: never