1 2011-04-18 Julian Brown <julian@codesourcery.com>
3 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
5 2011-04-11 Dan McDonald <dan@wellkeeper.com>
8 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
10 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
12 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
13 New instruction set flags.
14 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
16 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
18 * mips.h (M_PREF_AB): New enum value.
20 2011-02-12 Mike Frysinger <vapier@gentoo.org>
22 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
24 (is_macmod_pmove, is_macmod_hmove): New functions.
26 2011-02-11 Mike Frysinger <vapier@gentoo.org>
28 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
30 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
32 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
33 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
35 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
38 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
41 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
44 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
46 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
48 * mips.h: Update commentary after last commit.
50 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
52 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
53 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
54 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
56 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
58 * mips.h: Fix previous commit.
60 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
62 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
63 (INSN_LOONGSON_3A): Clear bit 31.
65 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
68 * arm.h (ARM_AEXT_V6M_ONLY): New define.
69 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
70 (ARM_ARCH_V6M_ONLY): New define.
72 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
74 * mips.h (INSN_LOONGSON_3A): Defined.
75 (CPU_LOONGSON_3A): Defined.
76 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
78 2010-10-09 Matt Rice <ratmice@gmail.com>
80 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
81 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
83 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
85 * arm.h (ARM_EXT_VIRT): New define.
86 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
87 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
90 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
92 * arm.h (ARM_AEXT_ADIV): New define.
93 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
95 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
97 * arm.h (ARM_EXT_OS): New define.
98 (ARM_AEXT_V6SM): Likewise.
99 (ARM_ARCH_V6SM): Likewise.
101 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
103 * arm.h (ARM_EXT_MP): Add.
104 (ARM_ARCH_V7A_MP): Likewise.
106 2010-09-22 Mike Frysinger <vapier@gentoo.org>
108 * bfin.h: Declare pseudoChr structs/defines.
110 2010-09-21 Mike Frysinger <vapier@gentoo.org>
112 * bfin.h: Strip trailing whitespace.
114 2010-07-29 DJ Delorie <dj@redhat.com>
116 * rx.h (RX_Operand_Type): Add TwoReg.
117 (RX_Opcode_ID): Remove ediv and ediv2.
119 2010-07-27 DJ Delorie <dj@redhat.com>
121 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
123 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
124 Ina Pandit <ina.pandit@kpitcummins.com>
126 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
127 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
128 PROCESSOR_V850E2_ALL.
129 Remove PROCESSOR_V850EA support.
130 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
131 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
132 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
133 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
134 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
135 V850_OPERAND_PERCENT.
136 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
138 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
141 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
143 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
144 (MIPS16_INSN_BRANCH): Rename to...
145 (MIPS16_INSN_COND_BRANCH): ... this.
147 2010-07-03 Alan Modra <amodra@gmail.com>
149 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
150 Renumber other PPC_OPCODE defines.
152 2010-07-03 Alan Modra <amodra@gmail.com>
154 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
156 2010-06-29 Alan Modra <amodra@gmail.com>
158 * maxq.h: Delete file.
160 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
162 * ppc.h (PPC_OPCODE_E500): Define.
164 2010-05-26 Catherine Moore <clm@codesourcery.com>
166 * opcode/mips.h (INSN_MIPS16): Remove.
168 2010-04-21 Joseph Myers <joseph@codesourcery.com>
170 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
172 2010-04-15 Nick Clifton <nickc@redhat.com>
174 * alpha.h: Update copyright notice to use GPLv3.
180 * convex.h: Likewise.
194 * m68hc11.h: Likewise.
200 * mn10200.h: Likewise.
201 * mn10300.h: Likewise.
202 * msp430.h: Likewise.
213 * score-datadep.h: Likewise.
214 * score-inst.h: Likewise.
216 * spu-insns.h: Likewise.
220 * tic54x.h: Likewise.
225 2010-03-25 Joseph Myers <joseph@codesourcery.com>
227 * tic6x-control-registers.h, tic6x-insn-formats.h,
228 tic6x-opcode-table.h, tic6x.h: New.
230 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
232 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
234 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
236 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
238 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
240 * ia64.h (ia64_find_opcode): Remove argument name.
241 (ia64_find_next_opcode): Likewise.
242 (ia64_dis_opcode): Likewise.
243 (ia64_free_opcode): Likewise.
244 (ia64_find_dependency): Likewise.
246 2009-11-22 Doug Evans <dje@sebabeach.org>
248 * cgen.h: Include bfd_stdint.h.
249 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
251 2009-11-18 Paul Brook <paul@codesourcery.com>
253 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
255 2009-11-17 Paul Brook <paul@codesourcery.com>
256 Daniel Jacobowitz <dan@codesourcery.com>
258 * arm.h (ARM_EXT_V6_DSP): Define.
259 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
260 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
262 2009-11-04 DJ Delorie <dj@redhat.com>
264 * rx.h (rx_decode_opcode) (mvtipl): Add.
265 (mvtcp, mvfcp, opecp): Remove.
267 2009-11-02 Paul Brook <paul@codesourcery.com>
269 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
270 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
271 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
272 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
273 FPU_ARCH_NEON_VFP_V4): Define.
275 2009-10-23 Doug Evans <dje@sebabeach.org>
277 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
278 * cgen.h: Update. Improve multi-inclusion macro name.
280 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
282 * ppc.h (PPC_OPCODE_476): Define.
284 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
286 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
288 2009-09-29 DJ Delorie <dj@redhat.com>
292 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
294 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
296 2009-09-21 Ben Elliston <bje@au.ibm.com>
298 * ppc.h (PPC_OPCODE_PPCA2): New.
300 2009-09-05 Martin Thuresson <martin@mtme.org>
302 * ia64.h (struct ia64_operand): Renamed member class to op_class.
304 2009-08-29 Martin Thuresson <martin@mtme.org>
306 * tic30.h (template): Rename type template to
307 insn_template. Updated code to use new name.
308 * tic54x.h (template): Rename type template to
311 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
313 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
315 2009-06-11 Anthony Green <green@moxielogic.com>
317 * moxie.h (MOXIE_F3_PCREL): Define.
318 (moxie_form3_opc_info): Grow.
320 2009-06-06 Anthony Green <green@moxielogic.com>
322 * moxie.h (MOXIE_F1_M): Define.
324 2009-04-15 Anthony Green <green@moxielogic.com>
328 2009-04-06 DJ Delorie <dj@redhat.com>
330 * h8300.h: Add relaxation attributes to MOVA opcodes.
332 2009-03-10 Alan Modra <amodra@bigpond.net.au>
334 * ppc.h (ppc_parse_cpu): Declare.
336 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
338 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
339 and _IMM11 for mbitclr and mbitset.
340 * score-datadep.h: Update dependency information.
342 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
344 * ppc.h (PPC_OPCODE_POWER7): New.
346 2009-02-06 Doug Evans <dje@google.com>
348 * i386.h: Add comment regarding sse* insns and prefixes.
350 2009-02-03 Sandip Matte <sandip@rmicorp.com>
352 * mips.h (INSN_XLR): Define.
353 (INSN_CHIP_MASK): Update.
355 (OPCODE_IS_MEMBER): Update.
356 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
358 2009-01-28 Doug Evans <dje@google.com>
360 * opcode/i386.h: Add multiple inclusion protection.
361 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
362 (EDI_REG_NUM): New macros.
363 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
364 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
365 (REX_PREFIX_P): New macro.
367 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
369 * ppc.h (struct powerpc_opcode): New field "deprecated".
370 (PPC_OPCODE_NOPOWER4): Delete.
372 2008-11-28 Joshua Kinard <kumba@gentoo.org>
374 * mips.h: Define CPU_R14000, CPU_R16000.
375 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
377 2008-11-18 Catherine Moore <clm@codesourcery.com>
379 * arm.h (FPU_NEON_FP16): New.
380 (FPU_ARCH_NEON_FP16): New.
382 2008-11-06 Chao-ying Fu <fu@mips.com>
384 * mips.h: Doucument '1' for 5-bit sync type.
386 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
388 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
391 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
393 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
395 2008-07-30 Michael J. Eager <eager@eagercon.com>
397 * ppc.h (PPC_OPCODE_405): Define.
398 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
400 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
402 * ppc.h (ppc_cpu_t): New typedef.
403 (struct powerpc_opcode <flags>): Use it.
404 (struct powerpc_operand <insert, extract>): Likewise.
405 (struct powerpc_macro <flags>): Likewise.
407 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
409 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
410 Update comment before MIPS16 field descriptors to mention MIPS16.
411 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
413 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
414 New bit masks and shift counts for cins and exts.
416 * mips.h: Document new field descriptors +Q.
417 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
419 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
421 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
422 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
424 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
426 * ppc.h: (PPC_OPCODE_E500MC): New.
428 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
430 * i386.h (MAX_OPERANDS): Set to 5.
431 (MAX_MNEM_SIZE): Changed to 20.
433 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
435 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
437 2008-03-09 Paul Brook <paul@codesourcery.com>
439 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
441 2008-03-04 Paul Brook <paul@codesourcery.com>
443 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
444 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
445 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
447 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
448 Nick Clifton <nickc@redhat.com>
451 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
452 with a 32-bit displacement but without the top bit of the 4th byte
455 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
457 * cr16.h (cr16_num_optab): Declared.
459 2008-02-14 Hakan Ardo <hakan@debian.org>
462 * avr.h (AVR_ISA_2xxe): Define.
464 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
466 * mips.h: Update copyright.
467 (INSN_CHIP_MASK): New macro.
468 (INSN_OCTEON): New macro.
469 (CPU_OCTEON): New macro.
470 (OPCODE_IS_MEMBER): Handle Octeon instructions.
472 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
474 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
476 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
478 * avr.h (AVR_ISA_USB162): Add new opcode set.
479 (AVR_ISA_AVR3): Likewise.
481 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
483 * mips.h (INSN_LOONGSON_2E): New.
484 (INSN_LOONGSON_2F): New.
485 (CPU_LOONGSON_2E): New.
486 (CPU_LOONGSON_2F): New.
487 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
489 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
491 * mips.h (INSN_ISA*): Redefine certain values as an
492 enumeration. Update comments.
493 (mips_isa_table): New.
494 (ISA_MIPS*): Redefine to match enumeration.
495 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
498 2007-08-08 Ben Elliston <bje@au.ibm.com>
500 * ppc.h (PPC_OPCODE_PPCPS): New.
502 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
504 * m68k.h: Document j K & E.
506 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
508 * cr16.h: New file for CR16 target.
510 2007-05-02 Alan Modra <amodra@bigpond.net.au>
512 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
514 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
516 * m68k.h (mcfisa_c): New.
517 (mcfusp, mcf_mask): Adjust.
519 2007-04-20 Alan Modra <amodra@bigpond.net.au>
521 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
522 (num_powerpc_operands): Declare.
523 (PPC_OPERAND_SIGNED et al): Redefine as hex.
524 (PPC_OPERAND_PLUS1): Define.
526 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
528 * i386.h (REX_MODE64): Renamed to ...
530 (REX_EXTX): Renamed to ...
532 (REX_EXTY): Renamed to ...
534 (REX_EXTZ): Renamed to ...
537 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
539 * i386.h: Add entries from config/tc-i386.h and move tables
540 to opcodes/i386-opc.h.
542 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
544 * i386.h (FloatDR): Removed.
545 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
547 2007-03-01 Alan Modra <amodra@bigpond.net.au>
549 * spu-insns.h: Add soma double-float insns.
551 2007-02-20 Thiemo Seufer <ths@mips.com>
552 Chao-Ying Fu <fu@mips.com>
554 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
555 (INSN_DSPR2): Add flag for DSP R2 instructions.
556 (M_BALIGN): New macro.
558 2007-02-14 Alan Modra <amodra@bigpond.net.au>
560 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
561 and Seg3ShortFrom with Shortform.
563 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
566 * i386.h (i386_optab): Put the real "test" before the pseudo
569 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
571 * m68k.h (m68010up): OR fido_a.
573 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
575 * m68k.h (fido_a): New.
577 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
579 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
580 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
583 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
585 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
587 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
589 * score-inst.h (enum score_insn_type): Add Insn_internal.
591 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
592 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
593 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
594 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
595 Alan Modra <amodra@bigpond.net.au>
597 * spu-insns.h: New file.
600 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
602 * ppc.h (PPC_OPCODE_CELL): Define.
604 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
606 * i386.h : Modify opcode to support for the change in POPCNT opcode
607 in amdfam10 architecture.
609 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
611 * i386.h: Replace CpuMNI with CpuSSSE3.
613 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
614 Joseph Myers <joseph@codesourcery.com>
615 Ian Lance Taylor <ian@wasabisystems.com>
616 Ben Elliston <bje@wasabisystems.com>
618 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
620 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
622 * score-datadep.h: New file.
623 * score-inst.h: New file.
625 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
627 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
628 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
631 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
632 Michael Meissner <michael.meissner@amd.com>
634 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
636 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
638 * i386.h (i386_optab): Add "nop" with memory reference.
640 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
642 * i386.h (i386_optab): Update comment for 64bit NOP.
644 2006-06-06 Ben Elliston <bje@au.ibm.com>
645 Anton Blanchard <anton@samba.org>
647 * ppc.h (PPC_OPCODE_POWER6): Define.
650 2006-06-05 Thiemo Seufer <ths@mips.com>
652 * mips.h: Improve description of MT flags.
654 2006-05-25 Richard Sandiford <richard@codesourcery.com>
656 * m68k.h (mcf_mask): Define.
658 2006-05-05 Thiemo Seufer <ths@mips.com>
659 David Ung <davidu@mips.com>
661 * mips.h (enum): Add macro M_CACHE_AB.
663 2006-05-04 Thiemo Seufer <ths@mips.com>
664 Nigel Stephens <nigel@mips.com>
665 David Ung <davidu@mips.com>
667 * mips.h: Add INSN_SMARTMIPS define.
669 2006-04-30 Thiemo Seufer <ths@mips.com>
670 David Ung <davidu@mips.com>
672 * mips.h: Defines udi bits and masks. Add description of
673 characters which may appear in the args field of udi
676 2006-04-26 Thiemo Seufer <ths@networkno.de>
678 * mips.h: Improve comments describing the bitfield instruction
681 2006-04-26 Julian Brown <julian@codesourcery.com>
683 * arm.h (FPU_VFP_EXT_V3): Define constant.
684 (FPU_NEON_EXT_V1): Likewise.
685 (FPU_VFP_HARD): Update.
686 (FPU_VFP_V3): Define macro.
687 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
689 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
691 * avr.h (AVR_ISA_PWMx): New.
693 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
695 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
696 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
697 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
698 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
699 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
701 2006-03-10 Paul Brook <paul@codesourcery.com>
703 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
705 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
707 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
708 first. Correct mask of bb "B" opcode.
710 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
712 * i386.h (i386_optab): Support Intel Merom New Instructions.
714 2006-02-24 Paul Brook <paul@codesourcery.com>
716 * arm.h: Add V7 feature bits.
718 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
720 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
722 2006-01-31 Paul Brook <paul@codesourcery.com>
723 Richard Earnshaw <rearnsha@arm.com>
725 * arm.h: Use ARM_CPU_FEATURE.
726 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
727 (arm_feature_set): Change to a structure.
728 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
729 ARM_FEATURE): New macros.
731 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
733 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
734 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
735 (ADD_PC_INCR_OPCODE): Don't define.
737 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
740 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
742 2005-11-14 David Ung <davidu@mips.com>
744 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
745 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
746 save/restore encoding of the args field.
748 2005-10-28 Dave Brolley <brolley@redhat.com>
750 Contribute the following changes:
751 2005-02-16 Dave Brolley <brolley@redhat.com>
753 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
754 cgen_isa_mask_* to cgen_bitset_*.
757 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
759 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
760 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
761 (CGEN_CPU_TABLE): Make isas a ponter.
763 2003-09-29 Dave Brolley <brolley@redhat.com>
765 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
766 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
767 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
769 2002-12-13 Dave Brolley <brolley@redhat.com>
771 * cgen.h (symcat.h): #include it.
772 (cgen-bitset.h): #include it.
773 (CGEN_ATTR_VALUE_TYPE): Now a union.
774 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
775 (CGEN_ATTR_ENTRY): 'value' now unsigned.
776 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
777 * cgen-bitset.h: New file.
779 2005-09-30 Catherine Moore <clm@cm00re.com>
783 2005-10-24 Jan Beulich <jbeulich@novell.com>
785 * ia64.h (enum ia64_opnd): Move memory operand out of set of
788 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
790 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
791 Add FLAG_STRICT to pa10 ftest opcode.
793 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
795 * hppa.h (pa_opcodes): Remove lha entries.
797 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
799 * hppa.h (FLAG_STRICT): Revise comment.
800 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
801 before corresponding pa11 opcodes. Add strict pa10 register-immediate
804 2005-09-30 Catherine Moore <clm@cm00re.com>
808 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
810 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
812 2005-09-06 Chao-ying Fu <fu@mips.com>
814 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
815 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
817 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
818 (INSN_ASE_MASK): Update to include INSN_MT.
819 (INSN_MT): New define for MT ASE.
821 2005-08-25 Chao-ying Fu <fu@mips.com>
823 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
824 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
825 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
826 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
827 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
828 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
830 (INSN_DSP): New define for DSP ASE.
832 2005-08-18 Alan Modra <amodra@bigpond.net.au>
836 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
838 * ppc.h (PPC_OPCODE_E300): Define.
840 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
842 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
844 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
847 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
850 2005-07-27 Jan Beulich <jbeulich@novell.com>
852 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
853 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
854 Add movq-s as 64-bit variants of movd-s.
856 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
858 * hppa.h: Fix punctuation in comment.
860 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
861 implicit space-register addressing. Set space-register bits on opcodes
862 using implicit space-register addressing. Add various missing pa20
863 long-immediate opcodes. Remove various opcodes using implicit 3-bit
864 space-register addressing. Use "fE" instead of "fe" in various
867 2005-07-18 Jan Beulich <jbeulich@novell.com>
869 * i386.h (i386_optab): Operands of aam and aad are unsigned.
871 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
873 * i386.h (i386_optab): Support Intel VMX Instructions.
875 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
877 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
879 2005-07-05 Jan Beulich <jbeulich@novell.com>
881 * i386.h (i386_optab): Add new insns.
883 2005-07-01 Nick Clifton <nickc@redhat.com>
885 * sparc.h: Add typedefs to structure declarations.
887 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
890 * i386.h (i386_optab): Update comments for 64bit addressing on
891 mov. Allow 64bit addressing for mov and movq.
893 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
895 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
896 respectively, in various floating-point load and store patterns.
898 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
900 * hppa.h (FLAG_STRICT): Correct comment.
901 (pa_opcodes): Update load and store entries to allow both PA 1.X and
902 PA 2.0 mneumonics when equivalent. Entries with cache control
903 completers now require PA 1.1. Adjust whitespace.
905 2005-05-19 Anton Blanchard <anton@samba.org>
907 * ppc.h (PPC_OPCODE_POWER5): Define.
909 2005-05-10 Nick Clifton <nickc@redhat.com>
911 * Update the address and phone number of the FSF organization in
912 the GPL notices in the following files:
913 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
914 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
915 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
916 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
917 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
918 tic54x.h, tic80.h, v850.h, vax.h
920 2005-05-09 Jan Beulich <jbeulich@novell.com>
922 * i386.h (i386_optab): Add ht and hnt.
924 2005-04-18 Mark Kettenis <kettenis@gnu.org>
926 * i386.h: Insert hyphens into selected VIA PadLock extensions.
927 Add xcrypt-ctr. Provide aliases without hyphens.
929 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
931 Moved from ../ChangeLog
933 2005-04-12 Paul Brook <paul@codesourcery.com>
934 * m88k.h: Rename psr macros to avoid conflicts.
936 2005-03-12 Zack Weinberg <zack@codesourcery.com>
937 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
938 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
941 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
942 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
943 Remove redundant instruction types.
944 (struct argument): X_op - new field.
945 (struct cst4_entry): Remove.
946 (no_op_insn): Declare.
948 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
949 * crx.h (enum argtype): Rename types, remove unused types.
951 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
952 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
953 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
954 (enum operand_type): Rearrange operands, edit comments.
955 replace us<N> with ui<N> for unsigned immediate.
956 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
957 displacements (respectively).
958 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
959 (instruction type): Add NO_TYPE_INS.
960 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
961 (operand_entry): New field - 'flags'.
962 (operand flags): New.
964 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
965 * crx.h (operand_type): Remove redundant types i3, i4,
967 Add new unsigned immediate types us3, us4, us5, us16.
969 2005-04-12 Mark Kettenis <kettenis@gnu.org>
971 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
972 adjust them accordingly.
974 2005-04-01 Jan Beulich <jbeulich@novell.com>
976 * i386.h (i386_optab): Add rdtscp.
978 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
980 * i386.h (i386_optab): Don't allow the `l' suffix for moving
981 between memory and segment register. Allow movq for moving between
982 general-purpose register and segment register.
984 2005-02-09 Jan Beulich <jbeulich@novell.com>
987 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
988 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
991 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
993 * m68k.h (m68008, m68ec030, m68882): Remove.
995 (cpu_m68k, cpu_cf): New.
996 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
997 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
999 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
1001 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1002 * cgen.h (enum cgen_parse_operand_type): Add
1003 CGEN_PARSE_OPERAND_SYMBOLIC.
1005 2005-01-21 Fred Fish <fnf@specifixinc.com>
1007 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1008 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1009 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1011 2005-01-19 Fred Fish <fnf@specifixinc.com>
1013 * mips.h (struct mips_opcode): Add new pinfo2 member.
1014 (INSN_ALIAS): New define for opcode table entries that are
1015 specific instances of another entry, such as 'move' for an 'or'
1016 with a zero operand.
1017 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1018 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1020 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1022 * mips.h (CPU_RM9000): Define.
1023 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1025 2004-11-25 Jan Beulich <jbeulich@novell.com>
1027 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1028 to/from test registers are illegal in 64-bit mode. Add missing
1029 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1030 (previously one had to explicitly encode a rex64 prefix). Re-enable
1031 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1032 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1034 2004-11-23 Jan Beulich <jbeulich@novell.com>
1036 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1037 available only with SSE2. Change the MMX additions introduced by SSE
1038 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1039 instructions by their now designated identifier (since combining i686
1040 and 3DNow! does not really imply 3DNow!A).
1042 2004-11-19 Alan Modra <amodra@bigpond.net.au>
1044 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1045 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1047 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1048 Vineet Sharma <vineets@noida.hcltech.com>
1050 * maxq.h: New file: Disassembly information for the maxq port.
1052 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1054 * i386.h (i386_optab): Put back "movzb".
1056 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
1058 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1059 comments. Remove member cris_ver_sim. Add members
1060 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1061 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1062 (struct cris_support_reg, struct cris_cond15): New types.
1063 (cris_conds15): Declare.
1064 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1065 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1066 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1067 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1068 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1069 SIZE_FIELD_UNSIGNED.
1071 2004-11-04 Jan Beulich <jbeulich@novell.com>
1073 * i386.h (sldx_Suf): Remove.
1074 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1075 (q_FP): Define, implying no REX64.
1076 (x_FP, sl_FP): Imply FloatMF.
1077 (i386_optab): Split reg and mem forms of moving from segment registers
1078 so that the memory forms can ignore the 16-/32-bit operand size
1079 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1080 all non-floating-point instructions. Unite 32- and 64-bit forms of
1081 movsx, movzx, and movd. Adjust floating point operations for the above
1082 changes to the *FP macros. Add DefaultSize to floating point control
1083 insns operating on larger memory ranges. Remove left over comments
1084 hinting at certain insns being Intel-syntax ones where the ones
1085 actually meant are already gone.
1087 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1089 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1092 2004-09-30 Paul Brook <paul@codesourcery.com>
1094 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1095 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1097 2004-09-11 Theodore A. Roth <troth@openavr.org>
1099 * avr.h: Add support for
1100 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1102 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1104 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1106 2004-08-24 Dmitry Diky <diwil@spec.ru>
1108 * msp430.h (msp430_opc): Add new instructions.
1109 (msp430_rcodes): Declare new instructions.
1110 (msp430_hcodes): Likewise..
1112 2004-08-13 Nick Clifton <nickc@redhat.com>
1115 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1118 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1120 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1122 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1124 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1126 2004-07-21 Jan Beulich <jbeulich@novell.com>
1128 * i386.h: Adjust instruction descriptions to better match the
1131 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
1133 * arm.h: Remove all old content. Replace with architecture defines
1134 from gas/config/tc-arm.c.
1136 2004-07-09 Andreas Schwab <schwab@suse.de>
1138 * m68k.h: Fix comment.
1140 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1144 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1146 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1148 2004-05-24 Peter Barada <peter@the-baradas.com>
1150 * m68k.h: Add 'size' to m68k_opcode.
1152 2004-05-05 Peter Barada <peter@the-baradas.com>
1154 * m68k.h: Switch from ColdFire chip name to core variant.
1156 2004-04-22 Peter Barada <peter@the-baradas.com>
1158 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1159 descriptions for new EMAC cases.
1160 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1161 handle Motorola MAC syntax.
1162 Allow disassembly of ColdFire V4e object files.
1164 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1166 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1168 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1170 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1172 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1174 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1176 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1178 * i386.h (i386_optab): Added xstore/xcrypt insns.
1180 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1182 * h8300.h (32bit ldc/stc): Add relaxing support.
1184 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1186 * h8300.h (BITOP): Pass MEMRELAX flag.
1188 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1190 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1193 For older changes see ChangeLog-9103
1199 version-control: never