1 2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
2 Richard Sandiford <rdsandiford@googlemail.com>
4 * mips.h: Document new VU0 operand characters.
5 (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
6 (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
7 (OP_REG_R5900_ACC): New mips_reg_operand_types.
8 (INSN2_VU0_CHANNEL_SUFFIX): New macro.
9 (mips_vu0_channel_mask): Declare.
11 2013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
13 * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
14 (mips_int_operand_min, mips_int_operand_max): New functions.
15 (mips_decode_pcrel_operand): Use mips_decode_int_operand.
17 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
19 * mips.h (mips_decode_reg_operand): New function.
20 (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
21 (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
22 (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
24 (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
25 (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
26 (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
27 (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
28 (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
29 (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
30 (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
31 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
32 (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
33 (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
34 macros to cover the gaps.
35 (INSN2_MOD_SP): Replace with...
36 (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
37 (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
38 (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
39 (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
40 (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
43 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
45 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
46 (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
47 (MIPS16_INSN_COND_BRANCH): Delete.
49 2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
50 Kirill Yukhin <kirill.yukhin@intel.com>
51 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
53 * i386.h (BND_PREFIX_OPCODE): New.
55 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
57 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
59 (decode_mips16_operand): Declare.
61 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
63 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
64 (mips_operand, mips_int_operand, mips_mapped_int_operand)
65 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
66 (mips_pcrel_operand): New structures.
67 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
68 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
69 (decode_mips_operand, decode_micromips_operand): Declare.
71 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
73 * mips.h: Document MIPS16 "I" opcode.
75 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
77 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
78 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
79 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
80 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
81 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
82 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
83 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
84 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
85 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
86 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
87 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
88 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
89 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
91 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
94 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
96 * mips.h: Remove documentation of "[" and "]". Update documentation
97 of "k" and the MDMX formats.
99 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
101 * mips.h: Update documentation of "+s" and "+S".
103 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
105 * mips.h: Document "+i".
107 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
109 * mips.h: Remove "mi" documentation. Update "mh" documentation.
110 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
112 (INSN2_WRITE_GPR_MHI): Rename to...
113 (INSN2_WRITE_GPR_MH): ...this.
115 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
117 * mips.h: Remove documentation of "+D" and "+T".
119 2013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
121 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
122 Use "source" rather than "destination" for microMIPS "G".
124 2013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
126 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
129 2013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
131 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
133 2013-06-17 Catherine Moore <clm@codesourcery.com>
134 Maciej W. Rozycki <macro@codesourcery.com>
135 Chao-Ying Fu <fu@mips.com>
137 * mips.h (OP_SH_EVAOFFSET): Define.
138 (OP_MASK_EVAOFFSET): Define.
139 (INSN_ASE_MASK): Delete.
141 (M_CACHEE_AB, M_CACHEE_OB): New.
142 (M_LBE_OB, M_LBE_AB): New.
143 (M_LBUE_OB, M_LBUE_AB): New.
144 (M_LHE_OB, M_LHE_AB): New.
145 (M_LHUE_OB, M_LHUE_AB): New.
146 (M_LLE_AB, M_LLE_OB): New.
147 (M_LWE_OB, M_LWE_AB): New.
148 (M_LWLE_AB, M_LWLE_OB): New.
149 (M_LWRE_AB, M_LWRE_OB): New.
150 (M_PREFE_AB, M_PREFE_OB): New.
151 (M_SCE_AB, M_SCE_OB): New.
152 (M_SBE_OB, M_SBE_AB): New.
153 (M_SHE_OB, M_SHE_AB): New.
154 (M_SWE_OB, M_SWE_AB): New.
155 (M_SWLE_AB, M_SWLE_OB): New.
156 (M_SWRE_AB, M_SWRE_OB): New.
157 (MICROMIPSOP_SH_EVAOFFSET): Define.
158 (MICROMIPSOP_MASK_EVAOFFSET): Define.
160 2013-06-12 Sandra Loosemore <sandra@codesourcery.com>
162 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
164 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
166 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
168 2013-05-09 Andrew Pinski <apinski@cavium.com>
170 * mips.h (OP_MASK_CODE10): Correct definition.
171 (OP_SH_CODE10): Likewise.
172 Add a comment that "+J" is used now for OP_*CODE10.
173 (INSN_ASE_MASK): Update.
174 (INSN_VIRT): New macro.
175 (INSN_VIRT64): New macro
177 2013-05-02 Nick Clifton <nickc@redhat.com>
179 * msp430.h: Add patterns for MSP430X instructions.
181 2013-04-06 David S. Miller <davem@davemloft.net>
183 * sparc.h (F_PREFERRED): Define.
184 (F_PREF_ALIAS): Define.
186 2013-04-03 Nick Clifton <nickc@redhat.com>
188 * v850.h (V850_INVERSE_PCREL): Define.
190 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
193 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
195 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
198 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
200 * tic6xc-opcode-table.h: Add 16-bit insns.
201 * tic6x.h: Add support for 16-bit insns.
203 2013-03-21 Michael Schewe <michael.schewe@gmx.net>
205 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
206 and mov.b/w/l Rs,@(d:32,ERd).
208 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
211 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
212 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
213 tic6x_operand_xregpair operand coding type.
214 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
215 opcode field, usu ORXREGD1324 for the src2 operand and remove the
218 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
221 * tic6x.h (enum tic6x_coding_method): Add
222 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
223 separately the msb and lsb of a register pair. This is needed to
224 encode the opcodes in the same way as TI assembler does.
225 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
226 and rsqrdp opcodes to use the new field coding types.
228 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
230 * arm.h (CRC_EXT_ARMV8): New constant.
231 (ARCH_CRC_ARMV8): New macro.
233 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
235 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
237 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
238 Andrew Jenner <andrew@codesourcery.com>
240 Based on patches from Altera Corporation.
244 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
246 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
248 2013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
251 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
253 2013-01-24 Nick Clifton <nickc@redhat.com>
255 * v850.h: Add e3v5 support.
257 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
259 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
261 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
263 * ppc.h (PPC_OPCODE_POWER8): New define.
264 (PPC_OPCODE_HTM): Likewise.
266 2013-01-10 Will Newton <will.newton@imgtec.com>
270 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
272 * cr16.h (make_instruction): Rename to cr16_make_instruction.
273 (match_opcode): Rename to cr16_match_opcode.
275 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
277 * mips.h: Add support for r5900 instructions including lq and sq.
279 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
281 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
282 (make_instruction,match_opcode): Added function prototypes.
283 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
285 2012-11-23 Alan Modra <amodra@gmail.com>
287 * ppc.h (ppc_parse_cpu): Update prototype.
289 2012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
291 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
292 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
294 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
296 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
298 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
300 * ia64.h (ia64_opnd): Add new operand types.
302 2012-08-21 David S. Miller <davem@davemloft.net>
304 * sparc.h (F3F4): New macro.
306 2012-08-13 Ian Bolton <ian.bolton@arm.com>
307 Laurent Desnogues <laurent.desnogues@arm.com>
308 Jim MacArthur <jim.macarthur@arm.com>
309 Marcus Shawcroft <marcus.shawcroft@arm.com>
310 Nigel Stephens <nigel.stephens@arm.com>
311 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
312 Richard Earnshaw <rearnsha@arm.com>
313 Sofiane Naci <sofiane.naci@arm.com>
314 Tejas Belagod <tejas.belagod@arm.com>
315 Yufeng Zhang <yufeng.zhang@arm.com>
317 * aarch64.h: New file.
319 2012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
320 Maciej W. Rozycki <macro@codesourcery.com>
322 * mips.h (mips_opcode): Add the exclusions field.
323 (OPCODE_IS_MEMBER): Remove macro.
324 (cpu_is_member): New inline function.
325 (opcode_is_member): Likewise.
327 2012-07-31 Chao-Ying Fu <fu@mips.com>
328 Catherine Moore <clm@codesourcery.com>
329 Maciej W. Rozycki <macro@codesourcery.com>
331 * mips.h: Document microMIPS DSP ASE usage.
332 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
333 microMIPS DSP ASE support.
334 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
335 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
336 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
337 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
338 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
339 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
340 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
342 2012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
344 * mips.h: Fix a typo in description.
346 2012-06-07 Georg-Johann Lay <avr@gjlay.de>
348 * avr.h: (AVR_ISA_XCH): New define.
349 (AVR_ISA_XMEGA): Use it.
350 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
352 2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
354 * m68hc11.h: Add XGate definitions.
355 (struct m68hc11_opcode): Add xg_mask field.
357 2012-05-14 Catherine Moore <clm@codesourcery.com>
358 Maciej W. Rozycki <macro@codesourcery.com>
359 Rhonda Wittels <rhonda@codesourcery.com>
361 * ppc.h (PPC_OPCODE_VLE): New definition.
362 (PPC_OP_SA): New macro.
363 (PPC_OP_SE_VLE): New macro.
364 (PPC_OP): Use a variable shift amount.
365 (powerpc_operand): Update comments.
366 (PPC_OPSHIFT_INV): New macro.
367 (PPC_OPERAND_CR): Replace with...
368 (PPC_OPERAND_CR_BIT): ...this and
369 (PPC_OPERAND_CR_REG): ...this.
372 2012-05-03 Sean Keys <skeys@ipdatasys.com>
374 * xgate.h: Header file for XGATE assembler.
376 2012-04-27 David S. Miller <davem@davemloft.net>
378 * sparc.h: Document new arg code' )' for crypto RS3
381 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
382 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
383 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
384 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
385 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
386 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
387 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
388 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
389 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
390 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
391 HWCAP_CBCOND, HWCAP_CRC32): New defines.
393 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
395 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
397 2012-02-27 Alan Modra <amodra@gmail.com>
399 * crx.h (cst4_map): Update declaration.
401 2012-02-25 Walter Lee <walt@tilera.com>
403 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
405 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
406 TILEPRO_OPC_LW_TLS_SN.
408 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
410 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
411 (XRELEASE_PREFIX_OPCODE): Likewise.
413 2011-12-08 Andrew Pinski <apinski@cavium.com>
414 Adam Nemet <anemet@caviumnetworks.com>
416 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
417 (INSN_OCTEON2): New macro.
418 (CPU_OCTEON2): New macro.
419 (OPCODE_IS_MEMBER): Add Octeon2.
421 2011-11-29 Andrew Pinski <apinski@cavium.com>
423 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
424 (INSN_OCTEONP): New macro.
425 (CPU_OCTEONP): New macro.
426 (OPCODE_IS_MEMBER): Add Octeon+.
427 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
429 2011-11-01 DJ Delorie <dj@redhat.com>
433 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
435 * mips.h: Fix a typo in description.
437 2011-09-21 David S. Miller <davem@davemloft.net>
439 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
440 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
441 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
442 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
444 2011-08-09 Chao-ying Fu <fu@mips.com>
445 Maciej W. Rozycki <macro@codesourcery.com>
447 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
448 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
449 (INSN_ASE_MASK): Add the MCU bit.
450 (INSN_MCU): New macro.
451 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
452 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
454 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
456 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
457 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
458 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
459 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
460 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
461 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
462 (INSN2_READ_GPR_MMN): Likewise.
463 (INSN2_READ_FPR_D): Change the bit used.
464 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
465 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
466 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
467 (INSN2_COND_BRANCH): Likewise.
468 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
469 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
470 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
471 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
472 (INSN2_MOD_GPR_MN): Likewise.
474 2011-08-05 David S. Miller <davem@davemloft.net>
476 * sparc.h: Document new format codes '4', '5', and '('.
477 (OPF_LOW4, RS3): New macros.
479 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
481 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
482 order of flags documented.
484 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
486 * mips.h: Clarify the description of microMIPS instruction
488 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
490 2011-07-24 Chao-ying Fu <fu@mips.com>
491 Maciej W. Rozycki <macro@codesourcery.com>
493 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
494 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
495 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
496 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
497 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
498 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
499 (OP_MASK_RS3, OP_SH_RS3): Likewise.
500 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
501 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
502 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
503 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
504 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
505 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
506 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
507 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
508 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
509 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
510 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
511 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
512 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
513 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
514 (INSN_WRITE_GPR_S): New macro.
515 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
516 (INSN2_READ_FPR_D): Likewise.
517 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
518 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
519 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
520 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
521 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
522 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
523 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
524 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
525 (CPU_MICROMIPS): New macro.
526 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
527 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
528 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
529 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
530 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
531 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
532 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
533 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
534 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
535 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
536 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
537 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
538 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
539 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
540 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
541 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
542 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
543 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
544 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
545 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
546 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
547 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
548 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
549 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
550 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
551 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
552 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
553 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
554 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
555 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
556 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
557 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
558 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
559 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
560 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
561 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
562 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
563 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
564 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
565 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
566 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
567 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
568 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
569 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
570 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
571 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
572 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
573 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
574 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
575 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
576 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
577 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
578 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
579 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
580 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
581 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
582 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
583 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
584 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
585 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
586 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
587 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
588 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
589 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
590 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
591 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
592 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
593 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
594 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
595 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
596 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
597 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
598 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
599 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
600 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
601 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
602 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
603 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
604 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
605 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
606 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
607 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
608 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
609 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
610 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
611 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
612 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
613 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
614 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
615 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
616 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
617 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
618 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
619 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
620 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
621 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
622 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
623 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
624 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
625 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
626 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
627 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
628 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
629 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
630 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
631 (micromips_opcodes): New declaration.
632 (bfd_micromips_num_opcodes): Likewise.
634 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
636 * mips.h (INSN_TRAP): Rename to...
637 (INSN_NO_DELAY_SLOT): ... this.
638 (INSN_SYNC): Remove macro.
640 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
642 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
643 a duplicate of AVR_ISA_SPM.
645 2011-07-01 Nick Clifton <nickc@redhat.com>
647 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
649 2011-06-18 Robin Getz <robin.getz@analog.com>
651 * bfin.h (is_macmod_signed): New func
653 2011-06-18 Mike Frysinger <vapier@gentoo.org>
655 * bfin.h (is_macmod_pmove): Add missing space before func args.
656 (is_macmod_hmove): Likewise.
658 2011-06-13 Walter Lee <walt@tilera.com>
660 * tilegx.h: New file.
661 * tilepro.h: New file.
663 2011-05-31 Paul Brook <paul@codesourcery.com>
665 * arm.h (ARM_ARCH_V7R_IDIV): Define.
667 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
669 * s390.h: Replace S390_OPERAND_REG_EVEN with
670 S390_OPERAND_REG_PAIR.
672 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
674 * s390.h: Add S390_OPCODE_REG_EVEN flag.
676 2011-04-18 Julian Brown <julian@codesourcery.com>
678 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
680 2011-04-11 Dan McDonald <dan@wellkeeper.com>
683 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
685 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
687 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
688 New instruction set flags.
689 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
691 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
693 * mips.h (M_PREF_AB): New enum value.
695 2011-02-12 Mike Frysinger <vapier@gentoo.org>
697 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
699 (is_macmod_pmove, is_macmod_hmove): New functions.
701 2011-02-11 Mike Frysinger <vapier@gentoo.org>
703 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
705 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
707 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
708 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
710 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
713 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
716 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
719 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
721 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
723 * mips.h: Update commentary after last commit.
725 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
727 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
728 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
729 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
731 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
733 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
735 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
737 * mips.h: Fix previous commit.
739 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
741 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
742 (INSN_LOONGSON_3A): Clear bit 31.
744 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
747 * arm.h (ARM_AEXT_V6M_ONLY): New define.
748 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
749 (ARM_ARCH_V6M_ONLY): New define.
751 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
753 * mips.h (INSN_LOONGSON_3A): Defined.
754 (CPU_LOONGSON_3A): Defined.
755 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
757 2010-10-09 Matt Rice <ratmice@gmail.com>
759 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
760 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
762 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
764 * arm.h (ARM_EXT_VIRT): New define.
765 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
766 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
769 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
771 * arm.h (ARM_AEXT_ADIV): New define.
772 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
774 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
776 * arm.h (ARM_EXT_OS): New define.
777 (ARM_AEXT_V6SM): Likewise.
778 (ARM_ARCH_V6SM): Likewise.
780 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
782 * arm.h (ARM_EXT_MP): Add.
783 (ARM_ARCH_V7A_MP): Likewise.
785 2010-09-22 Mike Frysinger <vapier@gentoo.org>
787 * bfin.h: Declare pseudoChr structs/defines.
789 2010-09-21 Mike Frysinger <vapier@gentoo.org>
791 * bfin.h: Strip trailing whitespace.
793 2010-07-29 DJ Delorie <dj@redhat.com>
795 * rx.h (RX_Operand_Type): Add TwoReg.
796 (RX_Opcode_ID): Remove ediv and ediv2.
798 2010-07-27 DJ Delorie <dj@redhat.com>
800 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
802 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
803 Ina Pandit <ina.pandit@kpitcummins.com>
805 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
806 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
807 PROCESSOR_V850E2_ALL.
808 Remove PROCESSOR_V850EA support.
809 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
810 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
811 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
812 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
813 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
814 V850_OPERAND_PERCENT.
815 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
817 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
820 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
822 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
823 (MIPS16_INSN_BRANCH): Rename to...
824 (MIPS16_INSN_COND_BRANCH): ... this.
826 2010-07-03 Alan Modra <amodra@gmail.com>
828 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
829 Renumber other PPC_OPCODE defines.
831 2010-07-03 Alan Modra <amodra@gmail.com>
833 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
835 2010-06-29 Alan Modra <amodra@gmail.com>
837 * maxq.h: Delete file.
839 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
841 * ppc.h (PPC_OPCODE_E500): Define.
843 2010-05-26 Catherine Moore <clm@codesourcery.com>
845 * opcode/mips.h (INSN_MIPS16): Remove.
847 2010-04-21 Joseph Myers <joseph@codesourcery.com>
849 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
851 2010-04-15 Nick Clifton <nickc@redhat.com>
853 * alpha.h: Update copyright notice to use GPLv3.
859 * convex.h: Likewise.
873 * m68hc11.h: Likewise.
879 * mn10200.h: Likewise.
880 * mn10300.h: Likewise.
881 * msp430.h: Likewise.
892 * score-datadep.h: Likewise.
893 * score-inst.h: Likewise.
895 * spu-insns.h: Likewise.
899 * tic54x.h: Likewise.
904 2010-03-25 Joseph Myers <joseph@codesourcery.com>
906 * tic6x-control-registers.h, tic6x-insn-formats.h,
907 tic6x-opcode-table.h, tic6x.h: New.
909 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
911 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
913 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
915 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
917 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
919 * ia64.h (ia64_find_opcode): Remove argument name.
920 (ia64_find_next_opcode): Likewise.
921 (ia64_dis_opcode): Likewise.
922 (ia64_free_opcode): Likewise.
923 (ia64_find_dependency): Likewise.
925 2009-11-22 Doug Evans <dje@sebabeach.org>
927 * cgen.h: Include bfd_stdint.h.
928 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
930 2009-11-18 Paul Brook <paul@codesourcery.com>
932 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
934 2009-11-17 Paul Brook <paul@codesourcery.com>
935 Daniel Jacobowitz <dan@codesourcery.com>
937 * arm.h (ARM_EXT_V6_DSP): Define.
938 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
939 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
941 2009-11-04 DJ Delorie <dj@redhat.com>
943 * rx.h (rx_decode_opcode) (mvtipl): Add.
944 (mvtcp, mvfcp, opecp): Remove.
946 2009-11-02 Paul Brook <paul@codesourcery.com>
948 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
949 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
950 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
951 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
952 FPU_ARCH_NEON_VFP_V4): Define.
954 2009-10-23 Doug Evans <dje@sebabeach.org>
956 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
957 * cgen.h: Update. Improve multi-inclusion macro name.
959 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
961 * ppc.h (PPC_OPCODE_476): Define.
963 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
965 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
967 2009-09-29 DJ Delorie <dj@redhat.com>
971 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
973 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
975 2009-09-21 Ben Elliston <bje@au.ibm.com>
977 * ppc.h (PPC_OPCODE_PPCA2): New.
979 2009-09-05 Martin Thuresson <martin@mtme.org>
981 * ia64.h (struct ia64_operand): Renamed member class to op_class.
983 2009-08-29 Martin Thuresson <martin@mtme.org>
985 * tic30.h (template): Rename type template to
986 insn_template. Updated code to use new name.
987 * tic54x.h (template): Rename type template to
990 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
992 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
994 2009-06-11 Anthony Green <green@moxielogic.com>
996 * moxie.h (MOXIE_F3_PCREL): Define.
997 (moxie_form3_opc_info): Grow.
999 2009-06-06 Anthony Green <green@moxielogic.com>
1001 * moxie.h (MOXIE_F1_M): Define.
1003 2009-04-15 Anthony Green <green@moxielogic.com>
1007 2009-04-06 DJ Delorie <dj@redhat.com>
1009 * h8300.h: Add relaxation attributes to MOVA opcodes.
1011 2009-03-10 Alan Modra <amodra@bigpond.net.au>
1013 * ppc.h (ppc_parse_cpu): Declare.
1015 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
1017 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1018 and _IMM11 for mbitclr and mbitset.
1019 * score-datadep.h: Update dependency information.
1021 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
1023 * ppc.h (PPC_OPCODE_POWER7): New.
1025 2009-02-06 Doug Evans <dje@google.com>
1027 * i386.h: Add comment regarding sse* insns and prefixes.
1029 2009-02-03 Sandip Matte <sandip@rmicorp.com>
1031 * mips.h (INSN_XLR): Define.
1032 (INSN_CHIP_MASK): Update.
1034 (OPCODE_IS_MEMBER): Update.
1035 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1037 2009-01-28 Doug Evans <dje@google.com>
1039 * opcode/i386.h: Add multiple inclusion protection.
1040 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1041 (EDI_REG_NUM): New macros.
1042 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1043 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1044 (REX_PREFIX_P): New macro.
1046 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
1048 * ppc.h (struct powerpc_opcode): New field "deprecated".
1049 (PPC_OPCODE_NOPOWER4): Delete.
1051 2008-11-28 Joshua Kinard <kumba@gentoo.org>
1053 * mips.h: Define CPU_R14000, CPU_R16000.
1054 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
1056 2008-11-18 Catherine Moore <clm@codesourcery.com>
1058 * arm.h (FPU_NEON_FP16): New.
1059 (FPU_ARCH_NEON_FP16): New.
1061 2008-11-06 Chao-ying Fu <fu@mips.com>
1063 * mips.h: Doucument '1' for 5-bit sync type.
1065 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1067 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1070 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1072 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1074 2008-07-30 Michael J. Eager <eager@eagercon.com>
1076 * ppc.h (PPC_OPCODE_405): Define.
1077 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1079 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1081 * ppc.h (ppc_cpu_t): New typedef.
1082 (struct powerpc_opcode <flags>): Use it.
1083 (struct powerpc_operand <insert, extract>): Likewise.
1084 (struct powerpc_macro <flags>): Likewise.
1086 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1088 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1089 Update comment before MIPS16 field descriptors to mention MIPS16.
1090 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1092 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1093 New bit masks and shift counts for cins and exts.
1095 * mips.h: Document new field descriptors +Q.
1096 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1098 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1100 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
1101 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1103 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
1105 * ppc.h: (PPC_OPCODE_E500MC): New.
1107 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1109 * i386.h (MAX_OPERANDS): Set to 5.
1110 (MAX_MNEM_SIZE): Changed to 20.
1112 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1114 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1116 2008-03-09 Paul Brook <paul@codesourcery.com>
1118 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1120 2008-03-04 Paul Brook <paul@codesourcery.com>
1122 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1123 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1124 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1126 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
1127 Nick Clifton <nickc@redhat.com>
1130 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1131 with a 32-bit displacement but without the top bit of the 4th byte
1134 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1136 * cr16.h (cr16_num_optab): Declared.
1138 2008-02-14 Hakan Ardo <hakan@debian.org>
1141 * avr.h (AVR_ISA_2xxe): Define.
1143 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1145 * mips.h: Update copyright.
1146 (INSN_CHIP_MASK): New macro.
1147 (INSN_OCTEON): New macro.
1148 (CPU_OCTEON): New macro.
1149 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1151 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1153 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1155 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1157 * avr.h (AVR_ISA_USB162): Add new opcode set.
1158 (AVR_ISA_AVR3): Likewise.
1160 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1162 * mips.h (INSN_LOONGSON_2E): New.
1163 (INSN_LOONGSON_2F): New.
1164 (CPU_LOONGSON_2E): New.
1165 (CPU_LOONGSON_2F): New.
1166 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1168 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1170 * mips.h (INSN_ISA*): Redefine certain values as an
1171 enumeration. Update comments.
1172 (mips_isa_table): New.
1173 (ISA_MIPS*): Redefine to match enumeration.
1174 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1177 2007-08-08 Ben Elliston <bje@au.ibm.com>
1179 * ppc.h (PPC_OPCODE_PPCPS): New.
1181 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1183 * m68k.h: Document j K & E.
1185 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1187 * cr16.h: New file for CR16 target.
1189 2007-05-02 Alan Modra <amodra@bigpond.net.au>
1191 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1193 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1195 * m68k.h (mcfisa_c): New.
1196 (mcfusp, mcf_mask): Adjust.
1198 2007-04-20 Alan Modra <amodra@bigpond.net.au>
1200 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1201 (num_powerpc_operands): Declare.
1202 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1203 (PPC_OPERAND_PLUS1): Define.
1205 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
1207 * i386.h (REX_MODE64): Renamed to ...
1209 (REX_EXTX): Renamed to ...
1211 (REX_EXTY): Renamed to ...
1213 (REX_EXTZ): Renamed to ...
1216 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1218 * i386.h: Add entries from config/tc-i386.h and move tables
1219 to opcodes/i386-opc.h.
1221 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1223 * i386.h (FloatDR): Removed.
1224 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1226 2007-03-01 Alan Modra <amodra@bigpond.net.au>
1228 * spu-insns.h: Add soma double-float insns.
1230 2007-02-20 Thiemo Seufer <ths@mips.com>
1231 Chao-Ying Fu <fu@mips.com>
1233 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1234 (INSN_DSPR2): Add flag for DSP R2 instructions.
1235 (M_BALIGN): New macro.
1237 2007-02-14 Alan Modra <amodra@bigpond.net.au>
1239 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1240 and Seg3ShortFrom with Shortform.
1242 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1245 * i386.h (i386_optab): Put the real "test" before the pseudo
1248 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
1250 * m68k.h (m68010up): OR fido_a.
1252 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
1254 * m68k.h (fido_a): New.
1256 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
1258 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1259 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1262 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1264 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1266 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1268 * score-inst.h (enum score_insn_type): Add Insn_internal.
1270 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1271 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1272 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1273 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1274 Alan Modra <amodra@bigpond.net.au>
1276 * spu-insns.h: New file.
1279 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1281 * ppc.h (PPC_OPCODE_CELL): Define.
1283 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1285 * i386.h : Modify opcode to support for the change in POPCNT opcode
1286 in amdfam10 architecture.
1288 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1290 * i386.h: Replace CpuMNI with CpuSSSE3.
1292 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
1293 Joseph Myers <joseph@codesourcery.com>
1294 Ian Lance Taylor <ian@wasabisystems.com>
1295 Ben Elliston <bje@wasabisystems.com>
1297 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1299 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1301 * score-datadep.h: New file.
1302 * score-inst.h: New file.
1304 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1306 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1307 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1308 movdq2q and movq2dq.
1310 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1311 Michael Meissner <michael.meissner@amd.com>
1313 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1315 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1317 * i386.h (i386_optab): Add "nop" with memory reference.
1319 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1321 * i386.h (i386_optab): Update comment for 64bit NOP.
1323 2006-06-06 Ben Elliston <bje@au.ibm.com>
1324 Anton Blanchard <anton@samba.org>
1326 * ppc.h (PPC_OPCODE_POWER6): Define.
1329 2006-06-05 Thiemo Seufer <ths@mips.com>
1331 * mips.h: Improve description of MT flags.
1333 2006-05-25 Richard Sandiford <richard@codesourcery.com>
1335 * m68k.h (mcf_mask): Define.
1337 2006-05-05 Thiemo Seufer <ths@mips.com>
1338 David Ung <davidu@mips.com>
1340 * mips.h (enum): Add macro M_CACHE_AB.
1342 2006-05-04 Thiemo Seufer <ths@mips.com>
1343 Nigel Stephens <nigel@mips.com>
1344 David Ung <davidu@mips.com>
1346 * mips.h: Add INSN_SMARTMIPS define.
1348 2006-04-30 Thiemo Seufer <ths@mips.com>
1349 David Ung <davidu@mips.com>
1351 * mips.h: Defines udi bits and masks. Add description of
1352 characters which may appear in the args field of udi
1355 2006-04-26 Thiemo Seufer <ths@networkno.de>
1357 * mips.h: Improve comments describing the bitfield instruction
1360 2006-04-26 Julian Brown <julian@codesourcery.com>
1362 * arm.h (FPU_VFP_EXT_V3): Define constant.
1363 (FPU_NEON_EXT_V1): Likewise.
1364 (FPU_VFP_HARD): Update.
1365 (FPU_VFP_V3): Define macro.
1366 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1368 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
1370 * avr.h (AVR_ISA_PWMx): New.
1372 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1374 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1375 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1376 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1377 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1378 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1380 2006-03-10 Paul Brook <paul@codesourcery.com>
1382 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1384 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1386 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1387 first. Correct mask of bb "B" opcode.
1389 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1391 * i386.h (i386_optab): Support Intel Merom New Instructions.
1393 2006-02-24 Paul Brook <paul@codesourcery.com>
1395 * arm.h: Add V7 feature bits.
1397 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1399 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1401 2006-01-31 Paul Brook <paul@codesourcery.com>
1402 Richard Earnshaw <rearnsha@arm.com>
1404 * arm.h: Use ARM_CPU_FEATURE.
1405 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1406 (arm_feature_set): Change to a structure.
1407 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1408 ARM_FEATURE): New macros.
1410 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
1412 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1413 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1414 (ADD_PC_INCR_OPCODE): Don't define.
1416 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1419 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1421 2005-11-14 David Ung <davidu@mips.com>
1423 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1424 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1425 save/restore encoding of the args field.
1427 2005-10-28 Dave Brolley <brolley@redhat.com>
1429 Contribute the following changes:
1430 2005-02-16 Dave Brolley <brolley@redhat.com>
1432 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1433 cgen_isa_mask_* to cgen_bitset_*.
1436 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1438 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1439 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1440 (CGEN_CPU_TABLE): Make isas a ponter.
1442 2003-09-29 Dave Brolley <brolley@redhat.com>
1444 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1445 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1446 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1448 2002-12-13 Dave Brolley <brolley@redhat.com>
1450 * cgen.h (symcat.h): #include it.
1451 (cgen-bitset.h): #include it.
1452 (CGEN_ATTR_VALUE_TYPE): Now a union.
1453 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1454 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1455 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1456 * cgen-bitset.h: New file.
1458 2005-09-30 Catherine Moore <clm@cm00re.com>
1462 2005-10-24 Jan Beulich <jbeulich@novell.com>
1464 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1467 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1469 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1470 Add FLAG_STRICT to pa10 ftest opcode.
1472 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1474 * hppa.h (pa_opcodes): Remove lha entries.
1476 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1478 * hppa.h (FLAG_STRICT): Revise comment.
1479 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1480 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1483 2005-09-30 Catherine Moore <clm@cm00re.com>
1487 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1489 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1491 2005-09-06 Chao-ying Fu <fu@mips.com>
1493 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1494 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1496 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1497 (INSN_ASE_MASK): Update to include INSN_MT.
1498 (INSN_MT): New define for MT ASE.
1500 2005-08-25 Chao-ying Fu <fu@mips.com>
1502 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1503 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1504 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1505 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1506 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1507 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1509 (INSN_DSP): New define for DSP ASE.
1511 2005-08-18 Alan Modra <amodra@bigpond.net.au>
1515 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1517 * ppc.h (PPC_OPCODE_E300): Define.
1519 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1521 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1523 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1526 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1529 2005-07-27 Jan Beulich <jbeulich@novell.com>
1531 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1532 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1533 Add movq-s as 64-bit variants of movd-s.
1535 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1537 * hppa.h: Fix punctuation in comment.
1539 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1540 implicit space-register addressing. Set space-register bits on opcodes
1541 using implicit space-register addressing. Add various missing pa20
1542 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1543 space-register addressing. Use "fE" instead of "fe" in various
1546 2005-07-18 Jan Beulich <jbeulich@novell.com>
1548 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1550 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1552 * i386.h (i386_optab): Support Intel VMX Instructions.
1554 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1556 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1558 2005-07-05 Jan Beulich <jbeulich@novell.com>
1560 * i386.h (i386_optab): Add new insns.
1562 2005-07-01 Nick Clifton <nickc@redhat.com>
1564 * sparc.h: Add typedefs to structure declarations.
1566 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1569 * i386.h (i386_optab): Update comments for 64bit addressing on
1570 mov. Allow 64bit addressing for mov and movq.
1572 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1574 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1575 respectively, in various floating-point load and store patterns.
1577 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1579 * hppa.h (FLAG_STRICT): Correct comment.
1580 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1581 PA 2.0 mneumonics when equivalent. Entries with cache control
1582 completers now require PA 1.1. Adjust whitespace.
1584 2005-05-19 Anton Blanchard <anton@samba.org>
1586 * ppc.h (PPC_OPCODE_POWER5): Define.
1588 2005-05-10 Nick Clifton <nickc@redhat.com>
1590 * Update the address and phone number of the FSF organization in
1591 the GPL notices in the following files:
1592 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1593 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1594 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1595 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1596 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1597 tic54x.h, tic80.h, v850.h, vax.h
1599 2005-05-09 Jan Beulich <jbeulich@novell.com>
1601 * i386.h (i386_optab): Add ht and hnt.
1603 2005-04-18 Mark Kettenis <kettenis@gnu.org>
1605 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1606 Add xcrypt-ctr. Provide aliases without hyphens.
1608 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1610 Moved from ../ChangeLog
1612 2005-04-12 Paul Brook <paul@codesourcery.com>
1613 * m88k.h: Rename psr macros to avoid conflicts.
1615 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1616 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1617 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1618 and ARM_ARCH_V6ZKT2.
1620 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1621 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1622 Remove redundant instruction types.
1623 (struct argument): X_op - new field.
1624 (struct cst4_entry): Remove.
1625 (no_op_insn): Declare.
1627 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1628 * crx.h (enum argtype): Rename types, remove unused types.
1630 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1631 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1632 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1633 (enum operand_type): Rearrange operands, edit comments.
1634 replace us<N> with ui<N> for unsigned immediate.
1635 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1636 displacements (respectively).
1637 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1638 (instruction type): Add NO_TYPE_INS.
1639 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1640 (operand_entry): New field - 'flags'.
1641 (operand flags): New.
1643 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1644 * crx.h (operand_type): Remove redundant types i3, i4,
1646 Add new unsigned immediate types us3, us4, us5, us16.
1648 2005-04-12 Mark Kettenis <kettenis@gnu.org>
1650 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1651 adjust them accordingly.
1653 2005-04-01 Jan Beulich <jbeulich@novell.com>
1655 * i386.h (i386_optab): Add rdtscp.
1657 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1659 * i386.h (i386_optab): Don't allow the `l' suffix for moving
1660 between memory and segment register. Allow movq for moving between
1661 general-purpose register and segment register.
1663 2005-02-09 Jan Beulich <jbeulich@novell.com>
1666 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1667 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1670 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1672 * m68k.h (m68008, m68ec030, m68882): Remove.
1674 (cpu_m68k, cpu_cf): New.
1675 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1676 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1678 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
1680 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1681 * cgen.h (enum cgen_parse_operand_type): Add
1682 CGEN_PARSE_OPERAND_SYMBOLIC.
1684 2005-01-21 Fred Fish <fnf@specifixinc.com>
1686 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1687 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1688 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1690 2005-01-19 Fred Fish <fnf@specifixinc.com>
1692 * mips.h (struct mips_opcode): Add new pinfo2 member.
1693 (INSN_ALIAS): New define for opcode table entries that are
1694 specific instances of another entry, such as 'move' for an 'or'
1695 with a zero operand.
1696 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1697 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1699 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1701 * mips.h (CPU_RM9000): Define.
1702 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1704 2004-11-25 Jan Beulich <jbeulich@novell.com>
1706 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1707 to/from test registers are illegal in 64-bit mode. Add missing
1708 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1709 (previously one had to explicitly encode a rex64 prefix). Re-enable
1710 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1711 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1713 2004-11-23 Jan Beulich <jbeulich@novell.com>
1715 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1716 available only with SSE2. Change the MMX additions introduced by SSE
1717 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1718 instructions by their now designated identifier (since combining i686
1719 and 3DNow! does not really imply 3DNow!A).
1721 2004-11-19 Alan Modra <amodra@bigpond.net.au>
1723 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1724 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1726 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1727 Vineet Sharma <vineets@noida.hcltech.com>
1729 * maxq.h: New file: Disassembly information for the maxq port.
1731 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1733 * i386.h (i386_optab): Put back "movzb".
1735 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
1737 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1738 comments. Remove member cris_ver_sim. Add members
1739 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1740 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1741 (struct cris_support_reg, struct cris_cond15): New types.
1742 (cris_conds15): Declare.
1743 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1744 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1745 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1746 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1747 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1748 SIZE_FIELD_UNSIGNED.
1750 2004-11-04 Jan Beulich <jbeulich@novell.com>
1752 * i386.h (sldx_Suf): Remove.
1753 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1754 (q_FP): Define, implying no REX64.
1755 (x_FP, sl_FP): Imply FloatMF.
1756 (i386_optab): Split reg and mem forms of moving from segment registers
1757 so that the memory forms can ignore the 16-/32-bit operand size
1758 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1759 all non-floating-point instructions. Unite 32- and 64-bit forms of
1760 movsx, movzx, and movd. Adjust floating point operations for the above
1761 changes to the *FP macros. Add DefaultSize to floating point control
1762 insns operating on larger memory ranges. Remove left over comments
1763 hinting at certain insns being Intel-syntax ones where the ones
1764 actually meant are already gone.
1766 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1768 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1771 2004-09-30 Paul Brook <paul@codesourcery.com>
1773 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1774 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1776 2004-09-11 Theodore A. Roth <troth@openavr.org>
1778 * avr.h: Add support for
1779 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1781 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1783 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1785 2004-08-24 Dmitry Diky <diwil@spec.ru>
1787 * msp430.h (msp430_opc): Add new instructions.
1788 (msp430_rcodes): Declare new instructions.
1789 (msp430_hcodes): Likewise..
1791 2004-08-13 Nick Clifton <nickc@redhat.com>
1794 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1797 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1799 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1801 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1803 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1805 2004-07-21 Jan Beulich <jbeulich@novell.com>
1807 * i386.h: Adjust instruction descriptions to better match the
1810 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
1812 * arm.h: Remove all old content. Replace with architecture defines
1813 from gas/config/tc-arm.c.
1815 2004-07-09 Andreas Schwab <schwab@suse.de>
1817 * m68k.h: Fix comment.
1819 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1823 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1825 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1827 2004-05-24 Peter Barada <peter@the-baradas.com>
1829 * m68k.h: Add 'size' to m68k_opcode.
1831 2004-05-05 Peter Barada <peter@the-baradas.com>
1833 * m68k.h: Switch from ColdFire chip name to core variant.
1835 2004-04-22 Peter Barada <peter@the-baradas.com>
1837 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1838 descriptions for new EMAC cases.
1839 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1840 handle Motorola MAC syntax.
1841 Allow disassembly of ColdFire V4e object files.
1843 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1845 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1847 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1849 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1851 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1853 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1855 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1857 * i386.h (i386_optab): Added xstore/xcrypt insns.
1859 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1861 * h8300.h (32bit ldc/stc): Add relaxing support.
1863 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1865 * h8300.h (BITOP): Pass MEMRELAX flag.
1867 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1869 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1872 For older changes see ChangeLog-9103
1874 Copyright (C) 2004-2012 Free Software Foundation, Inc.
1876 Copying and distribution of this file, with or without modification,
1877 are permitted in any medium without royalty provided the copyright
1878 notice and this notice are preserved.
1884 version-control: never